CN116301282A - Low-power consumption control method and device for multi-core processor chip - Google Patents
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Abstract
The invention provides a low-power consumption control method and device of a multi-core processor chip, and relates to the technical field of computer chips. The method comprises the following steps: acquiring the chip temperature of a multi-core processor chip; when the temperature of the chip reaches a first temperature threshold value and is smaller than a second temperature threshold value, radiating the multi-core processor chip; when the temperature of the chip reaches a second temperature threshold value and is smaller than the safety temperature, acquiring the power consumption of the multi-core processor chip, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the temperature of the chip while carrying out heat dissipation treatment to obtain an optimal power consumption strategy; and controlling each single core in the multi-core processor chip according to the optimal power consumption strategy. The scheme can effectively realize low-power consumption control of the multi-core processor chip and optimize the computing performance of the multi-core processor chip.
Description
Technical Field
The present invention relates to the field of computer chips, and in particular, to a method and apparatus for controlling low power consumption of a multi-core processor chip.
Background
With the rapid development of chip technology and the application of some special scenes, low-power consumption technology is increasingly emphasized. The multi-core processor chip has high working frequency, high system integration level and greatly improved power consumption, so that a series of practical problems are brought. The increase of the chip operation temperature caused by the increase of the power consumption can cause the drift of semiconductor parameters, influence the normal operation of the chip, reduce the reliability of the chip and increase the failure risk of the chip; and meanwhile, the service life of the chip can be shortened due to the rising of the operating temperature, and the system performance is further limited. Therefore, power consumption has become an important factor restricting the improvement of chip performance.
Disclosure of Invention
The invention provides a low-power consumption control method and device for a multi-core processor chip.
In a first aspect, an embodiment of the present invention provides a low power consumption control method of a multicore processor chip, including:
acquiring the chip temperature of a multi-core processor chip;
when the temperature of the chip reaches a first temperature threshold value and is smaller than a second temperature threshold value, radiating the multi-core processor chip;
when the chip temperature reaches the second temperature threshold and is smaller than the safety temperature, acquiring the power consumption of the multi-core processor chip, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while carrying out heat dissipation processing to obtain an optimal power consumption strategy;
and controlling each single core in the multi-core processor chip according to the optimal power consumption strategy.
Optionally, the performing dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature to obtain an optimal power consumption policy includes:
s1: acquiring an action space of the multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
Optionally, the obtaining a bonus factor according to the first state includes:
comparing the power consumption of the first state with the power consumption of the current state;
if the power consumption of the first state is smaller than that of the current state, a positive rewarding factor is given;
and if the power consumption of the first state is not smaller than that of the current state, giving a negative rewarding factor.
Optionally, the method further comprises:
constructing a gradient rewarding mapping relation; wherein, the rewarding factors corresponding to different states of the multi-core processor chip are different;
acquiring theoretical accumulated instruction execution number of the multi-core heterogeneous chip running for a specified duration at the safe temperature;
each interval the specified duration is executed: calculating the actual accumulated instruction number executed by the multi-core heterogeneous chip within the appointed time length; performing difference operation on the actual accumulated instruction number and the theoretical accumulated instruction execution number to obtain an instruction difference; giving a reward factor to the multi-core heterogeneous chip according to the instruction difference value; wherein the bonus factor is positively correlated with the instruction difference.
Optionally, the determining the optimal power consumption policy includes:
s71: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and the training model, and determining a second power consumption strategy so that the multi-core heterogeneous chip runs the second power consumption strategy;
s72: determining a second state in which the multi-core heterogeneous chip runs the second power consumption strategy, and judging whether the chip temperature in the second state is greater than a preset temperature threshold;
if yes, adding one to the last counted number of curtains to obtain the counted number of curtains, judging whether the counted number of curtains is equal to a preset training curtain number threshold value, and if yes, obtaining an optimal power consumption strategy; if not, returning to S71;
if not, returning to S71;
wherein the preset temperature threshold is lower than the safety temperature, and the preset temperature threshold is determined by the following formula:
wherein,,T y for characterizing the preset temperature threshold value,T a for the characterization of the safety temperature in question,εfor characterizing the heating coefficient of the multi-core processor chip,Pfor characterizing the power consumption in said second state,P s for characterizing the heat dissipation power consumption of the multi-core processor chip,tfor characterizing the time interval during which said dynamic power consumption management is performed,cfor characterizing the heat capacity of the multi-core processor chip,mfor characterizing the quality of the multicore processor chip.
Optionally, the method further comprises:
and clock synchronization among single cores in the multi-core processor chip is realized by adopting a de-skew phase-locked loop.
In a second aspect, an embodiment of the present invention further provides a low power consumption control device of a multicore processor chip, including:
the acquisition module is used for acquiring the chip temperature of the multi-core processor chip;
the heat dissipation module is used for conducting heat dissipation treatment on the multi-core processor chip when the temperature of the chip reaches a first temperature threshold value and is smaller than a second temperature threshold value;
the power consumption management module is used for acquiring the power consumption of the multi-core processor chip when the chip temperature reaches a second temperature threshold and is smaller than the safety temperature, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while carrying out heat dissipation processing to obtain an optimal power consumption strategy so as to control each single core in the multi-core processor chip according to the optimal power consumption strategy.
Optionally, the power consumption management module is configured to perform the following operations:
s1: acquiring an action space of the multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
In a third aspect, an embodiment of the present invention further provides a computing device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the low power consumption control method of any one of the foregoing multi-core processor chips is implemented.
In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed in a computer, causes the computer to execute the low power consumption control method of the multi-core processor chip described in any one of the above.
The embodiment of the invention provides a low-power consumption control method and a device for a multi-core processor chip, which combine heat dissipation and dynamic power consumption management, only perform heat dissipation when the chip temperature is higher, and perform dynamic power consumption management on the multi-core processor chip on the basis of heat dissipation in time when the chip temperature is higher than a second temperature threshold and lower than a safe temperature to obtain an optimal power consumption strategy, so that each single core is controlled through the optimal power consumption strategy to further reduce the chip temperature of the current multi-core processor chip, effectively realize low-power consumption control of the multi-core processor chip, and optimize the calculation performance of the multi-core processor chip through dynamic regulation.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for controlling low power consumption of a multi-core processor chip according to an embodiment of the present invention;
FIG. 2 is a hardware architecture diagram of a computing device according to one embodiment of the present invention;
fig. 3 is a block diagram of a low power consumption control device of a multi-core processor chip according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a low power consumption control method of a multi-core processor chip, where the method includes:
102, performing heat dissipation treatment on a multi-core processor chip in response to the chip temperature reaching a first temperature threshold and being smaller than a second temperature threshold;
104, acquiring the power consumption of the multi-core processor chip when the chip temperature reaches a second temperature threshold and is smaller than the safety temperature, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while carrying out heat dissipation treatment to obtain an optimal power consumption strategy;
and step 106, controlling each single core in the multi-core processor chip according to the optimal power consumption strategy.
The first temperature threshold value is less than the second temperature threshold value is less than the safety temperature.
In the embodiment of the invention, by combining heat dissipation and dynamic power consumption management, only heat dissipation is performed when the chip temperature is higher, and real-time dynamic power consumption management is performed on the multi-core processor chip on the basis of heat dissipation in time when the chip temperature is higher than the second temperature threshold and lower than the safety temperature, so that an optimal power consumption strategy is obtained, and each single core is controlled through the optimal power consumption strategy, so that the chip temperature of the current multi-core processor chip is further reduced, the low power consumption control of the multi-core processor chip is effectively realized, and the calculation performance of the multi-core processor chip is optimized through dynamic regulation and control.
The manner in which the individual steps shown in fig. 1 are performed is described below.
First, for step 102, when the chip temperature reaches a first temperature threshold and is less than a second temperature threshold, heat dissipation processing is performed on the multicore processor chip.
In the invention, when the first temperature threshold value is reached and is smaller than the second temperature threshold value, the heat dissipation device is started to conduct heat dissipation treatment on the multi-core processor chip, so that the heat dissipation on the multi-core processor chip is realized through an external physical heat dissipation mode, the chip temperature of the multi-core processor chip is further reduced, and the performance of the multi-core processor chip is prevented from being limited by the excessively high chip temperature.
Aiming at step 104, dynamic power consumption management is performed on the multi-core processor chip according to power consumption and chip temperature to obtain an optimal power consumption strategy, including:
s1: acquiring an action space of a multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
It should be noted that, the action space includes a frequency and a voltage level that are configurable by each single core, and one power consumption policy includes a frequency and a voltage level of at least one single core. For example, the power consumption policy a is to set the frequency of the single core 1 to f 1 The voltage level is set to V 1 The method comprises the steps of carrying out a first treatment on the surface of the The power consumption policy b is to set the frequency of the single core 1 to f 1 The voltage level is set to V 3 The method comprises the steps of carrying out a first treatment on the surface of the The power consumption policy c is to set the frequency of the single core 1 to f 2 The voltage level is set to V 1 The method comprises the steps of carrying out a first treatment on the surface of the The power consumption policy d is to set the frequency of the single core 1 to f 1 The voltage level is set to V 1 And setting the frequency of the single core 2Put to f 1 The voltage level is set to V 5 。
In the invention, the frequency and voltage level of each single core in the multi-core processor chip are adjusted to influence the current running state and performance and the running state at the next moment, so that a deep Q network is adopted, a target Q value is calculated by using a target network updated after delay, the stability and convergence of network training are greatly improved, the expression capacity and learning efficiency of a model are improved, and an optimal power consumption strategy is provided for reducing the power consumption optimization calculation performance of the multi-core processor chip.
More specifically, a training model is used for combining epsilon-greedy strategies at intervals for determining an optimal power consumption strategy, and the optimal power consumption strategy of the current multi-core heterogeneous chip is determined, so that real-time dynamic power consumption management is realized.
In a preferred embodiment, further comprising: and acquiring the current state of the multi-core processor chip in real time, and periodically training and updating the training model to obtain an updated training model.
Since chip performance generally decays with time of use, in the present invention, it further includes: and acquiring the current state of the multi-core processor chip in real time, and periodically updating and training the training model by utilizing the acquired current state. More specifically, the invention further comprises a storage library of sample data, the off-line training of the model is facilitated through an experience playback mechanism, an updated training model is obtained, and since the storage library has a fixed capacity, when new data is stored after the storage library is full, the data stored in the storage library at first can be discarded, thereby ensuring the timeliness of the training sample and ensuring that the training model can adapt to the change of the multi-core processor chip.
In a preferred embodiment, obtaining the bonus factor according to said first state in step S4 comprises:
comparing the power consumption of the first state with the power consumption of the current state;
if the power consumption of the first state is smaller than that of the current state, a positive rewarding factor is given;
and if the power consumption of the first state is not smaller than that of the current state, giving a negative rewarding factor.
In the invention, the Q value neural network is continuously optimized through setting the reward factor, so that the algorithm decision evolves towards the direction of reducing the energy consumption.
In a preferred embodiment, for the bonus factor in S4, further comprising:
constructing a gradient rewarding mapping relation; wherein, the rewarding factors corresponding to different states of the multi-core processor chip are different;
acquiring theoretical accumulated instruction execution number of the multi-core heterogeneous chip running for a specified duration at the safe temperature;
each interval the specified duration is executed: calculating the actual accumulated instruction number executed by the multi-core heterogeneous chip within the appointed time length; performing difference operation on the actual accumulated instruction number and the theoretical accumulated instruction execution number to obtain an instruction difference; giving a reward factor to the multi-core heterogeneous chip according to the instruction difference value; wherein the bonus factor is positively correlated with the instruction difference.
It should be noted that the reward factor is an optimal parameter obtained through multiple training. The theoretical accumulated instruction execution number is obtained by running the multi-core heterogeneous chip at the safe temperature for a specified duration with medium performance. The invention aims at maximizing the total instruction number executed by the chip in the appointed time length, and realizes the performance optimization of the multi-core heterogeneous chip.
In the invention, when the number of accumulated instruction execution reaches a certain number, the multi-core processor chip obtains corresponding rewards and obtains higher rewards after further updating the strategy, so that more rewards are given to the low-power-consumption strategy by setting the gradient rewarding factor, the training model can be guided to gradually improve the power-consumption strategy, and the aim of optimizing the chip performance is achieved.
In a preferred embodiment, determining an optimal power consumption strategy comprises:
s71: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and the training model, and determining a second power consumption strategy so that the multi-core heterogeneous chip runs the second power consumption strategy;
s72: determining a second state in which the multi-core heterogeneous chip runs the second power consumption strategy, and judging whether the chip temperature in the second state is greater than a preset temperature threshold;
if yes, adding one to the last counted number of curtains to obtain the counted number of curtains, judging whether the counted number of curtains is equal to a preset training curtain number threshold value, and if yes, obtaining an optimal power consumption strategy; if not, returning to S71;
if not, returning to S71;
wherein, the preset temperature threshold is lower than the safe temperature, and the preset temperature threshold is determined by the following formula:
wherein,,T y for characterizing the preset temperature threshold value,T a for the characterization of the safe temperature,εfor characterizing the heating coefficient of a multi-core processor chip,Pfor characterizing the power consumption in the second state,P s for characterizing the heat dissipation power consumption of a multi-core processor chip,tfor characterizing the time interval for dynamic power consumption management,cfor characterizing the heat capacity of a multi-core processor chip,mfor characterizing the quality of the multicore processor chip.
It should be noted that, when the temperature of the chip reaches the second temperature threshold, the heat dissipation of the multi-core processor chip is less than the heat dissipation of the chip, and at this time, along with the continuous operation of the multi-core processor chip, the temperature of the multi-core processor chip gradually increases until reaching the safe temperature and even exceeding the safe temperature, which has a certain influence on the performance of the multi-core processor chip. Therefore, in the present invention, when periodic dynamic power consumption management is performed, for each time interval, the temperature rise condition of the multicore processor chip after t is operated in the second state, that is, the temperature rise temperature of the multicore processor chip in t, which is spaced by the next time of dynamic power consumption management, needs to be considered, and the temperature rise temperature is recorded as
Ensuring that the chip temperature of the multicore processor chip after running t is +.>
So that->
，T 1 The chip temperature in the second state is the preset temperature threshold value determined by the method, so that the multi-core processor chip can be further delayed from reaching the safe temperature, and the high-efficiency operation of the multi-core processor chip is ensured.
In the invention, the greedy factor can be attenuated along with the increase of the training curtain number, so that the greedy factor can fully explore the environment in the early training stage, and is favorable for searching the globally optimal power consumption strategy in the later training stage, so that the frequency and/or voltage of a single core in the multi-core heterogeneous chip can be regulated by utilizing the optimal power consumption strategy.
In a preferred embodiment, further comprising: clock synchronization among single cores in the multi-core processor chip is achieved by adopting a de-skew phase-locked loop.
In the invention, the real-time phase alignment between different clock domains is realized by using the remote clock feedback technology of the de-skew phase-locked loop, and the change of the clock distribution along with the process voltage temperature in the feedback loop is resisted, so that the performance of the multi-core processor is further optimized.
As shown in fig. 2 and 3, the embodiment of the invention provides a low-power consumption control device of a multi-core processor chip. The apparatus embodiments may be implemented by software, or may be implemented by hardware or a combination of hardware and software. In terms of hardware, as shown in fig. 2, a hardware architecture diagram of a computing device where a low power consumption control device of a multi-core processor chip provided in an embodiment of the present invention is located, in addition to a processor, a memory, a network interface, and a nonvolatile memory shown in fig. 2, a computing device where the device is located in an embodiment may generally include other hardware, such as a forwarding chip responsible for processing a packet, and so on. Taking a software implementation as an example, as shown in fig. 3, as a device in a logic sense, the device is formed by reading a corresponding computer program in a nonvolatile memory into a memory by a CPU of a computing device where the device is located. The low power consumption control device of the multi-core processor chip provided in this embodiment includes: an acquisition module 300, a heat dissipation module 302, and a power consumption management module 304;
an obtaining module 300, configured to obtain a chip temperature of a multicore processor chip;
the heat dissipation module 302 is configured to perform heat dissipation processing on the multicore processor chip when the chip temperature reaches a first temperature threshold and is less than a second temperature threshold;
the power consumption management module 304 is configured to obtain power consumption of the multi-core processor chip when the chip temperature reaches a second temperature threshold and is less than the safe temperature, and perform dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while performing heat dissipation processing, so as to obtain an optimal power consumption policy, so as to control each single core in the multi-core processor chip according to the optimal power consumption policy.
In some embodiments, the obtaining module 300 may be configured to perform the step 100, the heat dissipating module 302 may be configured to perform the step 102, and the power consumption management module 304 may be configured to perform the steps 104 and 106.
In some specific embodiments, the power consumption management module 304 is further configured to perform the following operations:
s1: acquiring an action space of a multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
In some specific embodiments, the power consumption management module 304 is further configured to perform the following operations:
comparing the power consumption of the first state with the power consumption of the current state;
if the power consumption of the first state is smaller than that of the current state, a positive rewarding factor is given;
and if the power consumption of the first state is not smaller than that of the current state, giving a negative rewarding factor.
In some specific embodiments, the power consumption management module 304 is further configured to perform the following operations:
constructing a gradient rewarding mapping relation; wherein, the rewarding factors corresponding to different states of the multi-core processor chip are different;
acquiring theoretical accumulated instruction execution number of the multi-core heterogeneous chip running for a specified duration at the safe temperature;
each interval the specified duration is executed: calculating the actual accumulated instruction number executed by the multi-core heterogeneous chip within the appointed time length; performing difference operation on the actual accumulated instruction number and the theoretical accumulated instruction execution number to obtain an instruction difference; giving a reward factor to the multi-core heterogeneous chip according to the instruction difference value; wherein the bonus factor is positively correlated with the instruction difference.
In some specific embodiments, the power consumption management module 304 is further configured to perform the following operations:
s71: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and the training model, and determining a second power consumption strategy so that the multi-core heterogeneous chip runs the second power consumption strategy;
s72: determining a second state in which the multi-core heterogeneous chip runs the second power consumption strategy, and judging whether the chip temperature in the second state is greater than a preset temperature threshold;
if yes, adding one to the last counted number of curtains to obtain the counted number of curtains, judging whether the counted number of curtains is equal to a preset training curtain number threshold value, and if yes, obtaining an optimal power consumption strategy; if not, returning to S71;
if not, returning to S71;
wherein, the preset temperature threshold is lower than the safe temperature, and the preset temperature threshold is determined by the following formula:
wherein,,T y for characterizing the preset temperature threshold value,T a for the characterization of the safe temperature,εfor characterizing the heating coefficient of a multi-core processor chip,Pfor characterizing the power consumption in the second state,P s for characterizing the heat dissipation power consumption of a multi-core processor chip,tfor characterizing the time interval for dynamic power consumption management,cfor characterizing the heat capacity of a multi-core processor chip,mfor characterizing the quality of the multicore processor chip.
In a specific embodiment, the apparatus further includes an update module, where the update module is configured to perform the following operations:
and acquiring the current state of the multi-core processor chip in real time, and periodically training and updating the training model to acquire an updated training model.
In some embodiments, the apparatus further comprises: clock synchronization among single cores in the multi-core processor chip is achieved by adopting a de-skew phase-locked loop.
It will be appreciated that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on a low power consumption control apparatus of a multi-core processor chip. In other embodiments of the invention, a low power control device of a multi-core processor chip may include more or fewer components than shown, or may combine certain components, or may split certain components, or may have a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
The content of information interaction and execution process between the modules in the device is based on the same conception as the embodiment of the method of the present invention, and specific content can be referred to the description in the embodiment of the method of the present invention, which is not repeated here.
The embodiment of the invention also provides a computing device, which comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the low-power consumption control method of the multi-core processor chip in any embodiment of the invention is realized.
The embodiment of the invention also provides a computer readable storage medium, and the computer readable storage medium stores a computer program, when the computer program is executed by a processor, the processor is caused to execute the low power consumption control method of the multi-core processor chip in any embodiment of the invention.
Specifically, a system or apparatus provided with a storage medium on which a software program code realizing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be caused to read out and execute the program code stored in the storage medium.
In this case, the program code itself read from the storage medium may realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code form part of the present invention.
Examples of the storage medium for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer by a communication network.
Further, it should be apparent that the functions of any of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform part or all of the actual operations based on the instructions of the program code.
Further, it is understood that the program code read out by the storage medium is written into a memory provided in an expansion board inserted into a computer or into a memory provided in an expansion module connected to the computer, and then a CPU or the like mounted on the expansion board or the expansion module is caused to perform part and all of actual operations based on instructions of the program code, thereby realizing the functions of any of the above embodiments.
It is noted that relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of additional identical elements in a process, method, article or apparatus that comprises the element.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: various media in which program code may be stored, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A low power consumption control method of a multi-core processor chip, comprising:
acquiring the chip temperature of a multi-core processor chip;
when the temperature of the chip reaches a first temperature threshold value and is smaller than a second temperature threshold value, radiating the multi-core processor chip;
when the chip temperature reaches the second temperature threshold and is smaller than the safety temperature, acquiring the power consumption of the multi-core processor chip, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while carrying out heat dissipation processing to obtain an optimal power consumption strategy;
and controlling each single core in the multi-core processor chip according to the optimal power consumption strategy.
2. The method of claim 1, wherein the dynamically managing power consumption of the multi-core processor chip according to the power consumption and the chip temperature to obtain an optimal power consumption policy comprises:
s1: acquiring an action space of the multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
3. The method of claim 2, wherein the obtaining a bonus factor based on the first status comprises:
comparing the power consumption of the first state with the power consumption of the current state;
if the power consumption of the first state is smaller than that of the current state, a positive rewarding factor is given;
and if the power consumption of the first state is not smaller than that of the current state, giving a negative rewarding factor.
4. A method according to claim 2 or 3, further comprising:
constructing a gradient rewarding mapping relation; wherein, the rewarding factors corresponding to different states of the multi-core processor chip are different;
acquiring theoretical accumulated instruction execution number of the multi-core heterogeneous chip running for a specified duration at the safe temperature;
each interval the specified duration is executed: calculating the actual accumulated instruction number executed by the multi-core heterogeneous chip within the appointed time length; performing difference operation on the actual accumulated instruction number and the theoretical accumulated instruction execution number to obtain an instruction difference; giving a reward factor to the multi-core heterogeneous chip according to the instruction difference value; wherein the bonus factor is positively correlated with the instruction difference.
5. A method according to claim 2 or 3, wherein said determining an optimal power consumption strategy comprises:
s71: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and the training model, and determining a second power consumption strategy so that the multi-core heterogeneous chip runs the second power consumption strategy;
s72: determining a second state in which the multi-core heterogeneous chip runs the second power consumption strategy, and judging whether the chip temperature in the second state is greater than a preset temperature threshold;
if yes, adding one to the last counted number of curtains to obtain the counted number of curtains, judging whether the counted number of curtains is equal to a preset training curtain number threshold value, and if yes, obtaining an optimal power consumption strategy; if not, returning to S71;
if not, returning to S71;
wherein the preset temperature threshold is lower than the safety temperature, and the preset temperature threshold is determined by the following formula:
wherein,,T y for characterizing the preset temperature threshold value,T a for the characterization of the safety temperature in question,εfor characterizing the heating coefficient of the multi-core processor chip,Pfor characterizing the power consumption in said second state,P s for characterizing the heat dissipation power consumption of the multi-core processor chip,tfor characterizing the time interval during which said dynamic power consumption management is performed,cfor characterizing the heat capacity of the multi-core processor chip,mfor characterizing the quality of the multicore processor chip.
6. The method as recited in claim 1, further comprising:
and clock synchronization among single cores in the multi-core processor chip is realized by adopting a de-skew phase-locked loop.
7. A low power consumption control apparatus of a multi-core processor chip, comprising:
the acquisition module is used for acquiring the chip temperature of the multi-core processor chip;
the heat dissipation module is used for conducting heat dissipation treatment on the multi-core processor chip when the temperature of the chip reaches a first temperature threshold value and is smaller than a second temperature threshold value;
the power consumption management module is used for acquiring the power consumption of the multi-core processor chip when the chip temperature reaches the second temperature threshold and is smaller than the safety temperature, and carrying out dynamic power consumption management on the multi-core processor chip according to the power consumption and the chip temperature while carrying out heat dissipation processing to obtain an optimal power consumption strategy so as to control each single core in the multi-core processor chip according to the optimal power consumption strategy.
8. The apparatus of claim 7, wherein the power consumption management module is to:
s1: acquiring an action space of the multi-core processor chip; the action space comprises all power consumption strategies, and frequencies and/or voltage levels corresponding to different power consumption strategies of the same single core are different;
s2: initializing greedy factors and discount rates, and initializing a behavior Q value neural network to be the same as a target Q value neural network;
s3: acquiring the current state of the multi-core heterogeneous chip, performing action selection according to an epsilon-greedy strategy and a behavior Q value neural network, and determining a first power consumption strategy so that the multi-core heterogeneous chip runs the first power consumption strategy; wherein the current state includes power consumption and chip temperature;
s4: determining a first state in which the multi-core heterogeneous chip runs the first power consumption strategy, and obtaining a reward factor according to the first state;
s5: taking the current state, the first power consumption strategy, the rewarding factor and the first state as sample data and adding the sample data into a sample set;
s6: when the number of sample data in the sample set reaches a training threshold, training the behavior Q value neural network by using the sample set, and when the training times reach a training times threshold, assigning a weight parameter of the behavior Q value neural network to a target Q value neural network to obtain a training model;
s7: and determining an optimal power consumption strategy by combining the training model with the epsilon-greedy strategy so as to utilize the optimal power consumption strategy to carry out dynamic power consumption management on the multi-core heterogeneous chip.
9. A computing device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the method of any of claims 1-6 when the computer program is executed.
10. A computer readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method of any of claims 1-6.
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