CN116269446A - Method, electronic equipment and medium for classifying format tower electroencephalogram signals based on algebraic topology - Google Patents
Method, electronic equipment and medium for classifying format tower electroencephalogram signals based on algebraic topology Download PDFInfo
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Abstract
The invention discloses a method, electronic equipment and medium for classifying format tower brain electrical signals based on algebraic topology, which comprises the steps of performing a visual stimulus experiment of contour recognition pictures on a subject to obtain original format tower brain electrical signal data; preprocessing original format tower electroencephalogram data; performing algebraic topology processing on the preprocessed formatted tower electroencephalogram data; and constructing a format tower electroencephalogram signal classification network, and classifying the format tower electroencephalogram signal data after algebraic topology processing. According to the invention, by introducing an algebraic topological tool, topological spatial features of the format tower electroencephalogram signals are extracted and digitized as classification objects, so that the data size is reduced by orders of magnitude, the calculation complexity is greatly reduced, the calculation resources are saved, and the classification accuracy can be effectively improved.
Description
Technical Field
The invention belongs to the field of electroencephalogram signal classification, and particularly relates to a format tower electroencephalogram signal classification method, electronic equipment and medium based on algebraic topology.
Background
The rapid development of deep learning in recent years has a certain promotion effect on various research fields, and particularly the fields of computer vision, pattern recognition, signal processing, detection and the like are obvious. With the continuous improvement and wide application of neural networks, deep learning is also introduced into the processing of brain wave signals (electroencephalograms). The existing deep neural network classification electroencephalogram signals can be mainly divided into emotion recognition, motor imagery, mental load test, epilepsy detection, sleep stage scoring and other large types, and belong to electroencephalogram signals generated by perceptual and visual stimulation. Traditional electroencephalogram signal classification generally comprises an important step of feature extraction, and the feature extraction is highly dependent on field knowledge and takes time and labor; the neural network can automatically extract distinguishable characteristics on the basis of a large amount of data training, and the characteristic greatly improves the classification accuracy of the electroencephalogram signals. However, classification accuracy is low when dealing with the brain electrical signals at the conscious level of LSTM and the current more powerful transducer network classification format towers and non-format towers of the timing signals.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a format tower electroencephalogram signal classification method, electronic equipment and medium based on algebraic topology.
According to a first aspect of an embodiment of the present application, there is provided a method for classifying a formatted tower electroencephalogram signal based on algebraic topology, specifically including the following steps:
step S1, performing a visual stimulus experiment of a contour recognition picture on a subject to obtain an original format tower brain electrical signal;
step S2, preprocessing the original format tower electroencephalogram signals;
s3, performing algebraic topology processing on the preprocessed formatted tower electroencephalogram signals;
and S4, constructing a format tower electroencephalogram signal classification network, and classifying the format tower electroencephalogram signals after algebraic topology processing.
According to a second aspect of embodiments of the present application, there is provided an electronic device comprising a memory and a processor, the memory being coupled to the processor; the memory is used for storing program data, and the processor is used for executing the program data to realize the algebraic topology-based format tower electroencephalogram signal classification method.
According to a third aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above-described algebraic topology-based format tower electroencephalogram classification method.
Unlike the prior art, the invention has the following beneficial effects: the invention provides a method for classifying format tower electroencephalograms based on algebraic topology, which extracts topological spatial features of the format tower electroencephalograms by introducing an algebraic topology tool and digitizes the topological spatial features as classification objects, so that the size of data is reduced by orders of magnitude, the calculation complexity is greatly reduced, the calculation resources are saved, and the classification accuracy can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a flow chart of a method for classifying format tower electroencephalograms based on algebraic topology provided by an embodiment of the invention;
FIG. 2 is a trellis column and chaotic diagram;
FIG. 3 is a schematic diagram of acquiring single-format tower brain electrical signals;
FIG. 4 is a schematic diagram of preprocessing an original EEG signal;
FIG. 5 is a schematic diagram of algebraic topology processing;
FIG. 6 is a schematic diagram of a lattice tower electroencephalogram classification network;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The features of the following examples and embodiments may be combined with each other without any conflict.
The invention provides a method for classifying format tower electroencephalogram signals based on algebraic topology, which is generated by a subject when the subject views images of a format tower and a non-format tower (chaotic graph), wherein the images are shown in a figure 2, and are characterized in that people can easily distinguish the images visually, three small circles with gaps form an obvious triangle outline, the small circles are slightly rotated on the basis of the former, and the small circles obviously do not form the triangle outline. People can easily distinguish the two pictures through naked eyes, but the neural network is not used, and the classification results of the two pictures such as classical CNN, LSTM, transformer and the like are only about 50% accurate. Experiments prove that the neural network has little effect on improving the classification effect of the electroencephalogram signals, therefore, an algebraic topological tool is introduced, the topology is based on the body quantity research of network shapes and structures, and the abstract high-dimensional spatial feature is mapped or reduced in dimension into the digital feature which is easy to understand by combining algebraic analysis, so that the digital quantity is analyzed.
Fig. 1 shows a flowchart of a method for classifying a formatted tower electroencephalogram signal based on algebraic topology according to an embodiment of the present invention, where the method specifically includes the following sub-steps:
step S1, performing a visual stimulus experiment of a contour recognition picture on a subject to obtain original format tower brain electrical signal data.
Specifically, the procedure for obtaining the original format tower brain electrical signal data through the visual stimulus experiment in step S1 in this example is as follows:
step S101, collecting 20 volunteers with normal eyesight and mental state and healthy physical condition, and allowing the subjects to independently receive experimental stimulation and signal acquisition record in a shielding room without interference.
In step S102, each subject observes 10 times of tower pictures and 30 times of chaotic map pictures, each observation time is 10S, and the interval time between times is 1S, and the specific flow is shown in fig. 3.
Step S103, checking the validity of the acquired format tower brain electrical signal data.
And S2, preprocessing the tower electroencephalogram signal in the original format acquired in the step S1 to enable the tower electroencephalogram signal to be a data object suitable for being processed as an algebraic topological tool.
As shown in fig. 4, the specific process of processing the original format tower electroencephalogram signal in step S2 is as follows:
step S201, electrode selection; the acquired original format tower brain signals have 64 electrodes, 1-59 paths are selected as processing objects, and 60-64 paths are positioning electrodes to be deleted.
Step S202, filtering; the band-pass filtering is used for limiting the frequency of the brain electrical signal of the format tower within the range of 0.1-45hz, so that the interference signals of higher and lower wave bands are removed, and all effective brain electrical signals are basically reserved;
step S203, artifact removal; various other biological signals inevitably have artifact interference in the signal acquisition process, so that various artifact noises such as blinks, eye movements, electromechanics and the like need to be removed. Setting a noise amplitude threshold based on the standard of the normal signals of the human brain, and screening and discarding the test time when the amplitude peak exceeds the noise threshold;
step S204, baseline calibration; taking the average value of the brain electrical signals in the 1s state before the beginning of each experiment as a baseline of the spontaneous brain electrical signals, and subtracting the baseline from the brain electrical signals to obtain corresponding calibration signals.
And S3, performing algebraic topology processing on the preprocessed formatted tower electroencephalogram signals.
Specifically, after the processing of step S2, the signal of each test time period is:
step S301, for the signal F of each trial period EEG Each path of signals in the array is subjected to Hilbert transform and integrated;
wherein N is the data length, M is the electrode number for electroencephalogram signal acquisition.
Wherein t represents a time variable and τ is a dummy variable in convolution integral;
step S302, calculating the instantaneous phase of each electrode:
wherein f i Is F EEG Row i of (a);
step S303, calculating the values of the corresponding elements of the correlation matrix by adopting a phase-locked value (Phase Locking Value, PLV) phase synchronization analysis method;
wherein j is an imaginary unit, phi P (n)、φ q (n) represents the instantaneous phase of the nth sampling instant in the electrodes p and q. Taking absolute value of the calculation result of the formula (5), and normalizing the whole matrix to obtain the final correlation matrix C M×M ：
Step S304, based on the incidence matrix C M×M VR replication was constructed.
Specifically, the correlation matrix C M×M The number of rows and columns in the middle represents the initial number of independent components, the value recorded in each row characterizes the "distance" between the other components, and it is conceivable that in a high-dimensional space, the series of MM independent components are fixedly arranged in space according to the respective positional distance relationship, so that a VR (virtis-Rips complex) complex can be constructed. The filtering process from zero connections to complex sets of connection points is shown in fig. 5, where the connection relationship changes as the filtering increases.
Step S305, calculating the algebraic object-Betty number of n-dimensional hole number in topological space based on VR complex, and sharing beta 0 ，β 1 ，β 2 Three-dimensional characteristics, beta 0 As input to a grid tower electroencephalogram classification network.
And S4, constructing a format tower electroencephalogram signal classification network, and classifying the format tower electroencephalogram signals after algebraic topology processing.
In this example, a Long Short-Term Memory network (LSTM) and a transducer encoder are used as base networks to construct a format tower electroencephalogram classification network, respectively.
Further, the step S4 further includes: training the grid tower electroencephalogram signal classification network.
Step S401, the tower electroencephalogram data to be classified are processed according to 8: the scale of 2 is divided into training and test sets.
Step S402, training the format tower electroencephalogram signal classification network by using a training set, and storing model parameters.
And S403, testing the accuracy of the format tower electroencephalogram signal classification network by using the test set until the accuracy threshold value of the self definition is reached.
As shown in fig. 7, an embodiment of the present application provides an electronic device, which includes a memory 101 for storing one or more programs; a processor 102. The method of any of the first aspects described above is implemented when one or more programs are executed by the processor 102.
And a communication interface 103, where the memory 101, the processor 102 and the communication interface 103 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The memory 101 may be used to store software programs and modules that are stored within the memory 101 for execution by the processor 102 to perform various functional applications and data processing. The communication interface 103 may be used for communication of signaling or data with other node devices.
The Memory 101 may be, but is not limited to, a random access Memory 101 (Random Access Memory, RAM), a Read Only Memory 101 (ROM), a programmable Read Only Memory 101 (Programmable Read-Only Memory, PROM), an erasable Read Only Memory 101 (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory 101 (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
The processor 102 may be an integrated circuit chip with signal processing capabilities. The processor 102 may be a general purpose processor 102, including a central processor 102 (Central Processing Unit, CPU), a network processor 102 (Network Processor, NP), etc.; but may also be a digital signal processor 102 (Digital Signal Processing, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a Field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In the embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other manners. The above-described method and system embodiments are merely illustrative, for example, flow charts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
In another aspect, embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by the processor 102, implements a method as in any of the first aspects described above. The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory 101 (ROM), a random access Memory 101 (RAM, random Access Memory), a magnetic disk or an optical disk, or other various media capable of storing program codes.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. The specification and examples are to be regarded in an illustrative manner only.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof.
Claims (8)
1. The method for classifying the format tower electroencephalogram signals based on algebraic topology is characterized by comprising the following steps of:
step S1, performing a visual stimulus experiment of a contour recognition picture on a subject to obtain an original format tower brain electrical signal;
step S2, preprocessing the original format tower electroencephalogram signals;
s3, performing algebraic topology processing on the preprocessed formatted tower electroencephalogram signals;
and S4, constructing a format tower electroencephalogram signal classification network, and classifying the format tower electroencephalogram signals after algebraic topology processing.
2. The algebraic topology-based formatted tower electroencephalogram classification method of claim 1, wherein preprocessing the raw formatted tower electroencephalogram data comprises:
deleting the format tower electroencephalogram signals acquired by the positioning electrodes;
band-pass filtering is carried out on the format tower electroencephalogram signal, so that the frequency of the format tower electroencephalogram signal is within the range of 0.1-45 hz;
removing noise in the brain electrical signal of the format tower;
and carrying out baseline calibration on the format tower electroencephalogram signals.
3. The algebraic topology-based classification method of the formatted tower electroencephalogram according to claim 2, wherein baseline calibration of the formatted tower electroencephalogram comprises:
taking the mean value of the format tower brain electrical signals in the 1s state before the start of each visual stimulation experiment as a signal base line, and subtracting the signal base line from the acquired format tower brain electrical signals to obtain corresponding calibration signals.
4. The algebraic topology-based format tower electroencephalogram classification method of claim 1, wherein algebraic topology processing of the preprocessed format tower electroencephalogram comprises:
step S301, pre-treating F for each visual stimulus experiment period EEG Each path of signal is subjected to Hilbert transformation and integrated, and the calculation formula is as follows:
wherein N is the data length, M is the electrode number for electroencephalogram signal acquisition;
wherein t represents a time variable and τ is a dummy variable in convolution integral;
step S302, calculating the instantaneous phase phi of each electrode:
wherein f i Is F EEG Row i of (a);
step S303, calculating the values of the corresponding elements of the correlation matrix by adopting a phase-locked value phase synchronization analysis method;
wherein j is an imaginary unit, phi P (n)、φ q (n) represents the instantaneous phase of the nth sampling instant in the electrodes p and q; taking absolute value of the calculation result of the formula (5), and normalizing the whole matrix to obtain the final correlation matrix C M×M ：
Step S304, based on the incidence matrix C M×M Constructing VR complex shape;
step S305, calculating the Betty number, which is an algebraic object of the n-dimensional hole number in the topological space, based on VR complex to obtain beta 0 ，β 1 ，β 2 Three-dimensional characteristics, beta 0 As input to a grid tower electroencephalogram classification network.
5. The algebraic topology-based format tower electroencephalogram classification method of claim 1, wherein the format tower electroencephalogram classification network is constructed based on a long-short-term memory network and a transducer encoder.
6. The algebraic topology-based formatted tower electroencephalogram classification method of claim 1 or 5, wherein step S4 further comprises: training the grid tower electroencephalogram signal classification network.
7. An electronic device comprising a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is configured to store program data, and the processor is configured to execute the program data to implement the algebraic topology-based format tower electroencephalogram classification method of any one of claims 1-6.
8. A computer readable storage medium having stored thereon a computer program, wherein the program when executed by a processor implements the algebraic topology based format tower electroencephalogram classification method according to any one of claims 1-6.
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