CN116266756A - Digital slope type analog-digital converter and signal conversion method - Google Patents

Abstract

The application relates to a digital slope analog-to-digital converter and a signal conversion method. The digital slope analog-to-digital converter includes a charge injection digital-to-analog converter circuit, a comparator circuit, a detection circuit, and control logic circuitry. The charge injection type digital-to-analog converter circuit comprises a plurality of capacitors, samples a plurality of input signals through the plurality of capacitors respectively, and generates a plurality of signals through the plurality of capacitors. The comparator circuit compares the plurality of signals to generate a plurality of decision signals. The detection circuit generates an index signal according to the decision signals. The control logic circuitry generates an enable signal based on the index signal and generates a digital output when the comparator circuit detects a crossover point of the plurality of signals. The charge injection type digital-to-analog converter circuit gradually adjusts the charge stored in at least one of the plurality of capacitors according to the enable signal until the comparator circuit detects the crossover point.

Description

Digital slope type analog-digital converter and signal conversion method

Technical Field

The present invention relates to an analog-to-digital converter, and more particularly, to a digital slope analog-to-digital converter and a signal conversion method using a charge injection type digital-to-analog converter circuit.

Background

The digital slope analog-to-digital converter may utilize a ramp (or hierarchical) voltage change to generate a digital code. In the prior art digital slope analog-to-digital converter, a capacitor array circuit having a plurality of capacitors is used to gradually adjust the signal level to generate the ramp voltage change. However, the linearity of the analog-to-digital converter is poor due to the possible mismatch between the capacitors. In addition, to produce such a ramped voltage change, a sufficient number of capacitors are required. In this way, the circuit area and the device cost are significantly increased.

Disclosure of Invention

In some embodiments, the digital slope analog-to-digital converter includes a charge injection digital-to-analog converter circuit, a comparator circuit, a detection circuit, and control logic circuitry. The charge injection type digital-to-analog converter circuit comprises a first capacitor and a second capacitor, and is used for sampling a first input signal and a second input signal respectively through the first capacitor and the second capacitor, and generating a first signal through the first capacitor and a second signal through the second capacitor. The comparator circuit is used for comparing the first signal with the second signal to generate a plurality of decision signals. The detection circuit is used for generating an index signal according to a plurality of decision signals. The control logic circuitry is configured to generate an enable signal based on the indicator signal and to generate a digital output when the comparator circuit detects a crossing point of the first signal and the second signal. The charge injection type digital-to-analog converter circuit is further configured to gradually adjust the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal until the comparator circuit detects the crossover point.

In some embodiments, the signal conversion method includes the following operations: sampling a first input signal and a second input signal respectively through a first capacitor and a second capacitor, and generating a first signal through the first capacitor and a second signal through the second capacitor; comparing the first signal with the second signal to generate a plurality of decision signals; generating an enabling signal according to a plurality of decision signals, and gradually adjusting the charge stored in at least one of the first capacitor and the second capacitor by a charge injection type digital-to-analog converter circuit according to the enabling signal until a crossing point of the first signal and the second signal is detected; and generating a digital output upon detection of the crossover point.

The features, acts and effects of the present application are described in detail below with respect to preferred embodiments with reference to the drawings.

Drawings

FIG. 1 is a schematic diagram of a digital slope analog-to-digital converter according to some embodiments of the present application;

FIG. 2A is a schematic diagram of the charge injection circuit of FIG. 1 according to some embodiments of the present application;

FIG. 2B is a waveform diagram depicting the plurality of signals of FIG. 1 according to some embodiments of the present application;

FIG. 3A is a flow chart depicting the control logic circuitry of FIG. 1 producing a digital output in accordance with some embodiments of the present application;

FIG. 3B is a circuit diagram depicting a portion of the control logic circuitry of FIG. 1 according to some embodiments of the present application; and

fig. 4 is a flow chart of a signal conversion method according to some embodiments of the present application.

Detailed Description

All terms used herein have their ordinary meaning. The foregoing words are defined in commonly used dictionaries, and any examples of use of the words discussed herein are given by way of example only and should not be interpreted as limiting the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in this specification.

As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other. As used herein, the term "circuitry" may be a single system formed of at least one circuit, and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive element to process signals.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. The terms first, second, third, etc. are used herein to describe and identify various elements. Thus, a first element could also be termed a second element herein without departing from the spirit of the present application. For ease of understanding, like elements in the various figures will be designated with like reference numerals.

Fig. 1 is a schematic diagram illustrating a digital slope analog-to-digital converter 100 according to some embodiments of the present application. The digital slope analog-to-digital converter 100 includes a switch SW1, a switch SW2, a comparator circuit 120, a charge injection digital-to-analog converter circuit 140, a detection circuit 160, and control logic circuitry 180.

Based on the control of the control logic 180, the switches SW1 and SW2 are turned on during sampling to transmit the input signal VIP and the input signal VIN to the charge injection dac 140 based on the control of the control logic 180. Based on the control of the control logic circuitry 180, the switches SW1 and SW2 are not turned on during the analog-to-digital conversion.

The charge injection type digital-to-analog converter circuit 140 includes a capacitor C1, a capacitor C2, and a charge injection circuit 141. The charge injection type DAC circuit 140 samples the input signal VIP via the capacitor C1 and generates the signal VP via the capacitor C1. Similarly, the charge injection digital-to-analog converter circuit 140 may sample the input signal VIN via the capacitor C2 and generate the signal VN via the capacitor C2. During the analog-to-digital conversion, the comparator circuit 120 may compare the signal VP and the signal VN to generate the decision signal VON and the decision signal VOP. In response to the decision signal VON and the decision signal VOP, the detection circuit 160 may generate an indicator signal VF, which may be used to indicate whether the decision signal VON and the decision signal VOP are in transition. For example, the detection circuit 160 may be, but is not limited to, a AND gate circuit having an inverting input. The inverting input receives the decision signal VOP, and the other input receives the decision signal VON. When the decision signal VON is a logic value 1 and the decision signal VOP is a logic value 0, the detection circuit 160 may generate the indicator signal VF having a logic value 1. When the decision signal VON is logic 0 and the decision signal VOP is logic 1, the detection circuit 160 may generate the indicator signal VF with logic 0.

The control logic 180 may generate the enable signal EN according to the index signal VF and generate the digital output DOUT when the comparator circuit 120 detects a crossing point (crossing point) of the signal VP and the signal VN. In the process of the analog-to-digital conversion, the charge injection type digital-to-analog converter circuit 140 can gradually adjust the charge stored in at least one of the capacitor C1 and the capacitor C2 according to the enable signal EN to adjust at least one corresponding one of the signal VP and the signal VN until the comparator circuit 120 detects the crossing point of the signal VP and the signal VN. For example, the charge injection circuit 141 can gradually adjust at least one of the capacitor C1 and the capacitor C2 according to the enable signal EN until the decision signal VON and the decision signal VOP generated by the comparator circuit 120 transition (i.e. the index signal VF transitions). The operation of the comparator circuit 120 and the charge injection digital-to-analog converter circuit 140 will be described later with reference to fig. 2A and 2B.

In some embodiments, the control logic 180 may also control the timing of the switch SW1, the switch SW2, the comparator circuit 120 and the charge injection type digital-to-analog converter circuit 140. In some embodiments, the control logic 180 may include a clock generator circuit (not shown), a counter circuit (not shown), and an encoder circuit (not shown) to perform the operations described above. The operation of the control logic 180 will be described later with reference to fig. 3A.

Fig. 2A is a schematic diagram illustrating the charge injection circuit 141 of fig. 1 according to some embodiments of the present application. The charge injection circuit 141 is configured to gradually adjust the charge stored in at least one of the capacitors C1 and C2 in fig. 1 according to the enable signal EN, the decision signal VOP and the decision signal VON. In this example, the charge injection circuit 141 includes a control circuit 220, a switching circuit 240, and a current source circuit 260.

The control circuit 220 is configured to generate the switching signal E1 according to the decision signal VON, the decision signal VOP and the enable signal EN. The switching circuit 240 is selectively connected to the capacitor C1 or the capacitor C2 according to the switching signal E1. In some embodiments, the switching circuit 240 may include a plurality of switches that are turned on according to a plurality of control bits (not shown) of the switching signal E1, respectively, to connect the current source circuit 260 to the capacitor C1 or the capacitor C2. In this way, the current source circuit 260 can discharge the capacitor C1 or the capacitor C2 through the switching circuit 240. Equivalently, during the on period (e.g., the time t in fig. 2B) of the switching circuit 240, the capacitor C1 (or the capacitor C2) injects charges into the current source circuit 260 to gradually adjust (e.g., decrease) the level of the signal VP (or the signal VN).

In some embodiments, the control circuit 220 may be implemented by a plurality of logic gate circuits and register circuits to generate a plurality of control bits in the switching signal E1. The register circuit may be used to store the decision signal VON and the decision signal VOP corresponding to the first comparison result generated by the comparator circuit 120 during the analog-to-digital conversion period. Based on the decision signal VON and the decision signal VOP corresponding to the first comparison result, the switching circuit 240 can determine to connect the current source circuit 260 to the capacitor C1 or the capacitor C2. For example, the comparator circuit 120 resets before starting the comparison so that the decision signal VOP and the decision signal VON both have the same reset level (e.g., low level corresponding to logic value 0 or high level corresponding to logic value 1). If the comparator circuit 120 confirms that the level of the signal VP is higher than the level of the signal VN in the first comparison after the sampling period, the comparator circuit 120 outputs the decision signal VON with a first logic value (e.g. logic value 1) and the decision signal VOP with a second logic value (e.g. logic value 0) (corresponding to the first comparison result). In response to the decision signal VON and the decision signal VOP, the switching circuit 240 may connect the current source circuit 240 to the capacitor C1 according to the switching signal E1 to gradually discharge the capacitor C1. In other words, the charge injection circuit 141 discharges one of the capacitor C1 and the capacitor C2 with a higher level according to the decision signal VON and the decision signal VOP corresponding to the first comparison result to detect the crossover point of the signal VP and the signal VN. Furthermore, the charge injection circuit 141 can determine the on period of the switching circuit 240 (i.e. the time for the current source circuit 260 to discharge the capacitor C1 or the capacitor C2; e.g. the time t of fig. 2B) according to the enable signal EN.

FIG. 2B is a waveform diagram depicting the signals VP and VN of FIG. 1 according to some embodiments of the present application. During the period T1 (i.e., sampling period), the switch SW1 and the switch SW2 are turned on. Under this condition, the capacitor C1 may sample the input signal VIP such that the level of the signal VP (i.e., the level of the capacitor C1) becomes high, and the capacitor C2 may sample the input signal VIN such that the level of the signal VN (i.e., the level of the capacitor C2) becomes low.

In the period T2, the analog-to-digital conversion is started, so that the switch SW1 and the switch SW2 are not turned on. The comparator circuit 120 compares the signal VP with the signal VN, and confirms that the signal VP is higher than the signal VN to output the decision signal VON with a logic value 1 and the decision signal VOP with a logic value 0. In other words, in this example, the first comparison result after sampling the input signal VIP and the input signal VIN indicates that the level of the signal VP is higher than the level of the signal VN. Under this condition, the detection circuit 120 outputs the index signal VF having a logic value of 1, and the charge injection dac 140 can gradually discharge the capacitor C1 according to the decision signal VOP and the decision signal VON.

In the period T3, the charge injection DAC 140 discharges the capacitor C1 to decrease the level of the signal VP. The comparator circuit 120 again compares the signal VP with the signal VN and confirms that the signal VP is still higher than the signal VN and outputs the decision signal VON with logic value 1 and the decision signal VOP with logic value 0 again. In this way, the detection circuit 160 outputs the index signal VF having the logic value 1 again. By analogy, the charge injection dac circuit 140 may gradually decrease the level of the signal VP during a plurality of subsequent periods (each period corresponds to the time period t) until the level of the signal VP is lower than the level of the signal VN. For example, during the last period T4, the charge injection digital-to-analog converter circuit 140 discharges the capacitor C1 to decrease the level of the signal VP. The comparator circuit 120 again compares the signal VP with the signal VN and confirms that the signal VP is lower than the signal VN and outputs the decision signal VON with logic value 0 and the decision signal VOP with logic value 1 instead. Under this condition, the detection circuit 160 generates an indicator signal VF having a logic value of 0 to indicate that the comparator circuit 120 detects the crossing point of the signal VP and the signal VN. The control logic 180 may generate the corresponding digital output DOUT according to the plurality of index signals VF generated in the above process, and end the analog-to-digital conversion.

Fig. 3A is a flow chart depicting control logic circuitry 180 of fig. 1 generating digital output DOUT according to some embodiments of the present application. Fig. 3B is a partial circuit diagram depicting the control logic circuitry 180 of fig. 1 according to some embodiments of the present application. To illustrate the operation of the control logic 180 to generate the digital output DOUT, please refer to FIGS. 3A and 3B together. For simplicity of illustration, only the portion of the control logic circuitry 180 that is primarily concerned with generating the digital output DOUT is shown in fig. 3B. In some embodiments, control logic 180 includes counter circuit 305 and encoder circuit 315, which may be used to perform the operations of FIG. 3A to generate digital output DOUT.

In operation S310, counting is performed according to the index signal to generate a count value. In operation S320, it is confirmed whether the comparator circuit detects a crossover point. If a crossover point is detected, operation S330 is performed. If no crossover point is detected, execution returns to operation S310. In operation S330, the count value is encoded to generate a digital output.

For example, the counter circuit 305 may be configured to be reset during a sampling period (e.g., period T1 of fig. 2B) and to count according to the trigger of the indicator signal VF after the sampling period to generate the count value CT. In the example of fig. 2B, the indicator signal VF has a logic value of 1 during the period T2. In response to the indicator signal VF, the counter circuit 305 may increment the count value CT by one unit (e.g., the count value CT is incremented from 0 to +1). During the period T3, the indicator signal VF still has a logic value of 1. In response to the indicator signal VF, the counter circuit 305 may increment the count value CT by one more unit (e.g., the count value CT is incremented from +1 to +2). And so on, in the last period T4, the indicator signal VF transitions to have a logic value of 0. In response to the index signal VF, the counter circuit 305 stops increasing the count value CT and outputs the current count value to the encoder circuit 315. Encoder circuit 315 may encode count value CT to produce digital output DOUT. In other words, through operations S310 to S330, the control logic 180 may count according to the indicator signal VF until the comparator circuit 120 detects the crossover point to generate the count value CT, and encode the count value CT to generate the digital output DOUT.

The above described arrangements of the operations for generating the digital output DOUT and the control logic circuitry 180 are for illustration, and the present application is not limited thereto. Various operations for generating the digital output DOUT and their corresponding circuit arrangements are within the scope of the present application.

In some related art, a digital slope analog-to-digital converter uses a capacitor array having a plurality of capacitors to generate a ramp-type voltage change. In these techniques, there may be mismatch between the capacitors, which may result in reduced linearity of the analog-to-digital converter using the capacitor array. In addition, the capacitor array needs to use a plurality of capacitors to gradually adjust the level, which leads to a significant increase in circuit area. In the foregoing embodiments, the number of current source circuits (e.g., the current source circuit 260) in the charge injection digital-to-analog converter circuit 140 for adjusting the capacitor C1 and the capacitor C2 is 1. In this way, the mismatch of the charge injection type digital-to-analog conversion circuit 140 can be avoided, and the circuit area can be effectively reduced. In addition, since the charge injection type digital-to-analog conversion circuit 140 is sequentially injected with charges in different periods for operation, the operation characteristic can meet the operation requirement of the digital slope type analog-to-digital converter 100 to gradually adjust the signal level to detect the crossover point.

In the above embodiments, one of the capacitors C1 and C2 is adjusted to detect the crossover point, but the present application is not limited thereto. In other embodiments, both the capacitor C1 and the capacitor C2 can be adjusted to detect the crossover point. For example, the charge injection digital-to-analog converter circuit 140 may further include an additional charge injection circuit for charging the other of the capacitor C1 and the capacitor C2 (i.e., injecting charge into the other of the capacitor C1 and the capacitor C2). For the example of fig. 2B, since the first comparison result indicates that the level of the signal VN is low, the additional charge injection circuit can gradually charge the capacitor C2 to gradually increase the level of the signal VN. In this way, the crossover point between the signals VP and VN can be detected more quickly. In other words, in some embodiments, the charge injection digital-to-analog converter circuit 140 may include a plurality of charge injection circuits 141, wherein one charge injection circuit 141 may be used to discharge one of the capacitors C1 and C2 (e.g., a capacitor having a higher potential), and one charge injection circuit 141 may be used to charge one of the capacitors C1 and C2 (e.g., a capacitor having a lower potential).

Alternatively, in other embodiments, the charge injection digital-to-analog converter circuit 140 may alternately discharge one of the capacitors C1 and C2 and charge the other of the capacitors C1 and C2 using the same charge injection circuit (e.g., the charge injection circuit 141). For example in fig. 2B, during the period T2, the current source circuit 260 can discharge the capacitor C1 through the switching circuit 240. During period T3, current source circuit 260 may charge capacitor C2 via an additional switch (not shown in fig. 2A) in switching circuit 240. By so doing, the crossover point between the signals VP and VN can be detected. Thus, in various embodiments, the charge injection dac circuit 140 can gradually adjust the charge stored in at least one of the capacitors C1 and C2 to adjust at least one of the signals VN and VP until the comparator circuit 120 detects the crossover point.

The above arrangement of the charge injection type digital-to-analog converter circuit 140 is used for example, and the present application is not limited thereto. Various circuit arrangements for gradually adjusting the level of at least one of the capacitor C1 and the capacitor C2 are within the scope of the present application.

Fig. 4 is a flow chart of a signal conversion method 400 according to some embodiments of the present application. In operation S410, the first input signal (e.g., the input signal VIP) and the second input signal (e.g., the input signal VIN) are sampled respectively via the first capacitor (e.g., the capacitor C1) and the second capacitor (e.g., the capacitor C2), and the first signal (e.g., the signal VP) is generated via the first capacitor and the second signal (e.g., the signal VN) is generated via the second capacitor. In operation S420, the first signal and the second signal are compared to generate a plurality of decision signals (e.g., decision signal VON and decision signal VOP). In operation S430, an enable signal (e.g., enable signal EN) is generated according to the plurality of decision signals, and the charge stored in at least one of the first capacitor and the second capacitor is gradually adjusted by the charge injection type digital-to-analog converter circuit (e.g., charge injection type digital-to-analog converter circuit 140) according to the enable signal until a crossover point of the first signal and the second signal is detected. In operation S440, a digital output is generated when the crossover point is detected.

The above operations may be understood by referring to the above embodiments, and thus the description thereof will not be repeated here. The various operations of the signal conversion method 400 described above are merely examples and are not limited to being performed in the order illustrated in this example. The various operations under the signal conversion method 400 may be added, substituted, omitted, or performed in a different order (e.g., concurrently or with partial concurrence) as appropriate without departing from the manner and scope of operation of the various embodiments herein.

In summary, the digital slope analog-to-digital converter and the signal conversion method provided in some embodiments of the present application can gradually adjust the signal level by using the charge injection circuit to generate a slope voltage change. Thus, the influence of mismatch can be reduced, and the number of circuits used can be reduced to reduce the whole area of the circuit.

Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art may make various changes to the technical features of the present application according to the explicit or implicit disclosure of the present application, where the various changes may belong to the scope of patent protection sought herein, in other words, the scope of patent protection of the present application shall be defined by the claims of the present application.

[ symbolic description ]

100: digital slope type analog-digital converter

120: comparator circuit

140: charge injection type digital-to-analog converter circuit

141: charge injection circuit

160: detection circuit

180: control logic circuitry

220: control circuit

240: switching circuit

260: current source circuit

305: counter circuit

315: encoder circuit

400: signal conversion method

C1, C2: capacitance device

CT: count value

DOUT: digital output

E1: switching signals

EN: enable signal

S310, S320, S330, S410, S420, S430, S440: operation of

SW1, SW2: switch

T1 to T4: during the period of time

VF: index signal

VIN, VIP: input signal

VN, VP: signal signal

VON, VOP: decision signal

t: length of time.

Claims (10)

1. A digital slope analog to digital converter comprising:

the charge injection type digital-to-analog converter circuit comprises a first capacitor and a second capacitor, wherein the charge injection type digital-to-analog converter circuit is used for sampling a first input signal and a second input signal through the first capacitor and the second capacitor respectively, and generating a first signal through the first capacitor and a second signal through the second capacitor;

a comparator circuit for comparing the first signal and the second signal to generate a plurality of decision signals;

a detection circuit for generating an index signal according to the decision signals; and

a control logic circuit system for generating an enable signal according to the index signal and generating a digital output when the comparator circuit detects a crossing point of the first signal and the second signal,

the charge injection type digital-to-analog converter circuit is further configured to gradually adjust the charge stored in at least one of the first capacitor and the second capacitor according to the enable signal until the comparator circuit detects the crossover point.

2. The digital-to-analog converter of claim 1, wherein the charge injection digital-to-analog converter circuit is configured to adjust the charge stored in the first capacitor and the second capacitor according to the plurality of decision signals corresponding to a first comparison result of the first signal and the second signal.

3. The digital-to-analog converter of claim 1, wherein the charge injection digital-to-analog converter circuit gradually discharges the first capacitor according to the plurality of decision signals if a first comparison result after the first input signal and the second input signal are sampled indicates that a level of the first signal is higher than a level of the second signal.

4. The digital-to-analog-to-digital converter of claim 1, wherein the control logic is configured to count according to the indicator signal until the comparator circuit detects the crossover point to generate a count value and encode the count value to generate the digital output.

5. The digital-to-slope analog-to-digital converter of claim 1, wherein the charge injection digital-to-analog converter circuit further comprises:

a charge injection circuit for gradually adjusting the charge stored in the at least one of the first capacitor and the second capacitor according to the enable signal and the decision signals.

6. The digital-to-slope analog-to-digital converter of claim 5, wherein the charge injection circuit comprises:

a control circuit for generating a switching signal according to the enable signal and the decision signals;

a switching circuit selectively connected to the first capacitor or the second capacitor according to the switching signal; and

the current source circuit is used for discharging the first capacitor or the second capacitor through the switching circuit.

7. The digital-to-analog-to-digital converter of claim 1, wherein the number of current source circuits in the charge injection type digital-to-analog converter circuit for adjusting the first capacitor or the second capacitor is 1.

8. The digital-to-slope analog-to-digital converter of claim 1, wherein the charge injection digital-to-analog converter circuit further comprises:

and a plurality of charge injection circuits for discharging one of the first capacitor and the second capacitor and charging the other of the first capacitor and the second capacitor according to the enable signal and the plurality of decision signals.

9. A signal conversion method, comprising:

sampling a first input signal and a second input signal respectively through a first capacitor and a second capacitor, and generating a first signal through the first capacitor and a second signal through the second capacitor;

comparing the first signal with the second signal to generate a plurality of decision signals;

generating an enabling signal according to the decision signals, and gradually adjusting the charge stored in at least one of the first capacitor and the second capacitor by a charge injection type digital-to-analog converter circuit according to the enabling signal until a crossing point of the first signal and the second signal is detected; and

a digital output is generated upon detection of the crossover point.

10. The signal conversion method according to claim 9, wherein gradually adjusting the charge stored in at least one of the first capacitor and the second capacitor by the charge injection dac circuit according to the enable signal comprises:

determining to adjust the charge stored in the at least one of the first capacitor and the second capacitor according to the decision signals corresponding to a first comparison result of the first signal and the second signal.

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