CN116264490A

CN116264490A - Message processing method, related device and equipment

Info

Publication number: CN116264490A
Application number: CN202111519422.6A
Authority: CN
Inventors: 郑晓亮
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2023-06-16

Abstract

The embodiment of the application discloses a message processing method, a related device and equipment, which are used for improving forwarding bandwidth. The method comprises the following steps: and acquiring a learning message from upstream equipment, and determining the jitter position in the jitter range of the learning message according to a first periodic label, a sending time stamp and jitter information carried by the learning message. And determining the residual jitter time length of the learning message according to the jitter position. And determining a second moment corresponding to the learning message according to the residual jitter time length and the first moment of acquiring the learning message, and determining the sending period of the learning message according to the second moment.

Description

Message processing method, related device and equipment

Technical Field

Embodiments of the present application relate to the field of communications, and in particular, to a method, a related device, and an apparatus for processing a message.

Background

Deterministic internetworking protocol (internet protocol, IP) techniques, combined with explicit path, edge shaping, label mapping, etc. enable IP networks to have the capability of deterministic end-to-end jitter. The network can have relatively stable time delay through the learning of the label mapping technology.

In a message processing method, after a downstream device obtains a learning message for the first time, a time for calculating a sending period is determined according to a time when the message is received, a period time, a forwarding delay and a time corresponding to a jitter range, and a period mapping relation is determined according to the sending period and a period label carried by the learning message.

In the message processing method, each learning message is waited for a duration corresponding to a fixed jitter range to be sent. If the learning message is positioned at the tail of the jitter range, the waiting time is extra and increased, so that the message is forwarded for a longer time, more caches are consumed, and the total forwarding bandwidth of deterministic traffic is reduced.

Disclosure of Invention

The embodiment of the application provides a message processing method, a related device and equipment, wherein the residual jitter duration corresponding to a learning message is determined by determining the jitter position of the learning message in a jitter range, and the time for calculating a sending period is determined according to the residual jitter duration. The waiting time period will vary according to the jitter position and is more accurate. Therefore, under the condition that the learning message is positioned at the tail part of the jitter range, the waiting time is reduced, so that the consumption of the buffer memory is reduced, and the total forwarding bandwidth of deterministic traffic is improved.

An embodiment of the present application provides a method for processing a message, including:

the capability of end-to-end deterministic jitter of the IP network is provided by deterministic IP technology, so that the transmission of different messages through the whole network has relatively fixed time delay. The label mapping technology in the IP technology enables the transmission period of the upstream equipment and the transmission period of the downstream equipment to have a fixed offset relation by learning the label mapping relation. The message for learning the tag mapping relationship is called a learning message.

In the embodiment of the application, the upstream device sends a learning message to the downstream device, wherein the learning message carries a first periodic tag, a sending time stamp and jitter information, the first periodic tag indicates a period of the upstream device sending the learning message, and the sending time stamp indicates a moment of the upstream device sending the learning message. The jitter information can reflect jitter conditions of the message transmitted in the network. After receiving the learning message, the downstream device determines the jitter position of the learning message in the jitter range according to the first periodic label, the sending time stamp and the jitter information, and the jitter position provides a reference for the downstream device to determine the waiting time of the learning message. And the downstream equipment determines the residual jitter time length corresponding to the learning message according to the jitter positions, and different jitter positions correspond to different residual jitter time lengths. The downstream equipment also records a first moment for acquiring the learning message, and determines a second moment corresponding to the learning message according to the first moment and the residual jitter duration. And then determining the transmission period of the transmission learning message according to the second moment.

From the above technical solutions, the embodiments of the present application have the following advantages: the network equipment determines the residual jitter duration corresponding to the learning message by determining the jitter position of the learning message in the jitter range, and determines a second moment for calculating the sending period according to the residual jitter duration. The waiting time period will vary according to the jitter position and is more accurate. Therefore, under the condition that the learning message is positioned at the tail part of the jitter range, the waiting time is reduced, so that the consumption of the buffer memory is reduced, and the total forwarding bandwidth of deterministic traffic is improved.

In an alternative embodiment of the first aspect, the jitter information comprises at least two of a jitter range, a maximum value of the transmission delay, or a minimum value of the transmission delay. That is, the specific content included in the jitter information has various cases, and may include a jitter range and a maximum value of a transmission delay; or includes jitter information including a jitter range and a minimum value of a transmission delay; or includes jitter information including jitter range, maximum value of transmission delay, and minimum value of transmission delay, and is not limited herein. Where the transmission delay refers to the period of time from when the upstream device opens the gate to when the port is time stamped. The value of the jitter range is equal to the difference between the maximum value of the transmission delay and the minimum value of the transmission delay, so that any two values of the three values are known, and the other unknown value can be calculated.

In the embodiment of the application, the jitter information carried in the learning message is possible to be selected according to the actual application condition, so that the flexibility of the technical scheme of the application is improved. Meanwhile, only two items are carried, other values needed to be used can be calculated, more data can be carried in the message, and the utilization rate of the message is improved.

In an optional embodiment of the first aspect, the downstream device determines the second time corresponding to the learning message, specifically according to the remaining jitter duration, the period duration, the forwarding delay and the first time. The forwarding delay refers to a period of time before the downstream device receives a learning message, and after a series of processes (including identifying a message format, reading a message content, modifying a message, and/or encapsulating a message) are performed on the learning message, the downstream device reaches a gate of the downstream device. The period duration may be set according to actual needs, and is not limited herein.

In an optional embodiment of the first aspect, the downstream device determines a cycle mapping relationship of the learning packet according to a second cycle tag and a first cycle tag corresponding to the transmission cycle. The period mapping relation can be represented by a difference value of two period labels. It should be noted that, in practical application, since a plurality of periods form a cycle, the period labels formed by different physical moments may correspond to the same period label, or the value of the period label after the physical moment is smaller than that of the period label before the physical moment, the difference value of the two period labels is directly calculated, and a correct period mapping relationship cannot be obtained. Therefore, it is necessary to convert the two cycle labels into the same cycle through a certain conversion to obtain a correct cycle mapping relationship. This also requires that the number of cycles included in the cycle be at least one to satisfy jitter learning.

A second aspect of the embodiments of the present application provides a message processing apparatus, which includes an obtaining unit and a processing unit.

The acquisition unit is used for acquiring a learning message from the upstream equipment, wherein the learning message carries a first cycle label, a sending time stamp and jitter information, the first cycle label indicates the cycle of the upstream equipment for sending the learning message, and the sending time stamp is the moment of the upstream equipment for sending the learning message.

The processing unit is used for determining the jitter position of the learning message in the jitter range according to the sending time stamp and the first periodic label; determining the residual jitter time length of the learning message according to the jitter position; determining a second moment corresponding to the learning message according to the residual jitter time length and the first moment of acquiring the learning message; and determining the sending period of the learning message according to the second moment.

The message processing apparatus is configured to execute the method of the first aspect, and the beneficial effects shown in this aspect are similar to those of the first aspect, and are not described herein again.

A third aspect of the embodiments of the present application provides a network device, including a processor, a memory and a communication interface, where the processor is connected to the memory, and the processor is configured to perform the method of the first aspect.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium having a program stored therein, which when executed by a computer, performs the method of the first aspect.

A fifth aspect of the embodiments of the present application provides a computer program product, characterized in that the computer performs the method of the first aspect when the computer program product is executed on a computer.

Advantageous effects shown in the third to fifth aspects are similar to those of the first aspect, and are not described here again.

Drawings

FIG. 1 is a schematic diagram of a message processing system according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a principle of deterministic IP technology;

FIG. 3 is a schematic flow chart of a message processing method according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an upstream device according to an embodiment of the present application;

fig. 5 is a schematic view of an application scenario provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a network device according to an embodiment of the present application.

Detailed Description

First, terms that may be related will be described.

1. And (5) learning the message.

In deterministic IP technology, messages sent out by an upstream device in a certain period are all mapped to the same period sent out by a downstream device by a label mapping technology, so that a fixed offset relationship exists between the sending periods of the upstream device and the downstream device. As such, different messages are sent across the entire network with relatively fixed delays. The message for learning the periodic mapping relationship between the upstream and downstream devices is called a learning message. The periodic mapping relationship may also be referred to as a label mapping relationship.

2. Delay, jitter, and jitter suppression.

Delay is an important indicator in a network, affects the user experience, and may vary due to a number of factors, which may be used to measure the time required for a message to travel from an upstream device to a downstream device. The delay can be understood as a combination of the following four parts according to the processing flow of the data packet: processing delay, queuing delay, transmission delay, and propagation delay. Where the processing delay is the time at which the system analyzes the packet header and determines where the packet must be sent, and corresponds to the "forwarding delay" in the embodiments of the present application. The size of the processing delay is related to the entries in the routing table, the execution of the data structures in the system, and the hardware implementation. Queuing delay is the time between queuing and sending of a data packet, and depends on the size of the data traffic, the type of traffic, and which router queuing algorithms are implemented. The transmission delay is the time required to push the data of the data packet into the line, and varies according to the size of the data packet and/or the bandwidth. Propagation delay is the time associated with the first bit of a packet transmitted from a sender to a receiver, and is often referred to as "distance delay" and is affected by the propagation distance and speed.

Jitter is closely related to delay and can be understood as the difference between the delay values of two packets. The jitter can reflect the degree of stability of the network, with less network jitter being more stable. Jitter can have a number of adverse consequences including packet loss, network congestion, etc. Congestion occurs when a network device begins to drop packets and an endpoint does not receive a packet. The terminal may require retransmission of the lost data packet, which may easily lead to congestion collapse.

Jitter suppression refers to measures taken to reduce a series of adverse effects caused by network jitter. In the message processing method provided by the embodiment of the application, the message sent by the upstream device carries jitter information, and the downstream device uses the jitter information and the deterministic IP technology to keep relatively fixed time delay of the whole network and restrain the jitter in a reasonable range.

Embodiments of the present application are described below with reference to the accompanying drawings. As one of ordinary skill in the art can appreciate, with the development of technology and the appearance of new scenes, the technical solutions provided in the embodiments of the present application are applicable to similar technical problems.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which the embodiments of the application described herein have been described for objects of the same nature. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In addition, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Next, referring to fig. 1, fig. 1 is a schematic diagram of an architecture of a message processing system according to an embodiment of the present application.

As shown in fig. 1, a deterministic IP network includes a plurality of network devices, which can be divided into an ingress edge device (PE), an egress edge device, and a core device (P). In the embodiment shown in fig. 1, for a certain flow (flow), the devices that enter the network are called ingress PEs, the devices that exit the network are called egress PEs, and the middle will pass through two P devices.

In the embodiment shown in fig. 1, bidirectional label mapping relation learning is required between the ingress PE and the P1 device, between the P1 device and the P2 device, and between the P2 device and the egress PE, so as to achieve stable delay when the whole network processes the message.

It should be noted that fig. 1 is only an example of a deterministic IP network, and in practical applications, a greater or lesser number of P devices may be included in the deterministic IP network, and is not limited herein.

Alternatively, the types of the network devices in the deterministic IP network may be various, and may be routers, or other types of network devices, such as switches, which are not limited herein. The types of the respective network devices may be the same or different, and are not particularly limited herein.

Alternatively, the message processing system shown in fig. 1 is only an example, and the message processing method provided in the embodiment of the present application may also be applied to other types of communication systems. Other types of communication systems may be wireless communication systems such as fifth generation mobile communication technology (5th generation mobile communication technology,5G), satellite communication, and short range, and it should be noted that the wireless communication systems mentioned in the embodiments of the present application include, but are not limited to: three application scenarios of narrowband internet of things (NB-IoT), long term evolution (long term evolution, LTE) and 5G mobile communication systems enhance mobile broadband (enhanced mobile broadband, eMBB), low latency high reliability (ultra-low-latency communication, URLLC) and mass internet of things (massive machine type communications, mctc), as well as other mobile communication systems that may occur in the future, without limitation herein in particular.

In the following, referring to fig. 2, fig. 2 is a schematic diagram of deterministic IP technology for a simple explanation.

In the embodiment shown in fig. 2, the forwarding path of the message in the network is designated as outgoing from the network after passing through the ingress PE, the P device and the egress PE by an explicit path. As shown in fig. 2, in the message forwarding process, the upstream and downstream devices may set periods with the same duration, so that the same physical time corresponds to the same period label.

In practical applications, the time interval between different messages arriving at the ingress of the ingress PE is not always fixed, so that the messages received by the ingress PE within a period of time can be planned to be sent out in the same period divided by the egress interface by using an edge shaping technique. The technology has no strict limitation on the period requirement and has wider practical significance.

In the embodiment shown in fig. 2, through the label mapping technology, the messages sent by the ingress PE in the T1 period are all mapped to the T3 period sent by the P device; and mapping all messages sent out by the T3 period of the P equipment to the T5 period of the export PE. Thus, there is a fixed offset relationship between the transmission periods of the upstream and downstream devices, for example, T1- > T3, T3- > T5, which are different by two periods. It will be appreciated that in the embodiment shown in fig. 2, the ingress PE is an upstream device of the P device, which is an upstream device of the egress PE device; the P device is a downstream device of the ingress PR device and the egress PE is a downstream device of the P device.

As such, different messages are sent across the entire network with a relatively fixed delay and jitter ranges < 2T. Specifically, the maximum jitter range of 2T is because, when entering the network, the message enters the ingress PE at the head or tail of the T0 period, and a maximum jitter of 1T is generated; when exiting the network, the message leaves the egress PE at the head or tail of the T5 period, which also generates maximum 1T jitter, and in general, the message passes through the entire network, which generates maximum 2T jitter.

Next, a description is given of a message processing method provided in an embodiment of the present application, referring to fig. 3, fig. 3 is a schematic flow chart of the message processing method provided in the embodiment of the present application, including the following steps:

301. and acquiring a learning message from the upstream equipment.

The downstream device can acquire a learning message sent by the upstream device, wherein the learning message carries a first periodic tag (label), a sending time stamp (tup) and jitter information, the first periodic tag indicates the period of the upstream device sending the learning message, and the sending time stamp is the moment of the upstream device sending the learning message.

For clarity of explanation, referring to fig. 4 for explaining information carried by the learning message, referring to fig. 4, fig. 4 is a schematic structural diagram of an upstream device according to an embodiment of the present application. As shown in fig. 4, the upstream device includes a plurality of gates, a scheduling module, and an egress port.

After the upstream device receives the learning message, a series of processes may be performed on the learning message, including, but not limited to, identifying a format of the learning message, reading a content of the learning message, modifying a content of the learning message, and/or encapsulating the learning message. The scheduling module then controls the opening or closing of the different gates to determine which gate to send the learning message. The upstream device may send messages by scheduling module, opening different gates at regular time, and in the embodiment shown in fig. 4, the learning message is sent by gate 2. From the opening of the gate control, the learning message is sent out from the output port of the upstream equipment and is marked with a sending time stamp, and the upstream equipment is internally provided with a plurality of processing links, so jitter, max, min equivalence can appear.

In the embodiment shown in fig. 4, "O" indicates a gate open (open), and "C" indicates a gate close (close). the tlabel indicates that the first period tag corresponds to a physical time, and the transmission time stamp (tup) indicates a time when the upstream device transmits the learning message.

The jitter information carried by the learning message comprises at least two of a jitter range (jitter), a maximum value (max) of a transmission delay, or a minimum value (min) of the transmission delay. That is, the specific content included in the jitter information has various cases, and may include a jitter range and a maximum value of a transmission delay; or includes jitter information including a jitter range and a minimum value of a transmission delay; or includes jitter information including jitter range, maximum value of transmission delay, and minimum value of transmission delay, and is not limited herein.

The sending delay refers to the time from the opening of the gate of the upstream device to the time when the message is sent out from the output port of the upstream device and is time-stamped, that is, the time of tup-tlabel. Thus, min is the minimum value of tup-tlabel and max is the maximum value of tup-tlabel. In addition, jitter=max-min. Thus, based on any two known values in the jitter information, another unknown value can be obtained.

302. And determining the jitter position of the learning message in the jitter range according to the first periodic label, the sending time stamp and the jitter information.

After the downstream device acquires the learning message, the jitter position of the learning message in the jitter range can be determined according to the information carried by the learning message. For clarity of illustration, please refer to fig. 5, fig. 5 is a schematic view of an application scenario provided in an embodiment of the present application.

It is assumed that the upstream device transmits a learning message to the downstream device in the T1 period, and the learning message carries a first period tag (label), a transmission time stamp (tup), a jitter range (jitter), and a minimum value (min) of the forwarding delay. The downstream device may determine the jitter position P according to the following formula.

P= (tup-label×t-min)% cycle, where T represents the period length of the cycle, cycle represents the length of one cycle of multiple cycles, and% represents the remainder. Illustratively, in the embodiment shown in FIG. 5, the 6 periods T0-T5 are one cycle. In practical applications, a greater or lesser number of cycles may be included in a cycle, and the invention is not limited herein. It should be noted, however, that in order to ensure proper learning of the period mapping relationship, one cycle needs to cover at least one period number corresponding to the jitter learning.

303. And determining the residual jitter time length corresponding to the learning message according to the jitter position.

After the jitter position is obtained, the downstream device can determine the corresponding residual jitter duration according to the obtained jitter position. For example, assuming a jitter range of 20 microseconds, the calculated jitter position is at 5 microseconds, and then the remaining jitter duration is 20-5 = 15 microseconds. The method means that the time length of waiting 15 microseconds can be used for suppressing jitter, and compared with the prior art that the time length waiting for waiting is saved by waiting for a complete jitter range of 20 microseconds no matter the jitter position is, the method reduces the consumption of buffering and improves the total forwarding bandwidth of deterministic traffic.

304. And determining a second moment corresponding to the learning message according to the residual jitter time length and the first moment of acquiring the learning message.

After the remaining jitter duration is obtained, the downstream device determines a corresponding second time of the learning message. Specifically, the downstream device determines the second time according to the remaining jitter duration, the period duration, the forwarding delay and the first time. The second time t1 may be determined based on the following formula:

t1＝t0+(jitter－P)+T+Lmax。

as shown in fig. 5, T0 represents a first time when the downstream device acquires the learning message, jitter-P represents a remaining jitter duration, T represents a period duration, lmax represents a forwarding delay, and T1 represents a second time.

The forwarding delay refers to a maximum time period required for forwarding the learning message from an inlet of the downstream device to an outlet queue of the downstream device, that is, a maximum time period from receiving the learning message by the downstream device to entering a gate of the downstream device, where the downstream device performs a series of operations on the learning message, including identifying a format of the message, reading a content of the learning message, modifying the content of the learning message, and/or encapsulating the learning message, and is not limited herein. It will be appreciated that the upstream device may send multiple messages in one cycle, and the downstream device waits for one cycle, while the waiting time is not redundant, and also receives the message sent by the upstream device in one cycle as much as possible. The period duration T is the same as the duration of any one of the individual forwarding periods (T0 to T5) of the upstream device.

305. And determining the sending period of the learning message according to the second moment.

The downstream device takes the next complete cycle after the second moment as the transmission cycle of the learning message. In the embodiment shown in fig. 5, the second time T1 is located in the period T3, so the downstream device determines that the transmission period is the next period of T3, i.e., T4.

It should be noted that, in practical application, since a plurality of periods form a cycle, period labels formed by different physical moments may correspond to the same period label, in order to ensure accuracy of calculation, the following formula is used to calculate the transmission period:

labeluut= { round dup (T1/T) } (cycle/T), where Labeluut represents the transmission period; roundup represents rounding up, e.g., roundup (3.5) =4; % represents the remainder.

In the embodiment of the application, the network device determines the residual jitter duration corresponding to the learning message by determining the jitter position of the learning message in the jitter range, and determines the second time for calculating the sending period according to the residual jitter duration. The waiting time period will vary according to the jitter position and is more accurate. Therefore, under the condition that the learning message is positioned at the tail part of the jitter range, the waiting time is reduced, so that the consumption of the buffer memory is reduced, and the total forwarding bandwidth of deterministic traffic is improved.

In some alternative embodiments, after step 305, the downstream device may further determine the cycle mapping relationship of the learning message according to the second cycle label corresponding to the transmission cycle and the first cycle label. The period mapping relation can be represented by a difference value of two period labels. It should be noted that, in practical application, since a plurality of periods form a cycle, the period labels formed by different physical moments may correspond to the same period label, or the value of the period label after the physical moment is smaller than the value of the period label before the physical moment, so that the difference value of the two period labels is directly calculated, and a correct period mapping relationship may not be obtained. Therefore, in some cases, it is necessary to convert two cycle labels into the same cycle through a certain conversion to obtain a correct cycle mapping relationship. This also requires that the number of cycles included in the cycle be at least one to satisfy jitter learning.

Alternatively, the period map delta may be derived based on the following formula:

delta= (labelout+cycle/T-label)% (cycle/T), wherein Labelout represents the value of the second cycle label, label represents the value of the first cycle label, cycle represents a cycle consisting of a plurality of cycles, T represents the period duration, and% represents the remainder.

In some alternative embodiments, if the value of the second periodic tag is greater than the value of the first periodic tag, the periodic mapping delta may be further based on the formula: delta = Labelout-label determination.

Next, referring to fig. 6 for a description of the message processing apparatus provided in the embodiment of the present application, fig. 6 is a schematic structural diagram of the message processing apparatus provided in the embodiment of the present application, where the message processing apparatus 600 includes:

the obtaining unit 601 is configured to obtain a learning message from an upstream device, where the learning message carries a first period tag, a sending timestamp, and jitter information, and the first period tag indicates a period of sending the learning message by the upstream device, and the sending timestamp is a time when the learning message is sent by the upstream device.

The processing unit 602 is further configured to determine a jitter position of the learning message in the jitter range according to the first period tag, the sending timestamp, and the jitter information.

The processing unit 602 is further configured to determine a remaining jitter duration corresponding to the learning message according to the jitter position.

The processing unit 602 is further configured to determine a second time corresponding to the learning message according to the remaining jitter duration and the first time for obtaining the learning message.

The processing unit 602 is further configured to determine a transmission period of the learning message according to the second time.

In the embodiment of the application, the message processing device determines the residual jitter duration corresponding to the learning message by determining the jitter position of the learning message in the jitter range, and determines the second time for calculating the sending period according to the residual jitter duration. The waiting time period will vary according to the jitter position and is more accurate. Therefore, under the condition that the learning message is positioned at the tail part of the jitter range, the waiting time is reduced, so that the consumption of the buffer memory is reduced, and the total forwarding bandwidth of deterministic traffic is improved.

In some alternative embodiments, the jitter information includes at least two of a jitter range, a maximum value of a transmission delay, or a minimum value of a transmission delay.

In some alternative embodiments, the processing unit 602 is specifically configured to determine the second time according to the remaining jitter duration, the period duration, the forwarding delay, and the first time.

In some optional embodiments, the processing unit 602 is further configured to determine the cycle mapping relationship of the learning message according to the second cycle tag corresponding to the transmission cycle and the first cycle tag.

The message processing apparatus 600 may perform the operations performed by the P device or the egress PE in the embodiments shown in fig. 1 and fig. 2 and the operations performed by the downstream device in the embodiments shown in fig. 3 to fig. 5, which are not described herein.

Next, a description will be given of a network device provided in an embodiment of the present application, and referring to fig. 7, fig. 7 is a schematic structural diagram of the network device provided in the embodiment of the present application.

The network device 700 includes: a processor 701 and a memory 702, the memory 702 storing one or more application programs or data.

Wherein the memory 702 may be volatile storage or persistent storage. The program stored in the memory 702 may include one or more modules, each of which may be used to perform a series of operations performed by the network device 700. Still further, the processor 701 may be in communication with the memory 702, executing a series of instruction operations in the memory 702 on the network device 700.

In the embodiment of the present application, the processor 701 may be one or more central processing units (central processing unit, CPU), and in the case where the processor 701 is one CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor 701 may be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution.

In the embodiment of the present application, the memory 702 may include, but is not limited to, nonvolatile memory such as Hard Disk Drive (HDD) or Solid State Drive (SSD), random access memory (random access memory, RAM), erasable programmable read-only memory (erasable programmable rOM, EPROM), read-only memory (rOM), or portable read-only memory (compact disc read-only memory, CD-rOM), etc. The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory in the embodiments of the present application may also be circuitry or any other device capable of implementing a memory function for storing program instructions and/or data.

The network device 700 may also include one or more communication interfaces 703, one or more operating systems, such as Windows Server ^TM ，Mac OS X ^TM ，Unix ^TM ,Linux ^TM ，FreeBSD ^TM Etc.

The network device 700 may perform the operations performed by the P device or the egress PE in the embodiments shown in fig. 1 and fig. 2, and the operations performed by the downstream device in the embodiments shown in fig. 3 to fig. 5, which are not described herein.

Based on the same conception as the above-described method embodiments, the present application embodiment also provides a computer-readable storage medium storing a computer program that is executed by hardware (e.g., a processor, etc.) to implement part or all of the steps of any one of the methods performed by any of the apparatuses in the embodiments of the present application.

Based on the same conception as the above method embodiments, the present application also provides a computer program product comprising program instructions for causing a computer to perform part or all of the steps of any one of the above methods when said computer program product is run on said computer.

Based on the same conception as the above method embodiments, the present application also provides a chip or a chip system, which chip may comprise a processor. The chip may further comprise or be coupled to a memory (or storage module) and/or a transceiver (or communication module), wherein the transceiver (or communication module) may be used to support wired and/or wireless communication of the chip, and the memory (or storage module) may be used to store a program that is invoked by the processor to perform the operations performed by the terminal or network device in any one of the possible implementations of the method embodiments, method embodiments described above. The chip system may include the above chip, and may also include the above chip and other discrete devices, such as a memory (or memory module) and/or a transceiver (or communication module).

Based on the same conception as the above method embodiments, the present application also provides a communication system, which may include at least one of the above ingress PE, P device, or egress PE. The communication system may be used to implement operations performed by a terminal or network device in any of the above-described method embodiments, as well as any of the possible implementations of the method embodiments. By way of example, the communication system may have a structure as shown in fig. 1.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. A method for processing a message, comprising:

acquiring a learning message from upstream equipment, wherein the learning message carries a first periodic tag, a sending time stamp and jitter information, the first periodic tag indicates the period of the upstream equipment for sending the learning message, and the sending time stamp is the moment of the upstream equipment for sending the learning message;

determining a jitter position of the learning message in a jitter range according to the first periodic label, the sending time stamp and the jitter information;

determining the residual jitter time length corresponding to the learning message according to the jitter position;

determining a second moment corresponding to the learning message according to the residual jitter duration and the first moment of acquiring the learning message;

and determining the sending period of the learning message according to the second moment.

2. The method of claim 1, wherein the jitter information comprises at least two of the jitter range, a maximum value of a transmission delay, or a minimum value of a transmission delay.

3. The method according to claim 1 or 2, wherein the determining the second time corresponding to the learning message according to the remaining jitter duration and the first time for obtaining the learning message includes:

and determining the second moment according to the residual jitter duration, the period duration, the forwarding delay and the first moment.

4. A method according to any one of claims 1 to 3, further comprising:

and determining the cycle mapping relation of the learning message according to the second cycle label corresponding to the sending cycle and the first cycle label.

5. A message processing apparatus, comprising:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a learning message from upstream equipment, the learning message carries a first periodic label, a sending time stamp and jitter information, the first periodic label indicates the period of the upstream equipment for sending the learning message, and the sending time stamp is the moment of the upstream equipment for sending the learning message;

a processing unit for:

6. The apparatus of claim 5, wherein the jitter information comprises at least two of the jitter range, a maximum value of a transmission delay, or a minimum value of a transmission delay.

7. The apparatus according to claim 5 or 6, wherein the processing unit is specifically configured to determine the second time according to the remaining jitter duration, the period duration, the forwarding delay and the first time.

8. The apparatus according to any one of claims 5 to 7, wherein the processing unit is further configured to determine a period mapping relationship of the learning message according to a second period label corresponding to the transmission period and the first period label.

9. A network device, comprising: a processor, a memory, and a communication interface;

the processor and the memory are connected with the communication interface;

the processor is configured to perform the method of any one of claims 1 to 4.

10. A computer readable storage medium storing instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 4.