CN116264200A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN116264200A
CN116264200A CN202211574121.8A CN202211574121A CN116264200A CN 116264200 A CN116264200 A CN 116264200A CN 202211574121 A CN202211574121 A CN 202211574121A CN 116264200 A CN116264200 A CN 116264200A
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China
Prior art keywords
metal pattern
semiconductor chip
electrode pad
semiconductor device
main surface
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CN202211574121.8A
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Chinese (zh)
Inventor
附田正则
西康一
曾根田真也
田中香次
境纪和
鹿野武敏
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN116264200A publication Critical patent/CN116264200A/en
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Abstract

A semiconductor device with high yield and easy manufacture is obtained. A1 st main electrode (10) and a 1 st control electrode pad (15) are formed on the 1 st main surface of a semiconductor chip (1). A2 nd main electrode (29) and a 2 nd control electrode pad (31) are formed on the 2 nd main surface of the semiconductor chip (1). The 2 nd main electrode (29) and the 2 nd control electrode pad (31) are bonded to the 1 st metal pattern (39) and the 2 nd metal pattern (40) of the insulating substrate (36), respectively. The bonding portion of the 1 st wire (42) and the 2 nd wire (43) overlaps the bonding portion of the 2 nd main electrode (29) or the 2 nd control electrode pad (31) in a plan view. The thickness of the 1 st metal pattern (39) and the 2 nd metal pattern (40) is 0.2mm or less.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
As a switching element, a semiconductor device having a double gate structure in which control electrode pads are provided on both surfaces of a cathode side and an anode side has been proposed, and a method of wire bonding to the control electrode pads on both surfaces has been shown as an example (for example, refer to patent document 1).
Patent document 1: japanese patent application laid-open No. 2021-34506
Disclosure of Invention
If the opposite surface cannot be fixed at the time of wire bonding, breakage or chipping of the semiconductor chip occurs due to the impact of ultrasonic waves. Therefore, wire bonding to the control electrode pads on both sides is difficult, and it is difficult to improve mass productivity even if it can be manufactured by a special method.
The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device having a high yield and being easy to manufacture.
The semiconductor device according to the present invention is characterized by comprising: a semiconductor chip having a 1 st main surface and a 2 nd main surface on opposite sides to each other; a 1 st main electrode formed on the 1 st main surface and electrically connected to the semiconductor chip; a 1 st control electrode pad formed on the 1 st main surface with a 1 st insulating film interposed between the 1 st control electrode pad and the semiconductor chip; a 2 nd main electrode formed on the 2 nd main surface and electrically connected to the semiconductor chip; a 2 nd control electrode pad formed on the 2 nd main surface with a 2 nd insulating film interposed between the 2 nd control electrode pad and the semiconductor chip; a 1 st wire bonded to the 1 st main electrode; a 2 nd wire bonded to the 1 st control electrode pad; and an insulating substrate having a 1 st metal pattern and a 2 nd metal pattern separated from each other, the 2 nd main electrode and the 2 nd control electrode pad being bonded to the 1 st metal pattern and the 2 nd metal pattern, respectively, a bonding portion of the 1 st wire and the 2 nd wire overlapping a bonding portion of the 2 nd main electrode or the 2 nd control electrode pad in a plan view, a thickness of the 1 st metal pattern and the 2 nd metal pattern being 0.2mm or less.
ADVANTAGEOUS EFFECTS OF INVENTION
In the present invention, the 2 nd main electrode and the 2 nd control electrode pad of the semiconductor chip are bonded to the 1 st metal pattern and the 2 nd metal pattern of the insulating substrate, respectively. This allows easy assembly by a general solder bonding process. The bonding portions of the 1 st wire and the 2 nd wire overlap the bonding portion of the 2 nd main electrode or the 2 nd control electrode pad in a plan view. The opposite surface of the bonding portion is fixed by the metal pattern, so that breakage of the semiconductor chip at the time of bonding can be prevented. The thickness of the metal pattern is 0.2mm or less. Thus, since the pattern accuracy of the metal pattern is improved, the shape of the metal pattern of the insulating substrate can be easily matched with the shapes of the collector electrode and the 2 nd gate electrode pad, and the bonding area between the two can be enlarged. This increases the mechanical strength and reduces the thermal resistance. Thus, the semiconductor device according to the present embodiment has high yield and is easy to manufacture.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor chip showing a dual gate structure.
Fig. 2 is a cross-sectional view showing the semiconductor device according to embodiment 1.
Fig. 3 is a top view of a semiconductor chip.
Fig. 4 is a bottom view of the semiconductor chip.
Fig. 5 is a plan view showing a positional relationship between a metal pattern of an insulating substrate and a semiconductor chip according to embodiment 1.
Fig. 6 is a cross-sectional view showing a semiconductor device according to a comparative example.
Fig. 7 is an enlarged cross-sectional view of a joint portion between an insulating substrate and a semiconductor chip.
Fig. 8 is a bottom view showing modification 1 of the semiconductor chip according to embodiment 1.
Fig. 9 is a plan view showing a metal pattern of an insulating substrate according to modification 1 of embodiment 1.
Fig. 10 is a bottom view showing modification 2 of the semiconductor chip according to embodiment 1.
Fig. 11 is a cross-sectional view showing a semiconductor device according to embodiment 2.
Fig. 12 is a cross-sectional view showing a modification of the semiconductor device according to embodiment 2.
Fig. 13 is a bottom view showing a semiconductor chip according to embodiment 3.
Fig. 14 is a plan view showing an insulating substrate according to embodiment 3.
Fig. 15 is a cross-sectional view showing a semiconductor device according to embodiment 3.
Fig. 16 is a cross-sectional view showing modification 1 of the semiconductor device according to embodiment 3.
Fig. 17 is a cross-sectional view showing modification 2 of the semiconductor device according to embodiment 3.
Fig. 18 is a cross-sectional view showing a semiconductor device according to embodiment 4.
Fig. 19 is a plan view showing a positional relationship between a metal pattern of an insulating substrate and a semiconductor chip according to embodiment 4.
Fig. 20 is a cross-sectional view showing modification 1 of the semiconductor device according to embodiment 4.
Fig. 21 is a cross-sectional view showing modification 2 of the semiconductor device according to embodiment 4.
Fig. 22 is a cross-sectional view showing a semiconductor device according to embodiment 5.
Fig. 23 is a cross-sectional view showing a modification of the semiconductor device according to embodiment 5.
Detailed Description
A semiconductor device according to an embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and a repetitive description thereof may be omitted.
Embodiment 1
Fig. 1 is a cross-sectional view of a semiconductor chip showing a dual gate structure. The semiconductor chip 1 has an emitter-side main surface and a collector-side main surface on opposite sidesIGBT chip. N is formed on the semiconductor chip 1 - A type drift layer 2. At n - A p-type base layer 3 having a predetermined thickness is formed on the drift layer 2. A plurality of trenches 4 penetrating the p-type base layer 3 to n - A type drift layer 2. The plurality of grooves 4 are arranged at predetermined intervals (intervals) and have a stripe structure extending parallel to the direction perpendicular to the paper surface of fig. 1 or a ring structure wound around the tip end after extending parallel.
The p-type base layer 3 is divided into a plurality of trenches 4. Part of which is a p-channel layer 5 constituting a channel region. n is n + The emitter region 6 is formed on the side surface of the trench 4 at the surface layer portion of the p-channel layer 5.n is n + Emitter regions 6 and n - The type drift layer 2 has a higher impurity concentration than the type drift layer. A gate electrode 7 made of doped polysilicon or the like is formed in the trench 4 through a gate insulating film 8. An insulating film 9 is formed on the emitter-side main surface of the semiconductor chip 1 so as to cover the upper side of the gate electrode 7.
An emitter electrode 10 is formed on the insulating film 9. The emitter electrode 10 is electrically connected to n via a contact hole 11 formed in the insulating film 9 + A type emitter region 6 and a p-channel layer 5.
A p-type diffusion layer 12 is formed on the n-type base layer 3 so as to surround the p-type base layer - Above the type drift layer 2. A doped polysilicon layer 13 is formed over the p-type diffusion layer 12 via an insulating film 9. The doped polysilicon layer 13 is electrically connected to the gate electrode 7, and the doped polysilicon layer 13 is electrically connected to the 1 st gate electrode pad 15 via a contact hole 14 formed in the insulating film 9. Accordingly, the gate electrode 7 is electrically connected to the outside via the doped polysilicon layer 13 and the 1 st gate electrode pad 15. Thus, an emitter side IGBT region is constituted.
In the outer peripheral region surrounding the emitter side IGBT region, at n - A plurality of p-type guard ring layers 16 are formed in a multiple-ring configuration over the type drift layer 2. The p-type diffusion layer 12 and the p-type guard ring layer 16 are formed deeper than the p-type base layer 3. A plurality of outer peripheral electrodes 17 are formed on the insulating film 9 and connected to the plurality of p-type guard ring layers 16 via contact holes 18, respectively. The plurality of peripheral electrodes 17 are electrically isolated from each other and have a multiple ring structure like the p-type guard ring layer 16。
In the manner of surrounding the p-type guard ring layer 16 at n - N is formed on the surface layer of the drift layer 2 + A mold layer 19. Electrode 20 is formed at n + Over the mold layer 19. n is n + The mold layer 19 and the electrode 20 are electrically connected to each other to form an equipotential ring (EQR) structure. The outer peripheral region is covered with a protective film 21 at a position where electrical connection is not made. In this way, the outer peripheral pressure-resistant holding structure 22 is formed in the outer peripheral region of the emitter-side main surface.
At n - P is formed under the drift layer 2 + A shaped collector layer 23. At n - Type drift layer 2 and p + A collector layer 23 having a junction n - N of higher impurity concentration than the type drift layer 2 + A field stop layer 24. At p + The collector side surface of the collector layer 23 is selectively formed with a high concentration of n + And a collector layer 25.
A plurality of trenches 26 for penetrating p + Collector layers 23, n + Collector layer 25 and n + A field stop layer 24 reaching n - The type drift layer 2 is formed. The plurality of grooves 26 are arranged at predetermined intervals, for example, at equal intervals in a stripe shape. A control gate electrode 27 made of doped polysilicon or the like is formed in the trench 26 through a gate insulating film 28. All control gate electrodes 27 are electrically connected to each other in other cross sections.
Collector electrodes 29 and p + Collector layer 23 and n + The collector layer 25 is in contact and electrically connected. An insulating film 30 is formed on the collector side main surface of the semiconductor chip 1 so as to cover the control gate electrode 27.
The 2 nd gate electrode pad 31 is electrically connected to the doped polysilicon layer 33 via a contact hole 32 formed in the insulating film 30. The doped polysilicon layer 33 is connected to the control gate electrode 27 via a contact hole 34 formed in the insulating film 30. The collector electrode 29 is disposed so as to surround the 2 nd gate electrode pad 31 covered with the protective film 35, and the collector electrode 29 is separated from the control gate electrode 27 by the insulating film 30 and the protective film 35. Thus, the collector side IGBT region is constituted.
Fig. 2 is a cross-sectional view showing the semiconductor device according to embodiment 1. An emitter electrode 10 and a 1 st gate electrode pad 15 are formed on the emitter-side main surface of the semiconductor chip 1. The outer Zhou Naiya holding structure 22 is formed on the emitter-side main surface in an outer peripheral region surrounding the emitter electrode 10 and the 1 st gate electrode pad 15. A collector electrode 29 and a 2 nd gate electrode pad 31 are formed on the collector side main surface of the semiconductor chip 1.
The insulating substrate 36 includes an insulating material 37, a metal layer 38 formed on a lower surface of the insulating material 37, and metal patterns 39 and 40 formed on an upper surface of the insulating material 37. The metal patterns 39, 40 are separated from each other and bonded to the collector electrode 29 and the 2 nd gate electrode pad 31 of the semiconductor chip 1, respectively, by solder 41. By separating the metal patterns 39, 40, a control signal of the order of several volts to 20 volts can be applied between the collector electrode 29 and the 2 nd gate electrode pad 31.
Wires 42 and 43 are bonded to the emitter electrode 10 and the 1 st gate electrode pad 15, respectively. Wires 44 and 45 are bonded to the metal patterns 39 and 40, respectively. The joint of the wire 42 bonded to the emitter electrode 10 and the joint of the wire 43 bonded to the 1 st gate electrode pad 15 overlap with the solder joint of the collector electrode 29 or the 2 nd gate electrode pad 31 in a plan view. This can prevent breakage due to ultrasonic waves at the time of wire bonding.
Fig. 3 is a top view of a semiconductor chip. The 1 st gate electrode pad 15 is located slightly closer to the center of the chip. The 1 st gate electrode pad 15 is not limited to this, and the wire 43 may be bonded to the center of the chip, and the wire 43 may be bonded to a position near one corner.
Fig. 4 is a bottom view of the semiconductor chip. The 2 nd gate electrode pad 31 is formed at a corner of the chip. The 2 nd gate electrode pad 31 may be provided at the center of the chip, or may be provided on any side. The 2 nd gate electrode pad 31 is provided at the corner or side of the chip, so that patterning is easily performed without crossing the metal pattern 39 bonded to the collector electrode 29 and the metal pattern 40 bonded to the 2 nd gate electrode pad 31. Although the 2 nd gate electrode pad 31 can be formed in the central portion of the chip, as described below, it is necessary to insulate the metal patterns 39 and 40 from each other, or to use the insulating substrate 36 and the via hole of the multilayer electrode layer.
Fig. 5 is a plan view showing a positional relationship between a metal pattern of an insulating substrate and a semiconductor chip according to embodiment 1. The dashed line indicates the semiconductor chip 1. The portions of the insulating substrate 36 where the metal patterns 39, 40 are not formed coincide with the portions of the semiconductor chip 1 where the collector electrode 29 and the 2 nd gate electrode pad 31 are not formed. This prevents a short circuit between the collector electrode 29 and the 2 nd gate electrode pad 31, and a control signal is applied to the 2 nd gate electrode pad 31. In the present embodiment, the pattern interval of the insulating substrate 36 is narrower than the pattern interval of the semiconductor chip 1. The present invention is not limited to this, and the collector electrode 29 and the 2 nd gate electrode pad 31 may be formed so as not to contact each other and short-circuit, and thus the semiconductor chip 1 may have a wider pattern interval or may have two patterns aligned.
Next, the effects of the present embodiment will be described in comparison with comparative examples. Fig. 6 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, the wire 46 was directly bonded to the 2 nd gate electrode pad 31 on the lower surface of the chip. However, since wire bonding is also provided on the upper surface of the chip, the upper surface of the chip cannot be fixed by solder or the like. Therefore, breakage or chipping of the semiconductor chip 1 occurs by the impact of ultrasonic waves at the time of wire bonding. In the case where the bonding of the lower surface of the chip is advanced in order to avoid this, the insulating substrate 36 becomes an obstacle, and the tip (tool) for melting the wire by applying the ultrasonic wave cannot be brought into contact with the 2 nd gate electrode pad 31. Therefore, the semiconductor device of the comparative example is difficult to manufacture, and it is difficult to improve mass productivity even if it can be manufactured by a special method.
In contrast, in the present embodiment, the collector electrode 29 and the 2 nd gate electrode pad 31 of the semiconductor chip 1 are solder-bonded to the metal patterns 39, 40 of the insulating substrate 36, respectively. This makes it possible to easily assemble the solder by a general solder bonding process.
The bonding portions of the wires 42 and 43 overlap with the solder bonding portions of the collector electrode 29 or the 2 nd gate electrode pad 31 in a plan view. Since the opposite surfaces of the bonding portions are fixed, breakage of the semiconductor chip 1 at the time of bonding can be prevented.
Fig. 7 is an enlarged cross-sectional view of a joint portion between an insulating substrate and a semiconductor chip. The distance between the collector electrode 29 and the 2 nd gate electrode pad 31 is set to 0.5mm or less in terms of the pattern matching accuracy of the semiconductor chip 1 and the insulating substrate 36 and the insulation distance between the electrodes. The thinner the metal pattern is, the finer the processing becomes, and therefore, the thickness of the metal patterns 39 and 40 connected to the collector electrode 29 and the 2 nd gate electrode pad 31 needs to be made thinner. The metal patterns 39 and 40 are processed by wet etching with high productivity. Therefore, the thicknesses of the metal patterns 39, 40 are made 0.2mm or less taking into consideration the side etching in which the pattern thickness amounts from both sides exist. Accordingly, since the pattern accuracy of the metal patterns 39 and 40 is improved, the shape of the metal patterns 39 and 40 of the insulating substrate 36 can be easily matched with the shapes of the collector electrode 29 and the 2 nd gate electrode pad 31, and the bonding area between the two can be enlarged. Thus, the mechanical strength increases and the thermal resistance decreases. Thus, the semiconductor device according to the present embodiment has high yield and is easy to manufacture.
In addition, the thicker the metal pattern is, the smaller the lateral resistance is, the larger the current can flow, the lateral thermal resistance is also reduced, the heat is diffused to the periphery of the chip, and the heat dissipation is improved. Therefore, the thickness of the usual metal pattern is about 0.3 mm. In contrast, in the present invention, the thicknesses of the metal patterns 39 and 40 are intentionally 0.2mm or less for the reasons described above.
Fig. 8 is a bottom view showing modification 1 of the semiconductor chip according to embodiment 1. A 2 nd gate electrode pad 31 is formed in a central portion of the lower surface of the semiconductor chip 1, and a collector electrode 29 is formed around the same. A slit 47 in which the collector electrode 29 is not present is formed in a part of the lower surface of the semiconductor chip 1 from the central portion toward the outer peripheral portion of the semiconductor chip 1. Fig. 9 is a plan view showing a metal pattern of an insulating substrate according to modification 1 of embodiment 1. The metal patterns 39, 40 are separated from each other. The metal pattern 40 is led out of the semiconductor chip 1 from the central portion of the semiconductor chip 1 through the slit 47 in a plan view. Thus, the metal pattern 40 does not contact the collector electrode 29, and thus a short circuit between the collector electrode 29 and the 2 nd gate electrode pad 31 can be prevented.
Fig. 10 is a bottom view showing modification 2 of the semiconductor chip according to embodiment 1. A 2 nd gate electrode pad 31 is formed in a central portion of the lower surface of the semiconductor chip 1, and a collector electrode 29 is formed around the same. An insulating film 48 is formed from the central portion toward the outer peripheral portion of the semiconductor chip 1 so as to cover a part of the collector electrode 29. The metal patterns 39 and 40 of the insulating substrate 36 are the same as those of modification 1. The metal pattern 40 is led out of the semiconductor chip 1 from the central portion of the semiconductor chip 1 through the region where the insulating film 48 is formed in a plan view. Thus, the metal pattern 40 does not contact the collector electrode 29, and thus a short circuit between the collector electrode 29 and the 2 nd gate electrode pad 31 can be prevented. Further, the insulating film 48 may be formed by combining the modifications 1 and 2, and avoiding interference by patterning the collector electrode 29. In addition, as long as the collector electrode 29 and the 2 nd gate electrode pad 31 are not shorted, the 2 nd gate electrode pad 31 may be disposed at a corner or the like.
Embodiment 2
Fig. 11 is a cross-sectional view showing a semiconductor device according to embodiment 2. The semiconductor chip 1 is mounted by turning up and down as compared with embodiment 1. The emitter electrode 10 and the 1 st gate electrode pad 15 of the semiconductor chip 1 are solder-bonded to the metal patterns 39, 40 of the insulating substrate 36, respectively. Wires 42 and 43 are bonded to the collector electrode 29 and the 2 nd gate electrode pad 31, respectively. The emitter side of the semiconductor chip 1 having large heat generation is bonded to the insulating substrate 36, which is a heat dissipation path, and therefore has more excellent heat dissipation performance than embodiment 1.
In addition, when electrode pads for temperature sensing or current sensing are formed on the emitter side of the semiconductor chip 1, these electrode pads can be bonded to the metal pattern of the insulating substrate 36. In addition, when the 1 st gate electrode pad 15 is disposed in the central portion of the chip, the structures of modification examples 1 and 2 of embodiment 1 are applied.
Fig. 12 is a cross-sectional view showing a modification of the semiconductor device according to embodiment 2. A voltage of several thousand volts is applied between the outer peripheral portion of the outer Zhou Naiya retaining structure 22 and the metal pattern 39. For insulation, a part of the metal pattern 39 is partially thinned compared with the surrounding area in the area facing the outer Zhou Naiya holding structure 22, and the distance between the two is increased.
Embodiment 3
Fig. 13 is a bottom view showing a semiconductor chip according to embodiment 3. A 2 nd gate electrode pad 31 is formed in a central portion of the lower surface of the semiconductor chip 1, and a collector electrode 29 is formed around the same.
Fig. 14 is a plan view showing an insulating substrate according to embodiment 3. A metal pattern 39 is formed around the metal pattern 40. A metal pattern 49 is formed at a position outside the semiconductor chip 1 in a plan view. The metal patterns 39, 40, 49 are separated from each other.
Fig. 15 is a cross-sectional view showing a semiconductor device according to embodiment 3. The metal layer 38 formed on the lower surface of the insulating layer 37a is used for grounding or the like, and is not used as a metal pattern for safety. The metal layer 50 is formed on the insulating layer 37 a. An insulating layer 37b is formed over the metal layer 50. Metal patterns 39, 40, 49 are formed on the insulating layer 37b. Therefore, the conductor layer of the insulating substrate is 3 layers.
An opening 51 is formed in the insulating layer 37b. The metal layer 50 inside the substrate is connected to the metal pattern 40 via the opening 51. The metal layer 50 is connected to the metal pattern 49 via a via hole 52 formed in the insulating layer 37b. Thus, the 2 nd gate electrode pad 31 formed in the central portion of the lower surface of the semiconductor chip 1 can be led out to the outside through the metal pattern 40, the metal layer 50, and the metal pattern 49. Other structures and effects are the same as those of embodiment 1.
Fig. 16 is a cross-sectional view showing modification 1 of the semiconductor device according to embodiment 3. In combination with the structure of embodiment 2, the semiconductor chip 1 is mounted by being turned upside down as compared with embodiment 3. The emitter electrode 10 and the 1 st gate electrode pad 15 of the semiconductor chip 1 are solder-bonded to the metal patterns 39, 40 of the insulating substrate 36, respectively. Wires 42 and 43 are bonded to the collector electrode 29 and the 2 nd gate electrode pad 31, respectively. Since the emitter side of the semiconductor chip 1 having large heat generation is bonded to the insulating substrate 36 as a heat dissipation path, the heat dissipation performance is more excellent than that of embodiment 3.
In addition, when electrode pads for temperature sensing or current sensing are formed on the emitter side of the semiconductor chip 1, these electrode pads can be bonded to the metal pattern of the insulating substrate 36. In addition, when the 1 st gate electrode pad 15 is disposed in the central portion of the chip, the structures of modification examples 1 and 2 of embodiment 1 are applied.
Fig. 17 is a cross-sectional view showing modification 2 of the semiconductor device according to embodiment 3. In combination with the structure of embodiment 2, a voltage of several thousand volts is applied between the outer peripheral portion of the holding structure 22 and the metal pattern 39 to the outside Zhou Naiya. For insulation, a part of the metal pattern 39 is partially thinned compared with the surrounding area in the area facing the outer Zhou Naiya holding structure 22, and the distance between the two is increased.
Embodiment 4
Fig. 18 is a cross-sectional view showing a semiconductor device according to embodiment 4. A large opening 51 is formed immediately below the semiconductor chip 1 in the insulating layer 37b near the chip. The metal layer 50 is connected to the metal pattern 39 via the opening 51.
Even if the metal patterns 39, 40 bonded to the semiconductor chip 1 are as thin as 0.2mm or less, current flows through the metal layer 50 via the opening 51, and thus loss (resistance) becomes small. In addition, heat is radiated through the metal layer 50 at the opening 51, so that the thermal resistance does not rise.
Fig. 19 is a plan view showing a positional relationship between a metal pattern of an insulating substrate and a semiconductor chip according to embodiment 4. The opening 51 is circular and is arranged so as to overlap the semiconductor chip 1 in a plan view. In order to lead from the metal layer 50 of the inner layer to the metal pattern 39 on the surface side, a small-diameter via hole 52 is formed.
Fig. 20 is a cross-sectional view showing modification 1 of the semiconductor device according to embodiment 4. The metal pattern 39 is separated from the bonding portion of the semiconductor chip 1 and the bonding portion of the wire 44. The two are electrically connected to the metal layer 50 of the inner layer, and thus there is no problem even in this method. However, from the viewpoints of heat dissipation and low loss, it is preferable that the two are not separated.
Fig. 21 is a cross-sectional view showing modification 2 of the semiconductor device according to embodiment 4. The formation of the large diameter openings 51 shown in fig. 18-19 requires special processing techniques. Thus, a plurality of small-diameter openings 51 are formed instead of the large-diameter openings 51. Therefore, loss and thermal resistance are not increased, cost is reduced, and productivity is improved.
In addition, the insulating layer 37a and the insulating layer 37b are made of the same material. Therefore, the insulating layer 37a and the insulating layer 37b are easily integrally formed. Further, since the insulating layer 37a and the insulating layer 37b have the same thermal expansion coefficient, the reliability is high.
Embodiment 5
Fig. 22 is a cross-sectional view showing a semiconductor device according to embodiment 5. An insulating substrate 36b is laminated on the insulating substrate 36 a. On the insulating substrate 36a, a metal layer 38 is formed on the lower surface of the insulating layer 37a, and a metal layer 53 is formed on the upper surface. On the insulating substrate 36b, a metal layer 54 is formed on the lower surface of the insulating layer 37b, and metal patterns 39 and 40 are formed on the upper surface. The metal layer 53 of the insulating substrate 36a is bonded to the metal layer 54 of the insulating substrate 36b by the solder 41. Instead of the solder 41, other bonding materials such as silver nanopaste or copper nanopaste may be used. The insulating layer 37a and the insulating layer 37b may be integrally formed, and the metal layer therebetween may be 1 layer.
The insulating layer 37b near the semiconductor chip 1 requires refinement of the pattern, precision, ease of processing of the opening 51, difficulty in breaking, and the like. On the other hand, the insulating layer 37a distant from the semiconductor chip 1 needs to have heat radiation properties, i.e., needs to have low thermal resistance. Accordingly, the insulating layer 37a and the insulating layer 37b are made of different materials, and the most suitable materials are selected. Specifically, the insulating layer 37a is a ceramic substrate such as aluminum nitride, silicon nitride, or aluminum oxide, which has low thermal resistance. The insulating layer 37b is a glass epoxy substrate or a resin sheet. Since the ceramic substrate is easily broken and a brazing material is used for bonding the insulating substrate and the metal pattern, the pattern accuracy is poor and the minimum size and error are large. On the other hand, the glass epoxy resin substrate or the resin sheet is hardly broken, and a hot press is used for bonding the insulating substrate and the metal sheet, so that the pattern accuracy is high.
Fig. 23 is a cross-sectional view showing a modification of the semiconductor device according to embodiment 5. In fig. 22, the wire 44 is bonded to the metal pattern 39 of the insulating substrate 36b, but in fig. 23, is bonded to the metal layer 53 of the insulating substrate 36 a. Thereby, the loss becomes small.
The semiconductor chip 1 is not limited to being formed of silicon, and may be formed of a wide band gap semiconductor having a band gap larger than that of silicon. The wide band gap semiconductor is, for example, silicon carbide, gallium nitride-based material, or diamond. The semiconductor chip formed of such a wide band gap semiconductor has high withstand voltage and allowable current density, and thus can be miniaturized. By using such a miniaturized semiconductor chip, a semiconductor device incorporating the semiconductor chip can also be miniaturized and highly integrated. Further, since the semiconductor chip has high heat resistance, the heat radiation fins of the heat sink can be miniaturized, and the water cooling portion can be cooled by air, so that the semiconductor device can be further miniaturized. In addition, the semiconductor chip has low power consumption and high efficiency, and therefore the semiconductor device can be made efficient.
Description of the reference numerals
1 semiconductor chip, 8, 28 gate insulating film, 10 emitter electrode, 15 1 st gate electrode pad, 22 outer Zhou Naiya holding structure, 29 collector electrode, 31 2 nd gate electrode pad, 36a, 36b insulating substrate, 37a, 37b insulating layer, 39, 40 metal pattern, 42, 43 wire, 47 slit, 48 insulating film, 50 metal layer, 51 opening, 52 via.

Claims (14)

1. A semiconductor device is characterized by comprising:
a semiconductor chip having a 1 st main surface and a 2 nd main surface on opposite sides to each other;
a 1 st main electrode formed on the 1 st main surface and electrically connected to the semiconductor chip;
a 1 st control electrode pad formed on the 1 st main surface with a 1 st insulating film interposed between the 1 st control electrode pad and the semiconductor chip;
a 2 nd main electrode formed on the 2 nd main surface and electrically connected to the semiconductor chip;
a 2 nd control electrode pad formed on the 2 nd main surface with a 2 nd insulating film interposed between the 2 nd control electrode pad and the semiconductor chip;
a 1 st wire bonded to the 1 st main electrode;
a 2 nd wire bonded to the 1 st control electrode pad; and
an insulating substrate having a 1 st metal pattern and a 2 nd metal pattern separated from each other,
the 2 nd main electrode and the 2 nd control electrode pad are bonded to the 1 st metal pattern and the 2 nd metal pattern respectively,
the bonding portions of the 1 st wire and the 2 nd wire overlap with the bonding portion of the 2 nd main electrode or the 2 nd control electrode pad in a plan view,
the thickness of the 1 st metal pattern and the 2 nd metal pattern is less than or equal to 0.2mm.
2. The semiconductor device according to claim 1, wherein,
the interval between the 2 nd main electrode and the 2 nd control electrode bonding pad is less than or equal to 0.5mm.
3. The semiconductor device according to claim 1 or 2, wherein,
forming the 2 nd control electrode pad at a central portion of the 2 nd main surface of the semiconductor chip,
a slit in which the 2 nd main electrode is not present is formed from the central portion toward the outer peripheral portion of the 2 nd main surface,
the 2 nd metal pattern is led out from the central portion of the semiconductor chip to the outside of the semiconductor chip through the slit in a plan view.
4. The semiconductor device according to claim 1 or 2, wherein,
forming the 2 nd control electrode pad at a central portion of the 2 nd main surface of the semiconductor chip,
an insulating film is formed from the central portion of the 2 nd main surface toward the outer peripheral portion so as to cover a part of the 2 nd main electrode,
the 2 nd metal pattern is led out from the central portion of the semiconductor chip to the outside of the semiconductor chip through a region where the insulating film is formed in a plan view.
5. A semiconductor device is characterized by comprising:
a semiconductor chip having a 1 st main surface and a 2 nd main surface on opposite sides to each other;
a 1 st main electrode formed on the 1 st main surface and electrically connected to the semiconductor chip;
a 1 st control electrode pad formed on the 1 st main surface with a 1 st insulating film interposed between the 1 st control electrode pad and the semiconductor chip;
a 2 nd main electrode formed on the 2 nd main surface and electrically connected to the semiconductor chip;
a 2 nd control electrode pad formed on the 2 nd main surface with a 2 nd insulating film interposed between the 2 nd control electrode pad and the semiconductor chip;
a 1 st wire bonded to the 2 nd main electrode;
a 2 nd wire bonded to the 2 nd control electrode pad; and
an insulating substrate having a 1 st metal pattern and a 2 nd metal pattern separated from each other,
the 1 st main electrode and the 1 st control electrode pad are bonded to the 1 st metal pattern and the 2 nd metal pattern respectively,
the bonding portions of the 1 st wire and the 2 nd wire overlap with the bonding portion of the 1 st main electrode or the 1 st control electrode pad in a plan view,
the thickness of the 1 st metal pattern and the 2 nd metal pattern is less than or equal to 0.2mm.
6. The semiconductor device according to claim 5, wherein,
further comprising an outer Zhou Naiya holding structure formed on an outer peripheral region of the 1 st main surface so as to surround the 1 st main electrode and the 1 st control electrode pad,
a portion of the thickness of the 1 st metal pattern is partially thinned in a region opposite to the outer Zhou Naiya holding structure.
7. The semiconductor device according to any one of claims 1 to 6, wherein,
the insulating substrate has a 1 st insulating layer, a metal layer formed over the 1 st insulating layer, and a 2 nd insulating layer formed over the metal layer,
forming the 1 st metal pattern and the 2 nd metal pattern on the 2 nd insulating layer,
an opening is formed in the 2 nd insulating layer,
the metal layer is connected to the 1 st metal pattern or the 2 nd metal pattern via the opening.
8. The semiconductor device according to claim 7, wherein,
the device is provided with: a 3 rd metal pattern formed on the 2 nd insulating layer, separate from the 1 st metal pattern and the 2 nd metal pattern; and
a via hole formed in the 2 nd insulating layer to connect the metal layer and the 3 rd metal pattern,
the metal layer is connected to the 2 nd metal pattern via the opening.
9. The semiconductor device according to claim 7 or 8, wherein,
the opening is formed directly under the semiconductor chip,
the metal layer is connected to the 1 st metal pattern via the opening.
10. A semiconductor device according to any one of claims 7 to 9, wherein,
the 1 st insulating layer and the 2 nd insulating layer are composed of the same material.
11. A semiconductor device according to any one of claims 7 to 9, wherein,
the 1 st insulating layer and the 2 nd insulating layer are composed of different materials.
12. The semiconductor device according to claim 11, wherein,
the 1 st insulating layer is a ceramic substrate,
the 2 nd insulating layer is a glass epoxy resin substrate or a resin sheet.
13. The semiconductor device according to any one of claims 1 to 12, wherein,
the semiconductor chip is an IGBT or an RC-IGBT.
14. The semiconductor device according to any one of claims 1 to 13, wherein,
the semiconductor chip is formed of a wide bandgap semiconductor.
CN202211574121.8A 2021-12-13 2022-12-08 Semiconductor device with a semiconductor device having a plurality of semiconductor chips Pending CN116264200A (en)

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