CN116259654A

CN116259654A - Metal carbon barrier for NMOS device contacts

Info

Publication number: CN116259654A
Application number: CN202211389785.7A
Authority: CN
Inventors: A·森古普塔; G·W·杜威; S·舒克赛; N·哈拉蒂普; J·T·卡瓦列罗斯; M·V·梅茨; S·B·克伦德宁; J·C·雷塔什凯特; E·O·小约翰逊
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2021-12-09
Filing date: 2022-11-08
Publication date: 2023-06-13
Also published as: US20230187553A1; EP4195289A1

Abstract

Described herein are integrated circuit devices with source and drain (S/D) contacts having blocking regions. The S/D contacts conduct current to and from the semiconductor device, for example, to the source and drain regions of the transistor. A blocking region is formed between the S/D region and the internal conductive structure and reduces the schottky barrier height between the S/D region and the contact. The barrier region may include one or more carbon layers and one or more metal layers. The metal layer may comprise niobium, tantalum, aluminum or titanium.

Description

Metal carbon barrier for NMOS device contacts

Technical Field

The present disclosure relates generally to the field of Integrated Circuit (IC) structures and devices, and more particularly to contact materials incorporated into such IC structures and devices.

Background

In an IC device, conductive contacts provide conductive paths for transistors and other circuit elements. For example, transistors typically have source and drain contacts coupled to respective source and drain regions in the transistor. The source and drain contacts are typically more conductive than the source and drain regions, for example, the source and drain contacts may be a metal or metal alloy, and the source and drain regions are doped semiconductors. The source and drain contacts are further coupled to an interconnect that transmits signals from or to another portion of the IC device.

Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, like reference numerals refer to like structural elements. The embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Fig. 1 is a cross-sectional view illustrating an exemplary arrangement of a single transistor single capacitor (1T-1C) memory cell with source and drain contacts according to some embodiments of the present disclosure.

Fig. 2 is a perspective view of a cross section of a contact located over a source or drain, and silicide is formed between the contact and the source or drain.

Fig. 3 is a perspective view of a cross section of a contact over a source or drain, where the contact has a blocking region, according to some embodiments of the present disclosure.

Fig. 4 is a cross-sectional view of a carbon-metal barrier region according to some embodiments of the present disclosure.

Fig. 5 is a cross-sectional view of a carbon-metal barrier with a metal carbide layer according to some embodiments of the present disclosure.

Fig. 6 is a cross-sectional view of a carbon-metal-carbon blocking region according to some embodiments of the present disclosure.

Fig. 7 is a cross-sectional view of a carbon-metal-carbon barrier with two metal carbide layers according to some embodiments of the present disclosure.

Fig. 8 is a cross-sectional view of a carbon-metal-carbon barrier with three metal carbide layers according to some embodiments of the present disclosure.

Fig. 9A-9B are perspective and cross-sectional views, respectively, of an exemplary transistor implemented as a FinFET having source and drain contacts with metal and carbon blocking regions, in accordance with some embodiments of the present disclosure.

Fig. 10 is a flowchart illustrating a method for forming source and drain contacts with metal and carbon blocking regions, according to some embodiments of the present disclosure.

Fig. 11A and 11B are top views of a wafer and die including contacts with metal and carbon blocking regions according to any of the embodiments disclosed herein.

Fig. 12 is a cross-sectional side view of an IC device that may include contacts with metal and carbon blocking regions according to any of the embodiments disclosed herein.

Fig. 13 is a cross-sectional side view of an IC device assembly that may include contacts with metal and carbon blocking regions according to any of the embodiments disclosed herein.

Fig. 14 is a block diagram of an exemplary computing device that may include a contact having a metal and carbon blocking region according to any embodiment disclosed herein.

Detailed Description

SUMMARY

The systems, methods, and apparatus of the present disclosure each have several innovative aspects, no single one of which solely bears upon all of the desirable attributes disclosed herein. The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

IC devices having source and drain contacts with internal conductive structures and barrier regions, and methods for producing such devices, are described herein. The IC device includes various circuit elements, such as transistors and capacitors, coupled together by metal interconnects. The circuit elements typically include semiconductor material coupled to the interconnect through contacts (also referred to as electrodes).

An exemplary IC device includes a memory cell for storing data bits. A memory cell may include a capacitor for storing a bit value or memory state (e.g., a logic "1" or "0") of the cell, and an access transistor that controls access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell", focusing on the fact that it uses one transistor (i.e., the term "1T" in the "1T-1C memory cell") and one capacitor (i.e., the term "1C" in the "1T-1C memory cell"). The capacitor of the 1T-1C memory cell may be coupled to one source or drain (S/D) region/terminal of the access transistor (e.g., to the source region of the access transistor) through a first S/D contact, while the other S/D region of the access transistor may be coupled to a Bit Line (BL) through a second S/D contact, and the gate terminal of the transistor may be coupled to a Word Line (WL) through a gate contact. Conventionally, various 1T-1C memory cells have been implemented using access transistors based on front end of line (FEOL) logic processes as transistors implemented in the uppermost layer of a semiconductor substrate.

A transistor, such as the access transistor of the memory cell described above, includes channel material in which two S/D regions are formed. The channel material is typically a semiconductor, such as silicon (Si). Various semiconductor materials have been used as transistor channel materials, such as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Portions of the channel region may be highly doped to form S/D regions.

Common source and drain (S/D) contacts for semiconductor devices include one or more metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these materials. For example, titanium (Ti) and titanium nitride (TiN) are commonly used to form S/D contacts.

When previous S/D contact materials (e.g., ti and TiN) are used in combination with silicon or silicon-based channels, the contact materials and Si interact and form silicides. For example, the Ti contact reacts with the Si S/D region to form titanium silicide (TiSi ₂ ). The silicide creates an interfacial layer between the S/D regions and the contacts, which is not desirable. The silicide has a relatively high Schottky barrier height, e.g. TiSi ₂ Having a schottky barrier height of about 0.55 eV. It is desirable to reduce the schottky barrier height between the S/D regions and the contacts.

The barrier regions described herein reduce the schottky barrier height between the Si S/D regions and the S/D contacts. The barrier region includes carbon and a metal such as niobium (Nb), tantalum (Ta), aluminum (Al), or titanium (Ti). The barrier region prevents formation of TiSi by physically separating Si S/D from Ti or TiN contact materials ₂ . In addition to TiSi ₂ Compared with the prior art, the carbon and metal barrier region has lower Schottky barrier height<0.55 eV). For example, the schottky barrier height of the barrier regions disclosed herein may be in the range of 0.30eV to 0.47 eV.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details, or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

Various operations are described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

For the purposes of this disclosure, the phrase "a and/or B" means (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The term "between" when used with reference to a measurement range includes the ends of the measurement range. The meaning of "a" and "an" includes a plurality of references. The meaning of "in … …" includes "in … …" and "on … …".

The description uses the phrase "in an embodiment," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The present disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are provided for ease of discussion and are not intended to limit the application of the disclosed embodiments. The figures are not necessarily drawn to scale. The terms "substantially," "near," "approximately," "near," and "approximately" generally mean within +/-20% of the target value. Unless otherwise indicated, the use of ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

In the following detailed description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a "logic state" of a ferroelectric memory cell refers to one of a limited number of states that the cell may have, e.g., logic states "1" and "0", each represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, "reading" and "writing" memory accesses or operations refer to determining/sensing and programming/setting, respectively, the logic state of a memory cell. In other examples, the term "connected" means a direct electrical or magnetic connection between the things being connected, without any intervening devices; and the term "coupled" means a direct electrical or magnetic connection between the things being connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components arranged to cooperate to provide a desired function. In yet another example, a "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide. The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

Exemplary memory cell with S/D contact

Fig. 1 is a cross-sectional view showing an exemplary arrangement of a single transistor single capacitor (1T-1C) memory cell 100 with source and drain contacts according to some embodiments of the present disclosure.

The 1T-1C memory cell 100 is formed over a support structure 102. The 1T-1C memory cell 100 includes a transistor 101 coupled to a pair of S/

D contacts

112a and 112b, wherein the S/D contact 112 includes a blocking region not specifically shown in FIG. 1. One of the S/D contacts 112b is coupled to a capacitor 116 for storing a data bit. Transistor 101 is an access transistor that controls access to capacitor 116 to write information to capacitor 116 or read information from capacitor 116. The various elements referenced by reference numerals in the description of fig. 1-8 are shown in different patterns in these figures, with legends showing correspondence between reference numerals and patterns provided at the bottom or side of each drawing page containing fig. 1-8. For example, the illustration in fig. 1 shows that fig. 1 uses different patterns to illustrate the support structure 102, the gate electrode 104, the gate dielectric 106, the channel material 108, the S/D regions 110, the S/D contacts 112, and the capacitor 116.

In the drawings, some example structures of the various devices and components described herein are shown with precise right angles and straight lines, but it should be understood that such schematic diagrams may not reflect real-life process limitations that may result in features that do not appear to be so "ideal" when any of the structures described herein are inspected using, for example, scanning Electron Microscope (SEM) images or Transmission Electron Microscope (TEM) images. Possible processing defects may also be visible in such images of real structures, such as incompletely straight edges of material, tapered vias or other openings, inadvertent rounding of corners or variations in thickness of different material layers, occasional threading, edge or combination dislocations within crystalline regions, and/or occasional dislocation defects of single atoms or clusters. Other drawbacks not listed here but common in the field of device manufacturing may exist.

Transistor 101 includes a gate electrode 104, a gate dielectric 106, a channel material 108, and two S/D regions 110. The gate electrode 104 may be coupled to the WL, for example, via a gate via not specifically shown in fig. 1. WL may be coupled to a row of similar memory cells. The first S/D region 110a is coupled to the first S/D contact 112a and the second S/D region 110b is coupled to the second S/D contact 112b. The first S/D contact 112a may be coupled to a BL that is coupled to a column of similar memory cells. The second S/D contact 112a is coupled to one electrode of the capacitor 116. Capacitor 116 may have a second electrode coupled to a Plate Line (PL) (not shown in fig. 1), as is known in the art.

In general, embodiments of the present disclosure may be formed or performed on a support structure 102 (e.g., a semiconductor substrate composed of a semiconductor material system, and in particular, a semiconductor substrate composed of an N-type material system). In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described herein, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure. In various embodiments, support structure 102 may include any substrate that provides a suitable surface for providing the memory cell shown in fig. 1.

The transistor 101 is formed over a support structure 102. The gate electrode 104 and the gate dielectric 106 form a gate stack. The gate electrode 104 may include at least one N-type work function metal and the transistor 101 is an NMOS transistor. For NMOS transistors, metals that may be used for gate electrode 104 include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). Other materials that may be used include titanium nitride, tantalum nitride, hafnium nitride, tungsten, iridium, copper, or degenerately doped polysilicon. In some embodiments, the gate electrode 104 may be comprised of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional layers may be included in close proximity to the gate electrode 104 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

In some embodiments, the gate dielectric 106 may comprise one or more high-k dielectrics. Examples of high-k materials that may be used in gate dielectric 106 may include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tungsten oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum silicon oxide, lead scandium tantalum oxide, lead zinc niobate, aluminum nitride, and silicon nitride. In some embodiments, the gate dielectric 106 may be comprised of a stack of two or more dielectric layers (e.g., a stack of two or more high-k materials listed above). The gate dielectric 106 or the layer of the gate dielectric 106 may comprise a mixture of the materials listed above and/or a mixture of other oxides, nitrides, or oxynitrides.

The gate dielectric 106 may be deposited using a conformal deposition process, such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). Conformal deposition generally refers to the deposition of a coating of some kind on any exposed surface of a given structure. Thus, a conformal coating may be understood as a coating applied to an exposed surface of a given structure, rather than, for example, a coating applied only to a horizontal surface. In some embodiments, an annealing process may be performed on the gate dielectric 106 during fabrication of the transistor 101 to improve the quality of the gate dielectric 106. The gate dielectric 106 may have a thickness, i.e., a dimension measured in the direction of the z-axis of the x-y-z reference frame shown in fig. 1, which may be between 0.5 nanometers and 20 nanometers, including all values and ranges therein (e.g., between 2 and 6 nanometers), in some embodiments.

The channel material 108 may be comprised of a semiconductor material system (and in particular an N-type material system). In some embodiments, the channel material 108 is or includes silicon, such as N-type amorphous silicon or polysilicon, or single crystal silicon.

In some embodiments, the transistor 101 may be a Thin Film Transistor (TFT). TFTs are a special type of field effect transistor that is made by depositing a thin film of active semiconductor material and dielectric layers and metal contacts over a supporting layer, which may be a non-conductive layer. At least a portion of the active semiconductor material forms a channel of the TFT. In some embodiments, the channel material 108 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, the thin film channel material 108 may be deposited at a relatively low temperature, which allows the channel material 108 to be deposited within a thermal budget applied to back-end fabrication to avoid damaging other components, such as, for example, front-end components of a logic device.

An S/D region 110 is formed in the channel material 108. The S/D regions 110 may be generally formed using an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the channel material to form the S/D regions 110. An annealing process typically follows the ion implantation process, which activates the dopants and diffuses them further into the channel material 108. In the latter process, the channel material 108 may be etched first to form recesses at the locations of the S/D regions 110. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S/D regions 110. In some embodiments, the S/D regions 110 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorous.

The S/D contact 112 is coupled to the channel material 108 and, in particular, to the S/D region 110. The first S/D contact 112a is coupled to the first S/D region 110a, and the second S/D contact 112b is coupled to the second S/D region 110b. An insulator material (not shown in fig. 1) may be formed between the S/D contacts 112 and electrically separate the two S/

D contacts

112a and 112 b. The insulator material may be formed as a layer over the transistor 101 and similar transistors, wherein the insulator material layer further electrically separates the transistors from each other. The S/D contacts 112 may be formed in the insulator material by patterning the S/D contacts 112 in the insulator layer and depositing the S/D contact material in the patterned areas.

The S/D contact 112 includes an internal conductive structure surrounded by a blocking region. The barrier region separates the internal conductive structure, which may comprise titanium, from the S/D region 110, which may comprise silicon. The barrier region prevents the formation of titanium silicide which creates a resistivity between the S/D contact 112 and the S/D region 110. As described above, the barrier region may include carbon and a metal, such as a carbon layer and a metal (e.g., nb, ta, al, or Ti) layer. The blocking region is selected to have a relatively low schottky barrier height, for example less than 0.55eV.

The S/D contact 112 may have a thickness between 1 nm and 50 nm (including all values and ranges therein) measured in the z-direction in the reference frame shown in fig. 1. In some embodiments, the S/D contact 112 has a thickness between 30 and 40 nanometers.

Although the transistor 101 depicted in fig. 1 has a back side gate stack and a front side S/D contact, in other embodiments, different transistor architectures may include S/D contacts with the blocking regions described herein. For example, the gate stack may be on the front side, or one or both of the S/D regions and S/D contacts may be on the back side. In other embodiments, the transistor may have a non-planar architecture, such as a FinFET. An example of a FinFET is shown in fig. 9A and 9B. In some embodiments, the transistor is a nanoribbon based transistor (or, simply, a nanoribbon transistor, e.g., a nanowire transistor). In a nanoribbon transistor, a gate stack, which may include a stack of one or more gate electrode metals (e.g., the materials discussed with respect to gate electrode 104) and optionally a stack of one or more gate dielectrics (e.g., one of gate dielectrics 106), may be provided around a portion of an elongated semiconductor structure referred to as a "nanoribbon," such that a gate is formed on all sides of the nanoribbon. The portion of the nanoribbon surrounded by the gate stack is referred to as the "channel" or "channel portion" and may be formed of any of the channel materials 108 described above (and in particular the oxide-metal channel material). S/D regions are provided on opposite ends of the nanoribbon, forming the source and drain of such a transistor, respectively, on either side of the gate stack.

The 1T-1C memory cell shown in fig. 1 is but one exemplary IC device that may include S/D contacts with blocking regions. As another example, a capacitor may not be formed, resulting in a transistor with a contact having a blocking region.

Exemplary S/D contact with silicide formation

Fig. 2 is a perspective view of a cross section of a contact located over a source or drain, and silicide is formed between the contact and the source or drain. Fig. 2 shows one of the S/D regions 110 and a contact 200 formed over the S/D region 110. In this example, the S/D region 110 comprises silicon. The contact 200 includes multiple layers, such as a Ti layer 202, a TiN layer 204, and a core 206. Alternatively, the Ti layer 202 or TiN layer 204 may not be present. Core 206 may be formed from one or more metals or metal alloys of materials such as: copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these materials. In some embodiments, core 206 may include one or more conductive alloys, oxides, or carbides of one or more metals. In some embodiments, core 206 may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant. Metals may provide higher conductivity, while doped semiconductors may be more easily patterned during fabrication.

In this example, the Ti layer 202 is formed directly over the S/D region 110. The titanium reacts with the silicon in the S/D regions 110 to form an interfacial layer 208 of titanium silicide. As described above, tiSi ₂ Having a schottky barrier height of about 0.55 eV. If other materials are used instead of Ti layer 202, a different metal silicide may be formed.

Exemplary S/D contact with Barrier region

Fig. 3 is a perspective view of a cross section of a contact over a source or drain, where the contact has a blocking region, according to some embodiments of the present disclosure. Fig. 3 illustrates one of the S/D regions 110, wherein a contact 300 is formed over the S/D region 110. The S/D region 110 may include silicon. The contact 300 includes a blocking region 302 and an internal conductive structure. In this example, the inner conductive structure includes a Ti layer 202, a TiN layer 204, and a core 206. In other embodiments, the internal conductive structures may include more, fewer, or different layers, and may include different materials. For example, the Ti layer 202 or TiN layer 204 may not be present. Core 206 may be formed from any of the materials described with respect to fig. 2.

The blocking region 302 has a lower resistivity and a lower schottky barrier height than the silicide region 208 shown in fig. 2. The barrier region 302 may include carbon in combination with one or more other metals (e.g., nb, ta, al, or Ti). The barrier region 302 may include multiple layers, for example, one or more carbon layers, and one or more metal layers.

The blocking region 302 is coupled between the S/D region 110 and the internal conductive structure. The barrier region 302 may have a thickness between 0.25 nanometers and 2.5 nanometers. In the example shown in fig. 3, the barrier region 302 reaches the same height as each of the

layers

202, 204, and 206 of the internal conductive structure. For example, the barrier region 302 and the

layers

202 and 204 may be formed using a conformal deposition method such as ALD or CVD to deposit the barrier region 302 and the

layers

202 and 204 in openings formed in an insulating material (e.g., ILD) (not shown in fig. 3). If the barrier region 302 includes multiple layers (e.g., one or more carbon layers and one or more metal layers), each individual layer may extend across the base of the contact 300 and extend up the height of the contact 300. Exemplary layers for forming the blocking region 302 are shown in fig. 4-8. In particular, each of fig. 4-8 illustrates an exemplary structure of the region 304 within the dashed box.

In some embodiments, barrier region 302 (or one or more individual layers of barrier region 302) and/or

layers

202 and 204 may not extend the entire height of contact 300 upward. For example, the barrier region 302 may be formed over the S/D region 110, and the internal conductive structures (e.g., ti layer 202, tiN layer 204, and core 206) are formed over the top of the barrier region 302. In this example, the barrier region 302 may be deposited using a non-conformal deposition method (e.g., sputtering). For example, as shown in fig. 3, if a non-conformal deposition method is used to deposit the blocking region 302, some of the material forming the blocking region 302 may be formed along the sides of the contact 300.

Although fig. 3 shows one contact 300 over one S/D region 110, similar contacts 300 may be formed over both S/D regions 110 of the transistor, e.g., both S/D contacts 112a and S/D contacts 112b may have the structure of contact 300 shown in fig. 3.

Exemplary layered Barrier regions

Fig. 4-8 illustrate various layer structures of the blocking region 302. The layered structure shows details of the blocking area 302 within the area 304 shown in fig. 3.

Fig. 4 is a cross-sectional view of a carbon-metal barrier region according to some embodiments of the present disclosure. The barrier region 302 includes a carbon layer 402 and a metal layer 404. The S/D region 110 is below the carbon layer 402 and the titanium layer 202 (or, more generally, the internal conductive structure) is above the metal layer 404.

Carbon layer 402 may include graphite-like carbon, diamond-like carbon, or a mixture of graphite-like carbon and diamond-like carbon. Graphite-like carbon is a crystalline form of carbon having atoms arranged in a hexagonal structure. The graphite-like carbon may include a layer of two-dimensional sheets formed from carbon atoms; the single-layer sheet is called graphene. Graphite-like carbon is a good conductor of heat and electricity, making it suitable for use as an S/D contact. Diamond-like carbon is a class of carbon that may have one of seven structures, including cubic or hexagonal. Diamond-like carbon typically includes a large number of sp ³ And (3) hybridizing carbon atoms. Different forms of diamond-like carbon have different levels of electrical conductivity, with some forms acting as semiconductors and others acting as insulators.

The carbon layer 402 may include pure or nearly pure graphite-like carbon or diamond-like carbon. In other embodiments, carbon layer 402 may include a mixture of graphite-like carbon and diamond-like carbon, for example, at any ratio ranging from a 1:20 ratio of graphite-like carbon to diamond-like carbon to a 20:1 ratio of graphite-like carbon to diamond-like carbon. The carbon layer 402 may be deposited using a non-conformal deposition method, such as Physical Vapor Deposition (PVD) magnetron sputtering. Different parameters of the PVD magnetron sputtering process (e.g., temperature, bias, power, and throw distance) may be adjusted to achieve diamond-like carbon, graphite-like carbon, or a desired ratio of diamond-like carbon to graphite-like carbon.

The carbon layer 402 may have a thickness of between, for example, 0.125 nanometers and 2 nanometers. In some embodiments, metal layer 404 is omitted and titanium layer 202 is a metal layer over carbon layer 402. In such an embodiment, the carbon layer 402 may have a thickness of up to 2.5 nanometers.

As described above, the metal layer 404 may include Nb, ta, or Al. In some embodiments, the metal layer 404 may include a plurality of metals. In some embodiments, the metal layer 404 is composed of multiple metal layers (e.g., nb and Ta layers). The metal layer 404 may be formed using a conformal or non-conformal deposition method. The metal layer 404 may have a thickness of, for example, between 0.125 and 2 nanometers. As described above, the total thickness of the carbon layer 402 and the metal layer 404 (i.e., the total thickness of the barrier region 302) may be between 0.25 and 2.5 nanometers.

Fig. 5 is a cross-sectional view of a carbon-metal barrier with a metal carbide layer according to some embodiments of the present disclosure. In this example, the metal in metal layer 404 has reacted with the carbon in carbon layer 402, which forms metal carbide layer 502 between carbon layer 402 and metal layer 404. For example, if the metal layer 404 includes Nb, the metal carbide layer 502 includes niobium carbide. If metal layer 404 is titanium (e.g., if titanium layer 202 is a metal layer directly over carbon layer 402), then metal carbide layer 502 comprises titanium carbide. The metal carbide formed by metal layer 404 and carbon layer 402 is typically conductive and does not increase the resistivity of barrier region 302.

As shown in fig. 5, depending on the thickness of carbon layer 402 and metal layer 404, portions of carbon layer 402 and/or portions of metal layer 404 may remain. The metal carbide layer 502 may have a thickness between 0 nanometers (if no metal carbide is formed) and 2.5 nanometers (e.g., if the total height of the barrier region 302 is 2.5 nanometers and all of the carbon layer 402 and all of the metal layer 404 are reacted), or any thickness therebetween.

Fig. 6 is a cross-sectional view of a carbon-metal-carbon blocking region according to some embodiments of the present disclosure. The barrier region 302 includes a first carbon layer 602, a metal layer 404, and a second carbon layer 604. The first carbon layer 602 is between the S/D region 110 and the metal layer 404, the metal layer 404 is between the two

carbon layers

602 and 604, and the second carbon layer 604 is between the metal layer 404 and the titanium layer 202 (or, more generally, the inner conductive structure). As described above, the metal layer 404 may include Nb, ta, al, or Ti. In some embodiments, the metal layer 404 may include a plurality of metals. In some embodiments, the metal layer 404 is composed of multiple metal layers (e.g., nb and Ta layers).

The first carbon layer 602 may have a thickness of, for example, between 0.1 nanometers and 1 nanometer. The metal layer 404 may have a thickness of, for example, between 0.1 nanometers and 1.5 nanometers. The second carbon layer 602 may have a thickness of, for example, between 0.1 nanometers and 1 nanometer. The total thickness of the carbon layers 602 and 604 and the metal layer 404 (i.e., the total thickness of the barrier region 302) may be between 0.25 and 2.5 nanometers.

As described in connection with the carbon-metal barrier region and with respect to fig. 5, metal layer 404 may react with one or both of

carbon layers

602 and 604 to form a metal carbide layer. Fig. 7 is a cross-sectional view of a carbon-metal-carbon barrier with two metal carbide layers according to some embodiments of the present disclosure. The first metal carbide layer 702 is between the first carbon layer 602 and the metal layer 404, and the second metal carbide layer 704 is between the metal layer 404 and the second carbon layer 604. The first metal carbide layer 702 may have a thickness between 0 nanometers (if no metal carbide is formed) and 1.25 nanometers (e.g., if the total height of the barrier region 302 is 2.5 nanometers and all of the carbon layer 602 and all of the lower portion of the metal layer 404 are reacted), or any thickness therebetween. The second metal carbide layer 704 may have a thickness between 0 nanometers (if no metal carbide is formed) and 1.25 nanometers (e.g., if the total height of the barrier region 302 is 2.5 nanometers and all of the carbon layer 604 and all of the upper portion of the metal layer 404 are reacted).

In some cases, the second carbon layer 604 may also react with internal conductive structures formed over the second carbon layer 604. For example, if the bottom layer of the inner conductive structure comprises titanium, the titanium may react with carbon in the second carbon layer 604 to form titanium carbide. Fig. 8 is a cross-sectional view of a carbon-metal-carbon barrier with three metal carbide layers according to some embodiments of the present disclosure. In this example, a titanium carbide layer 802 is formed between the second carbon layer 604 and the titanium layer 202. The titanium carbide layer 802 may have a thickness between, for example, 0.125 nanometers and 1.25 nanometers.

FinFET arrangement with S/D contact having blocking region

As described above, although transistor 101 depicted in fig. 1 has a back side gate stack and a front side S/D contact, in other embodiments, different transistor architectures may include S/D contacts with blocking regions as described herein. For example, in some embodiments, contacts with blocking regions are used in transistors (e.g., finfets) with non-planar architectures.

Fig. 9A-9B are perspective and cross-sectional views, respectively, of an exemplary transistor implemented as a FinFET having contacts with metal and carbon blocking regions, in accordance with some embodiments of the present disclosure. FinFET refers to a transistor having a non-planar architecture in which a fin formed of one or more semiconductor materials extends away from a base (where the term "base" refers to any suitable support structure, such as a substrate, upon which the transistor may be built). A portion of the fin closest to the base may be surrounded by insulator material. Such insulator materials (typically oxides) are commonly referred to as "shallow trench isolation" (STI), and the portion of the fin surrounded by the STI is typically referred to as a "sub-fin portion" or simply "sub-fin". A gate stack comprising at least a layer of gate electrode material and (optionally) a gate dielectric layer may be provided over the top and sides of the remaining upper portion of the fin (i.e., the portion above and not surrounded by the STI), thus surrounding the uppermost portion of the fin. The portion of the fin surrounded by the gate stack is typically referred to as the "channel portion" of the fin, as this is where a conductive channel is formed during transistor operation and is part of the active region of the fin. Two S/D regions are provided on opposite sides of the gate stack, forming source and drain terminals of the transistor. A FinFET may be implemented as a "tri-gate transistor," where the name "tri-gate" stems from the fact that, in use, such a transistor may form a conductive channel on three "sides" of a fin. Finfets have the potential to improve performance over single gate transistors and double gate transistors.

Fig. 9A is a perspective view and fig. 9B is a cross-sectional side view of a FinFET 900 with metal and carbon blocking regions in the S/D contact. Fig. 9A-9B illustrate a support structure 102, a gate electrode 104, a gate dielectric 106, a channel material 108, and an S/D region 110 as described with respect to fig. 1. The two S/D regions are labeled 910a and 910b in FIG. 9A. As shown in fig. 9A-9B, when the transistor 900 is implemented as a FinFET, the FinFET 900 may also include a fin 922, and STI material 920 surrounding a sub-fin portion of the fin 922. Two S/D contacts 912a and 912B are further shown in fig. 9A-9B.

Contacts

912a and 912b may incorporate any of the barrier regions 302 described with respect to fig. 3-8. The cross-sectional side view of fig. 9B is a view in the y-z plane of the exemplary coordinate system x-y-z shown in fig. 9A, where the cross-section of fig. 9B is taken across fin 922 (e.g., along the plane shown as plane AA' in fig. 9A).

As shown in fig. 9A-9B, the fins 922 may extend away from the support structure 102 and may be substantially perpendicular to the support structure 102. Fin 904 may include one or more semiconductor materials, such as a stack of semiconductor materials, such that an uppermost portion of the fin (i.e., a portion of fin 922 surrounded by gate electrode 104 and gate dielectric 106) may serve as a channel region of FinFET 900. Thus, the uppermost portion of fin 922 may be formed from channel material 108 as described above.

The sub-fins of fin 922 may be binary, ternary, or quaternary III-V compound semiconductors that are alloys of two, three, or even four elements from groups III and V of the periodic table of elements (including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth). For some exemplary N-type transistor embodiments, the sub-fin portion of fin 922 may be a III-V material having an energy band offset (e.g., a conduction band offset for an N-type device) with respect to the channel portion. Exemplary materials include, but are not limited to GaAs, gaSb, gaAsSb, gaP, inAlAs, gaAsSb, alAs, alP, alSb and AlGaAs. In some N-type transistor embodiments of FinFET 900 in which the channel portion of fin 922 (e.g., the channel portion) is InGaAs, the sub-fin may be GaAs, and at least a portion of the sub-fin may also be doped with impurities (e.g., P-type) to a higher impurity level than the channel portion. In alternative heterojunction embodiments, both the sub-fins and the channel portion of fin 922 are or include group IV semiconductors (e.g., si, ge, siGe). The sub-fins of fin 922 may be a first element semiconductor (e.g., si or Ge) or a first SiGe alloy (e.g., having a wide bandgap).

As further shown in fig. 9A-9B, STI material 920 may surround portions of sides of fin 922. A portion of fin 922 surrounded by STI 920 forms a sub-fin. In various embodiments, STI material 920 may be a low-k or high-k dielectric including, but not limited to, elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Other examples of dielectric materials that may be used in STI material 920 may include, but are not limited to: silicon nitride, silicon oxide, silicon dioxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

As shown in fig. 9A-9B, the gate stack (i.e., gate dielectric 106 and gate electrode 104) may surround an upper portion of fin 922 (a portion above STI 920), with a channel portion of fin 922 corresponding to the portion of fin 922 surrounded by the gate stack, as shown in fig. 9A-9B. In particular, gate dielectric 106 (if used) may surround an uppermost portion of fin 922, and gate electrode 104 may surround gate dielectric 106. The interface between the channel portion and the sub-fin portion of fin 922 is located adjacent to where gate electrode 104 terminates.

In some embodiments, finFET 900 may have a gate length GL (i.e., the distance between first S/D region 910a and second S/D region 910B), i.e., the dimension measured along fin 922 in the direction of the x-axis of the exemplary reference coordinate system x-y-z shown in fig. 9A-9B, which may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers), in some embodiments. The fin 922 may have a thickness, i.e., a dimension measured in the y-axis direction of the reference coordinate system x-y-z shown in fig. 9A-9B, which may be between about 5 and 30 nanometers, including all values and ranges therein (e.g., between about 7 and 20 nanometers, or between about 10 and 15 nanometers), in some embodiments. The fins 922 may have a height, i.e., a dimension measured in the z-axis direction of the reference coordinate system x-y-z shown in fig. 9A-9B, which may be between about 30 and 350 nanometers, including all values and ranges therein (e.g., between about 30 and 200 nanometers, between about 75 and 250 nanometers, or between about 150 and 300 nanometers), in some embodiments.

Although the fins 922 shown in fig. 9A-9B are shown as having rectangular cross-sections in the y-z plane of the reference frame shown, the fins 922 may alternatively have rounded or sloped cross-sections at the "top" of the fins 922, and the gate stack may conform to the rounded or sloped fins 922. In use, finFET 900 may form a conductive channel on three "sides" of the channel portion of fin 922, potentially improving performance relative to single gate transistors (which may form a conductive channel on one "side" of the channel material or substrate) and double gate transistors (which may form a conductive channel on both "sides" of the channel material or substrate).

S/

D contacts

912a and 912b are electrically connected to S/

D regions

910a and 910b and extend in the same vertical direction relative to fin 922. In another example, one of the S/D contacts (e.g., the first S/D contact 912 a) may be electrically connected to the first S/D region 910a and extend from the first S/D region 910a toward the support structure 102, forming a backside S/D contact for the FinFET 900. In yet another embodiment, both the first S/D contact 912a and the second S/D contact 912b extend from the first S/D region 910a and the second S/D region 910b toward the support structure, forming two backside S/D contacts for the FinFET 900.

Exemplary methods for Forming S/D contacts with Barrier regions

Fig. 10 is a flowchart illustrating a method for forming source and drain contacts with metal and carbon blocking regions, according to some embodiments of the present disclosure. The method begins by depositing 1002 a carbon barrier layer, such as carbon layer 402 shown in fig. 4, or first carbon layer 602 shown in fig. 6. A carbon layer 402 is deposited over the S/D regions (e.g., S/D region 110).

The method continues with depositing 1004 a metal barrier layer, such as the metal layer 404 shown in fig. 4, or the metal layer 404 shown in fig. 6. In some embodiments, multiple metal layers (e.g., a niobium layer followed by an aluminum layer) are deposited. As shown in fig. 5, 7 and 8, the metal in the metal barrier layer may react with the carbon in the carbon layer to form metal carbides.

In some embodiments, the method continues with depositing (1006) a second carbon barrier layer, such as the second carbon layer 604 shown in fig. 6. As shown in fig. 7 and 8, the carbon in the second carbon barrier layer may react with the metal in the metal barrier layer to form a metal carbide. In other embodiments, the second carbon barrier layer is not deposited (e.g., as shown in fig. 4 and 5). The carbon barrier layer, the metal barrier layer and the optional second carbon barrier layer form a barrier region.

The method continues with depositing 1008 a Ti and/or TiN layer over the barrier region. For example, as shown in fig. 3, a Ti layer is deposited, followed by a TiN layer. If a second carbon barrier layer is deposited, ti may react with carbon in the second carbon barrier layer to form titanium carbide, as shown in FIG. 8. In alternative embodiments, a different conductive material is used instead of Ti and/or TiN.

The method continues with depositing 1010 a core material over the Ti/TiN layer. Fig. 3 shows a core 206. The core material fills the interior of the S/D contact.

Exemplary apparatus

The interconnect with barrier material liner disclosed herein may be included in any suitable electronic device. Fig. 11-14 illustrate various examples of devices that may include contacts with carbon and metal barrier regions as disclosed herein.

Fig. 11A and 11B are top views of a wafer and die including one or more IC structures having one or more contacts with carbon and metal barrier regions, according to any embodiment disclosed herein. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product that includes any suitable IC structure (e.g., an IC structure as shown in any of fig. 1-9, or any further embodiment of an IC structure described herein). After fabrication of the semiconductor product is completed (e.g., after fabrication of one or more IC structures having one or more contacts with carbon and metal barrier regions as described herein, the contacts being included in a particular electronic component, e.g., in a transistor or in a memory device), wafer 1500 may undergo a singulation process in which each die 1502 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, a device including one or more IC structures with contacts having carbon and metal barrier regions as disclosed herein may take the form of wafer 1500 (e.g., not singulated) or die 1502 (e.g., singulated). Die 1502 may include one or more transistors (e.g., one or more of transistors 1640 of fig. 12 discussed below) and/or support circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more IC structures with contacts having carbon and metal barrier regions). In some embodiments, wafer 1500 or die 1502 may include a memory device (e.g., an SRAM device), a logic device (e.g., AND, OR, NAND or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed from a plurality of memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of fig. 14) or other logic configured to store information in the memory device or execute instructions stored in the memory array.

Fig. 12 is a cross-sectional side view of an IC device 1600 that may include one or more IC structures having one or more contacts with carbon and metal barrier regions, in accordance with any embodiment disclosed herein. IC device 1600 may be formed on substrate 1602 (e.g., wafer 1500 of fig. 11A) and may be included in a die (e.g., die 1502 of fig. 11B). Substrate 1602 may be any substrate described herein. Substrate 1602 may be part of an singulated die (e.g., die 1502 of fig. 11B) or a wafer (e.g., wafer 1500 of fig. 11A).

IC device 1600 may include one or more device layers 1604 disposed on substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 for controlling the flow of current between the S/D regions 1620 in a transistor 1640, and one or more S/D contacts 1624 for routing electrical signals to/from the S/D regions 1620. The transistor 1640 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. The transistor 1640 is not limited to the type and configuration depicted in fig. 12, and may include a wide variety of other types and configurations such as planar transistors, non-planar transistors, or a combination of both. The non-planar transistors may include FinFET transistors (e.g., double gate transistors or tri-gate transistors) and wrap-gate or fully-wrap-gate transistors (e.g., nanoribbon and nanowire transistors).

Each transistor 1640 may include a gate 1622 formed of at least two layers (a gate electrode layer and a gate dielectric layer).

The gate electrode layer may be formed on the gate interconnect support layer and may be composed of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers may be included for other purposes, such as barrier layers and/or adhesion layers.

For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of PMOS gate electrodes having a work function between about 4.9 electron volts (eV) and about 5.2 eV. For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tungsten carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9eV and about 4.2 eV.

In some embodiments, the gate electrode may be formed as a U-shaped structure when viewed from a cross-section of the transistor 1640 in the source-channel-drain direction, the U-shaped structure including a bottom substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers. In some embodiments, the gate electrode may be comprised of a V-shaped structure (e.g., when the fin of a FinFET transistor does not have a "flat" upper surface, but rather has a rounded top end).

In general, the gate dielectric layer of transistor 1640 may include one layer or a stack of layers, and one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor 1640 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric layer to improve its quality.

IC device 1600 may include one or more contacts with carbon and metal barrier regions at any suitable location in IC device 1600. For example, S/D contact 1624 may include a blocking region as described herein, e.g., in a region of S/D contact 1624 adjacent S/D region 1620.

S/D regions 1620 may be formed within substrate 1602 adjacent to gate 1622 of each transistor 1640 using any suitable process known in the art. For example, the S/D regions 1620 may be formed using an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into substrate 1602 to form S/D regions 1620. An annealing process that activates the dopants and diffuses them farther into substrate 1602 may be followed by an ion implantation process. In the latter process, an epitaxial deposition process may provide the material used to fabricate S/D regions 1620. In some embodiments, S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorous. In some embodiments, one or more alternative semiconductor materials (such as germanium or a group III-V material or alloy) may be used to form S/D regions 1620. In further embodiments, one or more layers of metal and/or metal alloy may be used to form S/D regions 1620. In some embodiments, an etching process may be performed prior to epitaxial deposition to create a recess in substrate 1602 in which to deposit material for S/D regions 1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to transistors 1640 of device layer 1604 and/or from transistors 1640 of device layer 1604 through one or more interconnect layers (shown as interconnect layers 1606-1610 in fig. 12) disposed on device layer 1604. For example, conductive features of device layer 1604 (e.g., gate 1622 and S/D contacts 1624) may be electrically coupled with interconnect structures 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 may form ILD stack 1619 of IC device 1600.

Interconnect structure 1628 may be disposed within interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structure 1628 depicted in fig. 12). Although a particular number of interconnect layers 1606-1610 are depicted in fig. 12, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structure 1628 may include trench contact structures 1628a (sometimes referred to as "lines") and/or via structures 1628b (sometimes referred to as "holes") filled with a conductive material (e.g., metal). Trench contact structure 1628a may be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of substrate 1602 on which device layer 1604 is formed. For example, the trench contact structure 1628a may route electrical signals in a direction into and out of the page from the perspective of fig. 12. The via structure 1628b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, via structures 1628b may electrically couple trench contact structures 1628a of different interconnect layers 1606-1610 together.

As shown in fig. 12, interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628. Dielectric material 1626 may take the form of any embodiment of a dielectric material provided between interconnects of the IC structures disclosed herein.

In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions. In other embodiments, the composition of dielectric material 1626 may be the same between different interconnect layers 1606-1610.

First interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly on device layer 1604. In some embodiments, as shown, first interconnect layer 1606 may include trench contact structures 1628a and/or via structures 1628b. Trench contact structure 1628a of first interconnect layer 1606 may be coupled with a contact (e.g., S/D contact 1624) of device layer 1604.

The second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via structure 1628b to couple the trench contact structure 1628a of the second interconnect layer 1608 with the trench contact structure 1628a of the first interconnect layer 1606. Although the trench contact structures 1628a and via structures 1628b are structurally depicted with lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments the trench contact structures 1628a and via structures 1628b may be structurally and/or materially continuous (e.g., filled simultaneously during a dual damascene process).

Third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, as desired) may be formed successively on second interconnect layer 1608 according to similar techniques and configurations described in connection with second interconnect layer 1608 or first interconnect layer 1606.

IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more bond pads 1636 formed on interconnect layers 1606-1610. The bond pad 1636 may be electrically coupled with the interconnect structure 1628 and configured to route electrical signals to the transistor(s) 1640 of other external devices. For example, solder bonds may be formed on one or more bond pads 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). IC device 1600 may have other alternative configurations than those depicted in other embodiments to route electrical signals from interconnect layers 1606-1610. For example, bond pad 1636 may be replaced with or may also include other similar features (e.g., posts) that route electrical signals to external components.

Fig. 13 is a cross-sectional side view of an IC device assembly 1700 that may include components having or associated with (e.g., electrically connected by) one or more IC structures with contacts having carbon and metal barrier regions, according to any embodiment disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposite second side 1742 of the circuit board 1702; in general, the components may be disposed on one or both of the

faces

1740 and 1742. In particular, any suitable of the components of the IC device assembly 1700 may include any of the contacts disclosed herein having carbon and metal barrier regions.

In some embodiments, the circuit board 1702 may be a Printed Circuit Board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally in combination with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate.

The IC device assembly 1700 shown in fig. 13 includes an interposer-on package structure 1736 coupled to a first face 1740 of the circuit board 1702 by a coupling member 1716. The coupling component 1716 may electrically and mechanically couple the package on interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in fig. 13), male and female portions of a socket, adhesive, underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1736 may include an IC package 1720 coupled to the interposer 1704 through a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1716. Although fig. 13 shows a single IC package 1720, multiple IC packages may be coupled to interposer 1704; in practice, additional interpolators may be coupled to interpolators 1704. The interposer 1704 may provide an intervening substrate for bridging the circuit board 1702 and the IC package 1720. IC package 1720 may be or include, for example, a die (die 1502 of fig. 11B), an IC device (e.g., IC device 1600 of fig. 12), or any other suitable component. In some embodiments, IC package 1720 may include contacts with carbon and metal barrier regions as described herein. In general, the interposer 1704 may spread the connection to a wider pitch or reroute the connection to a different connection. For example, the interposer 1704 may couple the IC package 1720 (e.g., die) to a Ball Grid Array (BGA) of the coupling component 1716 to couple to the circuit board 1702. In the embodiment shown in fig. 13, an IC package 1720 and a circuit board 1702 are attached to opposite sides of an interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the interposer 1704. In some embodiments, three or more components may be interconnected by an interposer 1704.

The interposer 1704 may be formed of an epoxy, a glass fiber reinforced epoxy, a ceramic material, or a polymeric material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials as described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include a metal interconnect 1708 and a via 1710 including, but not limited to, a TSV 1706. The interposer 1704 may also include an embedded device 1714, including both passive and active devices. Such means may include, but are not limited to: capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, converters, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be formed on interposer 1704. The interposer 1704 may also include contacts with carbon and metal barrier regions as described herein. The package-on-interposer 1736 may take the form of any package-on-interposer known in the art.

The IC device assembly 1700 may include an IC package 1724 coupled to a first side 1740 of the circuit board 1702 by a coupling member 1722. Coupling component 1722 may take the form of any embodiment discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

The IC device assembly 1700 shown in fig. 13 includes an on-package structure 1734 coupled to the second side 1742 of the circuit board 1702 by a coupling member 1728. The on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732.

Coupling components

1728 and 1730 may take the form of any of the embodiments of coupling component 1716 discussed above, and

IC packages

1726 and 1732 may take the form of any of the embodiments of IC package 1720 discussed above. The on-package structure 1734 may be constructed according to any on-package structure known in the art.

Fig. 14 is a block diagram of an exemplary computing device 1800 that may include one or more components including one or more IC structures having one or more contacts with carbon and metal barrier regions, according to any embodiment disclosed herein. For example, any suitable of the components of computing device 1800 may include a die (e.g., die 1502 of fig. 11B) having contacts with carbon and metal barrier regions as described herein. Any one or more components of computing device 1800 may include IC device 1600, or be included in IC device 1600 (fig. 12). Any one or more components of the computing device 1800 may include the IC device assembly 1700, or be included in the IC device assembly 1700 (fig. 13).

A number of components included in the computing device 1800 are shown in fig. 14, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die.

Further, in various embodiments, computing device 1800 may not include one or more of the components shown in fig. 14, but computing device 1800 may include interface circuitry for coupling to one or more components. For example, the computing device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the computing device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

The computing device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to convert the electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more Digital Signal Processors (DSPs), application Specific ICs (ASICs), central Processing Units (CPUs), graphics Processing Units (GPUs), cryptographic processors (special purpose processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 1800 may include memory 1804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic Random Access Memory (DRAM)), non-volatile memory (e.g., read Only Memory (ROM)), flash memory, solid state memory, and/or a hard disk drive. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the computing device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications to transmit data to and from the computing device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

The communication chip 1812 may implement any of a variety of wireless standards or protocols including, but not limited to, institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE802.16 standards (e.g., IEEE802.16-2005 amendment), long Term Evolution (LTE) project, and any amendments, updates, and/or revisions (e.g., LTE-advanced project, ultra Mobile Broadband (UMB) project (also referred to as "3GPP 2"), etc.). IEEE802.16 compliant Broadband Wireless Access (BWA) networks, commonly referred to as WiMAX networks, are acronyms that represent worldwide interoperability for microwave access, and are authentication flags for products that pass compliance and interoperability tests for the IEEE802.16 standard. The communication chip 1812 may operate according to global system for mobile communications (GSM), general Packet Radio Service (GPRS), universal Mobile Telecommunications System (UMTS), high Speed Packet Access (HSPA), evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), digital Enhanced Cordless Telecommunications (DECT), evolution data optimized (EV-DO) and derivatives thereof, as well as any other wireless protocol designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 1812 may operate in accordance with other wireless protocols. The computing device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (e.g., AM or FM radio transmissions).

In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., ethernet). As described above, the communication chip 1812 may include a plurality of communication chips. For example, the first communication chip 1812 may be dedicated to shorter range wireless communications, such as Wi-Fi or bluetooth, and the second communication chip 1812 may be dedicated to longer range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, wiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communication and the second communication chip 1812 may be dedicated to wired communication.

The computing device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 1800 to an energy source (e.g., AC line power) separate from the computing device 1800.

The computing device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a Liquid Crystal Display (LCD), a light emitting diode display, or a flat panel display.

The computing device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). For example, the audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or an ear bud.

The computing device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument having a Musical Instrument Digital Interface (MIDI) output).

The computing device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above), as is known in the art, the GPS device 1818 may communicate with a satellite-based system and may receive the location of the computing device 1800.

The computing device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

The computing device 1800 may include other input devices 1820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touch pad), a bar code reader, a Quick Response (QR) code reader, any sensor, or a Radio Frequency Identification (RFID) reader.

The computing device 1800 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, smart phone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultra-book computer, personal Digital Assistant (PDA), ultra-portable personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, computing device 1800 may be any other electronic device that processes data.

Selective examples

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides an IC apparatus comprising: a transistor having a gate, a channel, and an S/D region; and an S/D contact coupled to the S/D region, the S/D contact including an internal conductive structure and a barrier region including carbon and metal, the barrier region being coupled between the S/D region and the internal conductive structure.

Example 2 provides the IC device of example 1, wherein the barrier region includes a first layer comprising carbon and a second layer comprising metal.

Example 3 provides the IC device of example 2, wherein the metal is niobium.

Example 4 provides the IC device of example 2, wherein the metal is tantalum.

Example 5 provides the IC device of example 2, wherein the metal is aluminum.

Example 6 provides the IC device of any of examples 2-5, wherein the first layer has a thickness between 0.1 and 2 nanometers.

Example 7 provides the IC device of any one of examples 2-6, wherein the second layer has a thickness between 0.1 and 2 nanometers.

Example 8 provides the IC device of any of examples 2-7, wherein the barrier region includes a third layer between the first layer and the second layer, the third layer including a metal carbide.

Example 9 provides the IC device of any of examples 2-7, wherein the barrier region further comprises a third layer comprising carbon, the second layer being located between the first layer and the third layer.

Example 10 provides the IC apparatus of example 9, wherein the blocking region further comprises: a fourth layer comprising a metal carbide, the fourth layer being located between the first layer and the third layer; and a fifth layer comprising a metal carbide, the fifth layer being located between the third layer and the second layer.

Example 11 provides the IC device of example 2, wherein the blocking region further includes a third layer between the first layer and the second layer, the third layer including a second metal different from the metal in the second layer.

Example 12 provides the IC device of any one of examples 1-11, wherein the S/D region comprises silicon.

Example 13 provides the IC apparatus of any one of examples 1-12, further comprising: a second S/D region; and a second S/D contact coupled to the second S/D region, the second S/D contact including an internal conductive structure and a blocking region.

Example 14 provides a contact for an IC device, the contact comprising: an internal conductive structure; a first barrier layer comprising carbon; and a second barrier layer between the inner conductive structure and the first barrier layer, the second barrier layer comprising a metal, wherein the metal is one of niobium, aluminum, and tantalum.

Example 15 provides the contact of example 14, wherein the first barrier layer is located between the second barrier layer and an S/D region, the S/D region comprising silicon.

Example 16 provides the contact of example 14 or 15, further comprising a metal carbide between the first barrier layer and the second barrier layer.

Example 17 provides the contact of any of examples 14-16, further comprising a third barrier layer comprising carbon, the third barrier layer being located between the inner conductive structure and the second barrier layer.

Example 18 provides the contact of example 17, further comprising a metal carbide between the second barrier layer and the third barrier layer.

Example 19 provides the contact of any of examples 14-18, wherein the internal conductive structure comprises titanium.

Example 20 provides a method for fabricating a contact having a blocking region, comprising: forming a blocking region over the S/D region of the transistor, the blocking region comprising carbon and a metal; and forming an internal conductive structure within the barrier region and over the S/D region, the barrier region physically separating the internal conductive structure from the S/D region.

Example 21 provides the method of example 20, wherein forming the barrier region includes depositing a first barrier layer comprising carbon and depositing a second barrier layer comprising metal.

Example 22 provides the method of example 21, wherein the first barrier layer and the second barrier layer are both deposited using a conformal deposition method.

Example 23 provides the method of any one of examples 20-22, wherein the metal is one of niobium, tantalum, aluminum, and titanium.

Example 24 provides the method of any one of examples 20-23, wherein the S/D region comprises silicon.

Example 25 provides the method of any one of examples 20-24, wherein forming the internal conductive structure comprises depositing a titanium layer and depositing a core material over the titanium layer.

The above description of illustrated embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications can be made to the disclosure in light of the above detailed description.

Claims

1. An Integrated Circuit (IC) device, comprising:

a transistor including a gate, a channel, and source/drain (S/D) regions; and

an S/D contact coupled to the S/D region, the S/D contact comprising:

an internal conductive structure; and

a barrier region comprising carbon and metal, the barrier region being coupled between the S/D region and the internal conductive structure.

2. The IC device of claim 1, wherein the barrier region comprises a first layer comprising carbon and a second layer comprising the metal.

3. The IC device of claim 2, wherein the metal comprises niobium.

4. The IC device of claim 2, wherein the metal comprises tantalum.

5. The IC device of claim 2, wherein the metal comprises aluminum.

6. The IC device of any of claims 2-5, wherein the first layer has a thickness between 0.1 and 2 nanometers.

7. The IC device of any of claims 2-5, wherein the second layer has a thickness between 0.1 and 2 nanometers.

8. The IC device of any of claims 2-5, wherein the blocking region comprises a third layer between the first layer and the second layer, the third layer comprising a metal carbide.

9. The IC device of any of claims 2-5, wherein the blocking region further comprises a third layer comprising carbon, the second layer being located between the first layer and the third layer.

10. The IC device of claim 9, wherein the blocking region further comprises:

A fourth layer comprising a metal carbide, the fourth layer being located between the first layer and the third layer; and

a fifth layer comprising a metal carbide, the fifth layer being located between the third layer and the second layer.

11. The IC device of claim 2, wherein the blocking region further comprises a third layer between the first layer and the second layer, the third layer comprising a second metal different from the metal in the second layer.

12. The IC device of claim 1, wherein the S/D region comprises silicon.

13. The IC device of claim 1, further comprising:

a second S/D region; and

a second S/D contact coupled to the second S/D region, the second S/D contact including an internal conductive structure and a blocking region.

14. A contact for an Integrated Circuit (IC) device, the contact comprising:

an internal conductive structure;

a first barrier layer comprising carbon; and

a second barrier layer between the inner conductive structure and the first barrier layer, the second barrier layer comprising a metal, wherein the metal is one of niobium, aluminum, and tantalum.

15. The contact of claim 14, wherein the first barrier layer is located between the second barrier layer and a source/drain (S/D) region, the S/D region comprising silicon.

16. The contact of any of claims 14-15, further comprising a metal carbide between the first barrier layer and the second barrier layer.

17. The contact of any of claims 14-15, further comprising a third barrier layer comprising carbon, the third barrier layer being located between the inner conductive structure and the second barrier layer.

18. The contact of claim 17, further comprising a metal carbide between the second barrier layer and the third barrier layer.

19. A method for fabricating a contact having a blocking region, comprising:

forming a blocking region over a source or drain (S/D) region of a transistor, the blocking region comprising carbon and a metal; and

an internal conductive structure is formed within the blocking region and over the S/D region, the blocking region physically separating the internal conductive structure from the S/D region.

20. The method of claim 19, wherein forming the barrier region comprises depositing a first barrier layer comprising carbon and depositing a second barrier layer comprising the metal.