CN116259544B - Manufacturing method of shielded gate trench type power metal oxide semiconductor - Google Patents
Manufacturing method of shielded gate trench type power metal oxide semiconductor Download PDFInfo
- Publication number
- CN116259544B CN116259544B CN202310540946.6A CN202310540946A CN116259544B CN 116259544 B CN116259544 B CN 116259544B CN 202310540946 A CN202310540946 A CN 202310540946A CN 116259544 B CN116259544 B CN 116259544B
- Authority
- CN
- China
- Prior art keywords
- layer
- doped silicon
- carbon
- depositing
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 66
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 52
- 238000000151 deposition Methods 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- -1 boron ion Chemical class 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000000992 sputter etching Methods 0.000 claims description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 98
- 238000010586 diagram Methods 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a manufacturing method of a shielded gate trench type power metal oxide semiconductor. The invention includes providing an epitaxial layer; photoetching is carried out on the epitaxial layer to obtain a groove; growing an oxide layer along the inner side of the groove; depositing a layer of first carbon doped silicon oxide in the groove after the oxide layer is grown; depositing source polycrystalline silicon in the groove after depositing a layer of first carbon doped silicon oxide; depositing second carbon-doped silicon oxide in the groove after depositing the source polycrystalline silicon; etching the oxide layer, the first carbon-doped silicon oxide and the second carbon-doped silicon oxide; growing a gate oxide layer and depositing gate polysilicon; photoetching to obtain a P-well region and an N+ well region; a dielectric layer is deposited. The obtained metal oxide semiconductor takes carbon doped silicon oxide as shielding on the periphery of the lower source polycrystalline silicon and on the upper dielectric layer, so that the switching loss of an input end and an output end can be optimized at the same time, and the existing voltage and current characteristics are not influenced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a shielded gate trench type power metal oxide semiconductor.
Background
In order to meet the requirement of environmental protection and power saving, the design of the shielded gate trench type power metal oxide semiconductor (Shielding gate MOSFET) has been widely studied in recent years, the functional characteristics of the shielded gate trench type power metal oxide semiconductor are greatly reduced in on-resistance compared with those of the conventional planar or trench type power metal oxide semiconductor, and the Cgd is almost completely shielded due to the design of the shielded gate assembly, so that the switching loss is greatly optimized, and the cost requirement is reduced.
The present invention is directed to further optimization of shield gate trench power metal oxide semiconductors.
Disclosure of Invention
The invention provides a manufacturing method of a shielded gate trench type power metal oxide semiconductor, wherein the metal oxide semiconductor obtained by the method takes carbon doped silicon oxide as a shielding layer around and above a lower source polycrystalline silicon, so that the switching loss of an input end and an output end can be optimized at the same time, and the existing voltage and current characteristics are not influenced.
In order to solve the technical problems, the invention provides a manufacturing method of a shielded gate trench type power metal oxide semiconductor, which comprises the following steps:
providing an epitaxial layer;
photoetching is carried out on the epitaxial layer to obtain a groove;
growing an oxide layer along the inner side of the groove;
depositing a layer of first carbon doped silicon oxide in the groove after the oxide layer is grown;
depositing source polycrystalline silicon in the groove after depositing a layer of first carbon doped silicon oxide;
depositing second carbon-doped silicon oxide in the groove after depositing the source polycrystalline silicon;
etching the oxide layer, the first carbon-doped silicon oxide and the second carbon-doped silicon oxide to obtain an oxide layer residual layer along the side wall of the groove and a carbon-doped silicon oxide residual layer positioned between the inner side of the oxide layer residual layer and the source polycrystalline silicon;
growing a gate oxide layer along the inner side of the groove, and depositing gate polysilicon in the groove after growing the gate oxide layer;
after a region is defined by a photoetching process, ion doping is carried out to obtain a P-well region and an N+ well region positioned at the upper part of the P-well region, wherein the N+ well region is flush with the upper surface of the P-well region;
depositing a dielectric layer of carbon doped silicon oxide on the upper surfaces of the gate polysilicon, the P-well region and the N+ well region;
and etching a metal contact hole on the dielectric layer of the carbon-doped silicon oxide through a photoetching process, depositing a metal layer above the dielectric layer of the carbon-doped silicon oxide, and enabling the extension end of the metal layer to pass through the dielectric layer of the carbon-doped silicon oxide, the N+ well region and extend to the P-well region through the metal contact hole.
In one embodiment of the present invention, the growing an oxide layer along the inner side of the trench includes:
and growing an oxide layer along the inner side of the groove in a high-temperature wet oxygen mode, wherein the temperature is 900-1100 ℃, and the thickness of the oxide layer is 0.2-0.4 mu m.
In one embodiment of the present invention, the depositing a gate oxide layer along the inner side of the trench includes:
and growing a layer of gate oxide layer along the inner side of the groove in a high-temperature dry oxygen mode, wherein the temperature is 900-1000 ℃.
In one embodiment of the present invention, the P-well region has a boron ion doping concentration of 6X10 12 ~3×10 13 /cm 2 The doped arsenic ion concentration of the N+ well region is 5 multiplied by 10 15 ~1×10 16 /cm 2 。
In one embodiment of the present invention, the depositing source polysilicon in the trench after depositing a layer of the first carbon doped silicon oxide further comprises:
and carrying out ion etching on the source polycrystalline silicon to obtain a triangular polycrystalline silicon side wall residual layer along the side wall of the groove.
In one embodiment of the present invention, a second carbon doped silicon oxide is deposited in the trench after depositing the source polysilicon, wherein the second carbon doped silicon oxide has a top surface that is higher than the top surface of the epitaxial layer.
In one embodiment of the present invention, the oxide layer residual layer upper surface is flush with the carbon doped silicon oxide residual layer upper surface and is lower than the epitaxial layer upper surface.
In one embodiment of the present invention, the depositing gate polysilicon in the trench after growing a gate oxide layer further comprises:
and etching the deposited gate polysilicon, so that the upper surface of the etched gate polysilicon is slightly lower than or equal to the upper surface of the epitaxial layer.
In one embodiment of the present invention, the gate polysilicon is in contact with the gate oxide layer, the oxide layer residual layer, and the carbon doped silicon oxide residual layer, respectively.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the manufacturing method of the shielded gate trench type power metal oxide semiconductor, the dielectric layers (ILD, inter-Layer Di-electric) around and above the lower source polycrystalline silicon are used as shielding, the dielectric coefficient of the common oxide Layer is about 4, the dielectric coefficient of the carbon doped silicon oxide Layer is about 3, and the characteristic of the capacitor is in direct proportion to the dielectric coefficient of the common oxide Layer, so that the low dielectric oxide Layer can respectively reduce part of the capacitance Cgs of the input end and part of the capacitance Cds of the output end.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.
FIG. 1 is a schematic diagram of a shield gate trench structure of the present invention.
FIG. 2 is a schematic diagram of the structure of the present invention for depositing a first carbon doped silicon oxide.
Fig. 3 is a schematic diagram of the present invention for depositing first source polysilicon.
FIG. 4 is a schematic illustration of the present invention for depositing a second carbon doped silicon oxide.
FIG. 5 is a schematic diagram of the present invention after etching the oxide layer, the first carbon-doped silicon oxide, and the second carbon-doped silicon oxide.
Fig. 6 is a schematic diagram of the present invention for depositing a second time source polysilicon.
FIG. 7 is a schematic diagram of the invention after photolithography of the P-well region and the N+ well region.
Fig. 8 is a schematic diagram of the present invention after deposition of a dielectric layer.
Fig. 9 is a schematic diagram of the present invention after deposition of a metal layer.
Fig. 10 is a schematic diagram of a shield gate trench structure with a triangular polysilicon sidewall residue layer in accordance with the present invention.
Description of the specification reference numerals:
100. an epitaxial layer; 11. a groove; 101. an oxide layer; 101a, an oxide layer residual layer; 102a, first carbon-doped silicon oxide; 102b, a second carbon doped silicon oxide; 102c, a carbon-doped silicon oxide residual layer; 103a, source polycrystalline silicon; 103b, gate polysilicon; 104a, a gate oxide layer; 105. a P-well region; 106. an n+ well region; 107. a carbon doped silicon oxide dielectric layer; 108. a metal layer; 108a, metal contact holes; 109. triangular polysilicon sidewall residual layers.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
In the present invention, if directions (up, down, left, right, front and rear) are described, they are merely for convenience of description of the technical solution of the present invention, and do not indicate or imply that the technical features must be in a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the present invention, "a plurality of" means one or more, and "a plurality of" means two or more, and "greater than", "less than", "exceeding", etc. are understood to not include the present number; "above", "below", "within" and the like are understood to include this number. In the description of the present invention, the description of "first" and "second" if any is used solely for the purpose of distinguishing between technical features and not necessarily for the purpose of indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the present invention, unless clearly defined otherwise, terms such as "disposed," "mounted," "connected," and the like should be construed broadly and may be connected directly or indirectly through an intermediate medium, for example; the connecting device can be fixedly connected, detachably connected and integrally formed; can be mechanically connected, electrically connected or capable of communicating with each other; may be a communication between two elements or an interaction between two elements. The specific meaning of the words in the invention can be reasonably determined by a person skilled in the art in combination with the specific content of the technical solution.
The manufacturing method of the shielded gate trench type power metal oxide semiconductor of the embodiment comprises the following steps:
s1, providing an epitaxial layer 100;
s2, photoetching is carried out on the epitaxial layer 100 to obtain a groove 11;
and S3, growing an oxide layer 101 along the inner side of the groove 11.
In this embodiment, an oxide layer 101 is grown along the inner side of the trench 11 by high-temperature wet oxygen, wherein the temperature is 900-1100 ℃, and the thickness of the oxide layer 101 is 0.2-0.4 μm.
S4, depositing a layer of first carbon doped silicon oxide 102a in the groove 11 after the oxide layer 101 is grown, wherein methyl (-CH 3) is introduced when the silicon oxide is deposited by a PECVD machine, so that SiOC H (carbon doped silicon oxide) is formed, and the thickness of the first carbon doped silicon oxide 102a is 0.2-0.4 mu m; reference is made to figure 2.
S5, depositing source polycrystalline silicon 103a in the groove 11 after the first carbon doped silicon oxide layer 102a is deposited by a PECVD machine, and etching the deposited source polycrystalline silicon 103 a; reference is made to fig. 3.
S6, depositing second carbon-doped silicon oxide 102b in the groove 11 after depositing the source polycrystalline silicon 103 a; wherein the upper surface of the second carbon doped silicon oxide 102b is higher than the upper surface of the epitaxial layer 100; reference is made to fig. 4.
S7, etching the oxide layer 101, the first carbon-doped silicon oxide 102a and the second carbon-doped silicon oxide 102b to obtain an oxide layer residual layer 101a along the side wall of the trench 11 and a carbon-doped silicon oxide residual layer 102c located between the inner side of the oxide layer residual layer 101a and the first source polysilicon 103 a; wherein the upper surface of the oxide layer residual layer 101a is flush with the upper surface of the carbon doped silicon oxide residual layer 102c and is lower than the upper surface of the epitaxial layer 100; reference is made to fig. 5.
S8, growing a gate oxide layer 104a along the inner side of the groove 11, depositing gate polysilicon 103b in the groove 11 after growing the gate oxide layer 104a, and etching the deposited gate polysilicon 103b to make the upper surface of the etched gate polysilicon 103b lower than or equal to the upper surface of the epitaxial layer 100; reference is made to fig. 6.
In this embodiment, a first gate oxide layer 104a is grown along the inner side of the trench 11 by high temperature dry oxygen, wherein the temperature is 900-1000 ℃.
S9, depositing a second gate oxide layer 104a on the upper surface of the second source polysilicon 103 a; wherein the second source polysilicon 103a is in contact with the first sub-gate oxide layer 104a, the second sub-gate oxide layer 104a, the oxide layer residual layer 101a and the carbon-doped silicon oxide residual layer 102c, respectively; reference is made to fig. 7.
S10, after a region is defined by a photoetching process, ion doping is carried out to obtain a P-well region 105 and an N+ well region 106 positioned at the upper part of the P-well region 105, wherein the upper surface of the N+ well region 106 is flush with the upper surface of the P-well region 105; reference is made to fig. 7.
In this embodiment, the doped boron ion concentration of the P-well region 105 is 6×10 12 ~3×10 13 /cm 2 The concentration of doped arsenic ions in the N+ well region 106 is 5×10 15 ~1×10 16 /cm 2 。
S11, depositing a dielectric layer 107 of carbon doped silicon oxide on the upper surfaces of the gate polysilicon 103b, the P-well region 105 and the N+ well region 106; reference is made to fig. 8.
S12, etching a metal contact hole 108a on the dielectric layer 107 of the carbon-doped silicon oxide, and depositing a metal layer 108 on the dielectric layer 107 of the carbon-doped silicon oxide, wherein the extension end of the metal layer 108 passes through the metal contact hole 108a, passes through the dielectric layer 107 of the carbon-doped silicon oxide, the N+ well region 106 and extends to the P-well region 105; reference is made to fig. 9.
Referring to fig. 10, when the aperture of the trench 11 is too small, a dry etching process may be added after step 5 (i.e. depositing the source polysilicon 103a in the trench 11 after depositing a layer of the first carbon-doped silicon oxide 102 a), i.e. ion etching the source polysilicon 103a to obtain a triangular polysilicon sidewall residual layer 109 along the sidewall of the trench 11, so as to avoid depositing the second carbon-doped silicon oxide 102b in step 6 to leave a crack.
Through the above process, a shield gate trench 11-type power metal oxide semiconductor is obtained, as shown with reference to fig. 1 or 10. The dielectric Layer (ILD) around and above the lower source polysilicon 103a is shielded by carbon doped silicon oxide (CDO, carbon Doped silicon Oxide), the dielectric coefficient of the oxide Layer 101 is about 4, the dielectric coefficient of the carbon doped silicon oxide is about 3, and the capacitance is proportional to the dielectric coefficient, so that the low dielectric oxide Layer 101 can reduce the partial capacitance Cgs (Cgs 1 and Cgs 2) of the input terminal and the partial capacitance Cds of the output terminal, respectively, as shown in fig. 1. The power MOS input end capacitor ciss=cgs+cgd and the output capacitor coss=cgd+cds simultaneously optimizes the switching loss of the input end and the output end without affecting the existing voltage-current characteristics.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (7)
1. A manufacturing method of a shielded gate trench type power metal oxide semiconductor is characterized by comprising the following steps:
providing an epitaxial layer (100);
carrying out photoetching on the epitaxial layer (100) to obtain a groove (11);
growing an oxide layer (101) along the inner side of the groove (11);
depositing a layer of first carbon doped silicon oxide (102 a) in the trench (11) after growing the oxide layer (101);
depositing source polysilicon (103 a) in the trench (11) after depositing a layer of first carbon doped silicon oxide (102 a);
depositing a second carbon doped silicon oxide (102 b) in the trench (11) after depositing the source polysilicon (103 a);
etching the oxide layer (101), the first carbon-doped silicon oxide (102 a) and the second carbon-doped silicon oxide (102 b) to obtain an oxide layer residual layer (101 a) along the side wall of the groove (11) and a carbon-doped silicon oxide residual layer (102 c) positioned between the inner side of the oxide layer residual layer (101 a) and the source polycrystalline silicon (103 a);
growing a gate oxide layer (104 a) along the inner side of the groove (11), and depositing gate polysilicon (103 b) in the groove (11) after growing the gate oxide layer (104 a);
after a region is defined by a photoetching process, ion doping is carried out to obtain a P-well region (105) and an N+ well region (106) positioned at the upper part of the P-well region (105), wherein the N+ well region (106) is flush with the upper surface of the P-well region (105);
depositing a carbon doped silicon oxide dielectric layer (107) on the upper surfaces of the gate polysilicon (103 b), the P-well region (105) and the n+ well region (106);
etching a metal contact hole (108 a) on the dielectric layer (107) of the carbon-doped silicon oxide through a photoetching process, and depositing a metal layer (108) above the dielectric layer (107) of the carbon-doped silicon oxide, wherein the extension end of the metal layer (108) passes through the dielectric layer (107) of the carbon-doped silicon oxide, the N+ well region (106) and extends to the P-well region (105) through the metal contact hole (108 a);
the gate polysilicon (103 b) is in contact with the gate oxide layer (104 a), the oxide layer residual layer (101 a) and the carbon-doped silicon oxide residual layer (102 c), respectively;
the depositing of source polysilicon (103 a) in the trench (11) after depositing a layer of first carbon doped silicon oxide (102 a) further comprises:
ion etching is performed on the source polysilicon (103 a) to obtain a triangular polysilicon sidewall residual layer (109) along the sidewalls of the trench (11).
2. The method of claim 1, wherein growing an oxide layer (101) along the inner side of the trench (11) comprises:
and growing an oxide layer (101) along the inner side of the groove (11) in a high-temperature wet oxygen mode, wherein the temperature is 900-1100 ℃, and the thickness of the oxide layer (101) is 0.2-0.4 mu m.
3. The method of claim 1, wherein depositing a gate oxide layer (104 a) along the inside of the trench (11) comprises:
a gate oxide layer (104 a) is grown along the inner side of the trench (11) by high temperature dry oxygen, wherein the temperature is 900-1000 ℃.
4. The method of claim 1, wherein the P-well region (105) has a boron ion doping concentration of 6 x 10 12 ~3×10 13 /cm 2 The doped arsenic ion concentration of the N+ well region (106) is 5×10 15 ~1×10 16 /cm 2 。
5. The method of claim 1, wherein a second carbon-doped silicon oxide (102 b) is deposited in the trench (11) after depositing the source polysilicon (103 a), wherein an upper surface of the second carbon-doped silicon oxide (102 b) is higher than an upper surface of the epitaxial layer (100).
6. The method of claim 1, wherein the top surface of the oxide layer residue layer (101 a) is level with the top surface of the carbon doped silicon oxide residue layer (102 c) and is lower than the top surface of the epitaxial layer (100).
7. The method of claim 1, wherein depositing gate polysilicon (103 b) in the trench (11) after growing a gate oxide layer (104 a), further comprises:
and etching the deposited gate polysilicon (103 b) so that the upper surface of the etched gate polysilicon (103 b) is slightly lower than or equal to the upper surface of the epitaxial layer (100).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310540946.6A CN116259544B (en) | 2023-05-15 | 2023-05-15 | Manufacturing method of shielded gate trench type power metal oxide semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310540946.6A CN116259544B (en) | 2023-05-15 | 2023-05-15 | Manufacturing method of shielded gate trench type power metal oxide semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116259544A CN116259544A (en) | 2023-06-13 |
| CN116259544B true CN116259544B (en) | 2023-08-08 |
Family
ID=86681086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310540946.6A Active CN116259544B (en) | 2023-05-15 | 2023-05-15 | Manufacturing method of shielded gate trench type power metal oxide semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116259544B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110429033A (en) * | 2019-08-21 | 2019-11-08 | 深圳市芯电元科技有限公司 | Shield grid groove MOSFET manufacturing method |
| CN111816709A (en) * | 2020-09-03 | 2020-10-23 | 江苏应能微电子有限公司 | Shielding gate trench type power metal oxide semiconductor field effect transistor |
| CN113571421A (en) * | 2021-09-24 | 2021-10-29 | 江苏应能微电子有限公司 | Oblique oxygen manufacturing method of shielded gate trench type MOS (metal oxide semiconductor) tube |
| CN114023647A (en) * | 2021-10-12 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Shielding gate trench MOSFET and manufacturing method thereof |
| CN115458599A (en) * | 2022-07-25 | 2022-12-09 | 深圳基本半导体有限公司 | SGT-MOSFET cell, manufacturing method thereof and electronic device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11469313B2 (en) * | 2020-01-16 | 2022-10-11 | Ipower Semiconductor | Self-aligned trench MOSFET and IGBT structures and methods of fabrication |
-
2023
- 2023-05-15 CN CN202310540946.6A patent/CN116259544B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110429033A (en) * | 2019-08-21 | 2019-11-08 | 深圳市芯电元科技有限公司 | Shield grid groove MOSFET manufacturing method |
| CN111816709A (en) * | 2020-09-03 | 2020-10-23 | 江苏应能微电子有限公司 | Shielding gate trench type power metal oxide semiconductor field effect transistor |
| CN113571421A (en) * | 2021-09-24 | 2021-10-29 | 江苏应能微电子有限公司 | Oblique oxygen manufacturing method of shielded gate trench type MOS (metal oxide semiconductor) tube |
| CN114023647A (en) * | 2021-10-12 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Shielding gate trench MOSFET and manufacturing method thereof |
| CN115458599A (en) * | 2022-07-25 | 2022-12-09 | 深圳基本半导体有限公司 | SGT-MOSFET cell, manufacturing method thereof and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116259544A (en) | 2023-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101558499B (en) | Structure and method for forming laterally extending dielectric layer in a trench-gate fet | |
| CN1172377C (en) | Lateral transistor with graded base region, semiconductor integrated circu8it and manufacturing method | |
| US8134222B2 (en) | MOS capacitor structures | |
| US6238981B1 (en) | Process for forming MOS-gated devices having self-aligned trenches | |
| US20040166619A1 (en) | Method of manufacturing transistor | |
| US9972496B2 (en) | Process for manufacturing a power device with a trench-gate structure and corresponding device | |
| JPH10335646A (en) | Mos field effect transistor element and its manufacture | |
| CN111092123A (en) | Lateral double-diffused transistor and manufacturing method thereof | |
| CN103107194A (en) | Trench type power transistor device and manufacturing method thereof | |
| US6087224A (en) | Manufacture of trench-gate semiconductor devices | |
| CN116259544B (en) | Manufacturing method of shielded gate trench type power metal oxide semiconductor | |
| US20100276810A1 (en) | Semiconductor device and fabrication method thereof | |
| US6156595A (en) | Method of fabricating a Bi-CMOS IC device including a self-alignment bipolar transistor capable of high speed operation | |
| CN113161238B (en) | Manufacturing process of gate-electrode sensitive trigger silicon controlled rectifier chip with high temperature characteristic | |
| US20030116823A1 (en) | Semiconductor device and fabrication method thereof | |
| CN111430461B (en) | Semiconductor structure and forming method thereof | |
| US6228698B1 (en) | Manufacture of field-effect semiconductor devices | |
| CN216719955U (en) | MOSFET structure with ESD protection | |
| US6137147A (en) | Bipolar transistor and semiconductor integrated circuit device | |
| CN112117327B (en) | IGBT device and manufacturing process thereof | |
| US7101750B2 (en) | Semiconductor device for integrated injection logic cell and process for fabricating the same | |
| US20010000113A1 (en) | Vertical double diffused MOSFET and method for manufacturing same | |
| CN114023823A (en) | MOSFET structure with ESD protection and manufacturing method | |
| EP4092724A1 (en) | Semiconductor die with a vertical power transistor device | |
| CN115548122A (en) | Device structure of shallow-trench MOSFET and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |