CN116257256A - Logic link management method and system for control logic configuration software - Google Patents
Logic link management method and system for control logic configuration software Download PDFInfo
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Abstract
The invention provides a logical link management method and a system for control logic configuration software, which belongs to the technical field of configuration software, and the method comprises the following steps: step S10, creating a data structure table for logical links; s20, carrying out grammar analysis on engineering logic; step S30, logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file; step S40, the link file is downloaded to the control station for execution by the control station. The invention has the advantages that: the unified management of the logic links is realized, and the running stability and efficiency of the control station are greatly improved.
Description
Technical Field
The invention relates to the technical field of configuration software, in particular to a logic link management method and system for control logic configuration software.
Background
The configuration software is also called configuration monitoring system software, and is special software for data acquisition and process control, and also refers to a software platform and a development environment at the level of an automatic control system monitoring layer. The software is also a general-purpose level software tool for rapidly constructing the monitoring function of the industrial automatic control system for users through a flexible configuration mode. The configuration software is widely applied to the fields of machinery, automobiles, petroleum, chemical industry, papermaking, water treatment, process control and the like.
The configuration software installed in the control station is operated by engineering logic, i.e. the engineering logic after logic link is downloaded to the control station for operating the control station. Logical links refer to linking and compiling logical pages of parsed engineering logic into code recognizable by a control station.
The logical links may be divided into loop links, node links, and system links; loop linking refers to linking all logical pages in a loop where a specified page is located; node linking refers to linking all logical pages in the current node; the system link refers to linking all nodes in the whole logic engineering respectively. For each logic link, conventionally, there is no unified management method, which causes conflict among codes compiled among different types of logic links, or different rules are required to be adopted for compiling, so that compiling efficiency is affected, and further stability and efficiency of operation of a control station are affected.
Therefore, how to provide a logic link management method and system for control logic configuration software, which implement unified management of logic links, so as to improve the stability and efficiency of operation of a control station, is a technical problem to be solved.
Disclosure of Invention
The invention aims to solve the technical problem of providing a logic link management method and a logic link management system for control logic configuration software, which realize unified management of logic links so as to improve the running stability and efficiency of a control station.
In a first aspect, the present invention provides a logical link management method for control logic configuration software, including the following steps:
step S10, creating a data structure table for logical links;
s20, carrying out grammar analysis on engineering logic;
step S30, logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
step S40, the link file is downloaded to the control station for execution by the control station.
Further, in the step S10, the data structure table at least includes fields of an array number, a description, a code, a data type definition, and a data type.
Further, in the step S10, the data structure table includes 90 arrays.
Further, the step S20 specifically includes:
step S21, saving engineering logic to be analyzed, traversing all logic nodes in an engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
step S22, traversing and searching each logic diagram under each logic loop, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram.
Further, in the step S22, the parsing for performing element input on the logic diagram specifically includes:
step S2211, judging whether the logic elements of the logic diagram need to be input, if yes, entering step S2212; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
step S2212, judging whether the number of the required inputs and the actual inputs of the logic element is consistent, if yes, proceeding to step S2213; if not, prompting the logic element to input the quantity error;
step S2213, checking the input sequence of the signal types input by the logic element, and performing syntax analysis of element parameters if the check is successful; if the verification fails, prompting that the input sequence is wrong;
the syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
step S2221, judging whether the logic element of the logic diagram needs to set parameters, if yes, entering step S2222; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
step S2222, traversing each logic element of the logic diagram in a left-to-right and top-to-bottom order, selecting logic elements which are not input elements, output elements and line elements;
step S2223, determining whether a parameter with a value different from 0 exists in each selected logic element, if yes, performing syntax analysis of element output; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
step S2231, determining whether the logic element of the logic diagram needs to be output, if yes, entering step S2232; if not, the grammar analysis output by the element passes;
step S2232, traversing each logic element of the logic diagram in a sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, if so, passing the grammar analysis of the element output; if not, the prompting element outputs an error.
In a second aspect, the present invention provides a logic link management system for control logic configuration software, including the following modules:
the data structure table creation module is used for creating a data structure table for logical link;
the grammar analysis module is used for carrying out grammar analysis on the engineering logic;
the link file generation module is used for logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
and the link file downloading module is used for downloading the link file to the control station for execution by the control station.
Further, in the data structure table creating module, the data structure table at least includes fields of an array number, a description, a code, a data type definition, and a data type.
Further, in the data structure table creation module, the data structure table includes 90 arrays.
Further, the syntax analysis module specifically includes:
the logic loop traversing unit is used for storing engineering logic to be analyzed, traversing all logic nodes in the engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
the logic diagram analysis unit is used for traversing and searching each logic diagram under each logic circuit, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram.
Further, in the logic diagram analysis unit, the syntax analysis for performing element input on the logic diagram specifically includes:
the input demand checking subunit is used for judging whether the logic elements of the logic diagram need to be input or not, if yes, the input quantity comparing subunit is entered; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
the input quantity comparison subunit is used for judging whether the quantity of the required input and the actual input of the logic element is consistent, if so, the logic element enters the input sequence checking subunit; if not, prompting the logic element to input the quantity error;
an input sequence checking subunit, configured to check an input sequence of each input signal type of the logic element, and perform syntax analysis on element parameters if the check is successful; if the verification fails, prompting that the input sequence is wrong;
the syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
the parameter setting requirement checking subunit is used for judging whether the logic element of the logic diagram needs to set parameters or not, and if so, entering the logic element screening subunit; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
a logic element screening subunit for traversing each logic element of the logic diagram in a left-to-right, top-to-bottom order, and selecting logic elements other than the input element, the output element, and the linear element;
the parameter value checking subunit is used for judging whether the selected logic elements have parameters with the value of not 0 or not, and if so, the syntax analysis of element output is carried out; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
the output requirement checking subunit is used for judging whether the logic elements of the logic diagram need to be output or not, and if yes, the output requirement checking subunit enters the output information comparing subunit; if not, the grammar analysis output by the element passes;
the output information comparison subunit is used for traversing each logic element of the logic diagram in sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, and if so, passing the grammar analysis of element output; if not, the prompting element outputs an error.
The invention has the advantages that:
1. through creating a data structure table for logic link, after the engineering logic is analyzed in grammar, the engineering logic is logically linked based on the data structure table to generate a link file, and finally the link file is downloaded to a control station for execution by the control station, namely, through creating the data structure table for loop link, node link and system link of the engineering logic, each logic link is uniformly managed, so that the conflict of codes compiled among different types of logic links is avoided, and different rules are avoided to compile, namely, the logic links are uniformly managed, and the running stability and efficiency of the control station are greatly improved.
2. By storing the engineering logic to be analyzed, traversing each logic node in the engineering system corresponding to the engineering logic, searching each logic loop under each logic node, traversing each logic graph under each logic loop, sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic graph, compiling and linking the engineering logic subjected to grammar analysis, and finally downloading a link file generated by compiling and linking to a control station, namely carrying out grammar analysis on the engineering logic downloaded to the control station in the engineering system, the logic nodes, the logic loops and the logic graph level, so as to comprehensively detect whether grammar errors exist in the engineering logic, avoid the engineering logic of which the control station operates based on the grammar errors, and greatly improve the operation stability of the control station.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method for logical link management for control logic configuration software according to the present invention.
FIG. 2 is a schematic diagram of a logical link management system for controlling logical configuration software according to the present invention.
Detailed Description
According to the technical scheme in the embodiment of the application, the overall thought is as follows: the data structure table is created for loop links, node links and system links of engineering logic, and all logic links are managed in a unified mode, so that the running stability and efficiency of the control station are improved.
Referring to fig. 1 to 2, a preferred embodiment of a logic link management method for controlling logic configuration software according to the present invention includes the following steps:
step S10, creating a data structure table for logical links;
s20, carrying out grammar analysis on engineering logic;
step S30, logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
step S40, the link file is downloaded to the control station for execution by the control station.
In the step S10, the data structure table at least includes fields of an array number, a description, a code, a data type definition, and a data type.
In the step S10, the data structure table includes 90 arrays.
The step S20 specifically includes:
step S21, saving engineering logic to be analyzed, traversing all logic nodes in an engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
step S22, checking whether the loop number of each logic loop exists or not, then traversing and searching each logic diagram under each logic loop, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram; i.e. to check the correctness of the element inputs, element parameters and element outputs.
The links of engineering logic are divided into system links, node links and loop links, so that logic analysis is required from the levels of engineering systems, logic nodes, logic loops and logic diagrams to comprehensively judge whether grammar errors exist.
In the step S22, the parsing for inputting the element to the logic diagram specifically includes:
step S2211, judging whether the logic elements of the logic diagram need to be input, if yes, entering step S2212; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
step S2212, starting with row 1 and column 1, judging whether the number of the required inputs and the number of the actual inputs of the logic elements are consistent in the order from left to right and from top to bottom, if yes, proceeding to step S2213; if not, prompting the input number of the lines and columns of the logic element to be wrong;
step S2213, checking the input sequence of the signal types input by the logic element, and performing syntax analysis of element parameters if the check is successful; if the verification fails, prompting the input sequence of the line and the column is wrong; for example, the input order of the signal type of a logic element is set to be analog, digital, or analog, and the actual input order is set to be analog, or digital, so that an error is indicated.
The syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
step S2221, judging whether the logic element of the logic diagram needs to set parameters, if yes, entering step S2222; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
step S2222, traversing each logic element of the logic diagram in a left-to-right and top-to-bottom order, selecting logic elements which are not input elements, output elements and line elements;
step S2223, determining whether a parameter with a value different from 0 exists in each selected logic element, if yes, performing syntax analysis of element output; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
step S2231, determining whether the logic element of the logic diagram needs to be output, if yes, entering step S2232; if not, the grammar analysis output by the element passes;
step S2232, traversing each logic element of the logic diagram in a sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, if so, passing the grammar analysis of the element output; if not, the prompting element outputs an error.
The invention relates to a preferred embodiment of a logic link management system oriented to control logic configuration software, which comprises the following modules:
the data structure table creation module is used for creating a data structure table for logical link;
the grammar analysis module is used for carrying out grammar analysis on the engineering logic;
the link file generation module is used for logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
and the link file downloading module is used for downloading the link file to the control station for execution by the control station.
In the data structure table creation module, the data structure table at least comprises fields of an array number, a description, a code, a data type definition and a data type.
In the data structure table creation module, the data structure table includes 90 arrays.
The grammar analysis module specifically comprises:
the logic loop traversing unit is used for storing engineering logic to be analyzed, traversing all logic nodes in the engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
the logic diagram analysis unit is used for checking whether the loop number of each logic loop exists or not, then traversing and searching each logic diagram under each logic loop, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram; i.e. to check the correctness of the element inputs, element parameters and element outputs.
The links of engineering logic are divided into system links, node links and loop links, so that logic analysis is required from the levels of engineering systems, logic nodes, logic loops and logic diagrams to comprehensively judge whether grammar errors exist.
In the logic diagram analysis unit, the syntax analysis for performing element input on the logic diagram specifically includes:
the input demand checking subunit is used for judging whether the logic elements of the logic diagram need to be input or not, if yes, the input quantity comparing subunit is entered; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
the input quantity comparison subunit is used for judging whether the quantity of the required input and the actual input of the logic element is consistent in sequence from left to right and from top to bottom by taking the 1 st row and the 1 st column as the start, and if so, entering the input sequence verification subunit; if not, prompting the input number of the lines and columns of the logic element to be wrong;
an input sequence checking subunit, configured to check an input sequence of each input signal type of the logic element, and perform syntax analysis on element parameters if the check is successful; if the verification fails, prompting the input sequence of the line and the column is wrong; for example, the input order of the signal type of a logic element is set to be analog, digital, or analog, and the actual input order is set to be analog, or digital, so that an error is indicated.
The syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
the parameter setting requirement checking subunit is used for judging whether the logic element of the logic diagram needs to set parameters or not, and if so, entering the logic element screening subunit; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
a logic element screening subunit for traversing each logic element of the logic diagram in a left-to-right, top-to-bottom order, and selecting logic elements other than the input element, the output element, and the linear element;
the parameter value checking subunit is used for judging whether the selected logic elements have parameters with the value of not 0 or not, and if so, the syntax analysis of element output is carried out; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
the output requirement checking subunit is used for judging whether the logic elements of the logic diagram need to be output or not, and if yes, the output requirement checking subunit enters the output information comparing subunit; if not, the grammar analysis output by the element passes;
the output information comparison subunit is used for traversing each logic element of the logic diagram in sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, and if so, passing the grammar analysis of element output; if not, the prompting element outputs an error.
The data structure table is exemplified as follows:
the field name naming convention hereinafter is: array name-array description-code (DT array name for the corresponding data engine).
E00-element code-DT 000:
this field is the number field of the logic element, the element number being the number that the logic element corresponds to in the data engine (control station), which number must be determined by the data engine and which is not substantially modified once determined. Corresponding to the id field in the "element class".
E02-element subscript-DT 002:
this field is the subscript field of the logic element, which serves to identify the current logic element. Each logic element should be given its own subscript. And the subscripts of the same logic element may not be identical in the same logic loop. For example, if there is a NOT element with a subscript of 1 already in the current logical loop, then when the NOT element is subsequently reused, its subscript may NOT be set to 1; but if NOT a NOT element, the 1 subscript may be used as long as the 1 subscript is NOT used. Logic elements can be divided into functional elements with subscripts ranging from 1 to 999 and input/output elements with subscripts ranging from 1 to 999, which may be later modified according to the actual situation.
E03-drawing number to which element belongs-DT 003:
i.e. the number of the figure in which the current logic element is located. Id attribute corresponding to Diagram.
E04-element row number-DT 004:
the rank number where the current logic element is located. The upper 8 bits represent the row number and the lower 8 bits represent the column number. For example, if the row and column number of a logic element is 1537, then the behavior of the graph in which it is located: 6, the columns are: 1. the calculation method is as follows: 1537 split into upper 8 bits: 00000110, the lower 8 bits are 00000001. So its row and column numbers are 6 and 1.
E05—absolute address-DT 005:
this field is assigned a value of 0.
E07—number of inputs-DT 007:
i.e. the number of inputs of the current logic element. If there is no input, the number of inputs is 0.
E08-address low order-DT 008 where input 1 is located:
the input n corresponds to the address value of the logic element. The address numbering sequence of the logic elements is the element sequence obtained by traversing the first logic diagram of the first logic circuit from left to right and from top to bottom in the logic diagram, namely the element address. Only the functional element and the input and output element calculate the element, and neither the connecting line nor the arrow and the like calculate the element. Inputs 1-6 all follow this rule.
Type of parameter value for E20-parameter 1-4-DT 020:
the parameter value type of element parameters 1-4.
Parameter value of E21-parameter 1-DT 021:
a value of parameter 1. (this is true for parameters 2-20)
E65-parameter value of parameter 21-DT 065:
the element calculates the period value, if 0, indicating that the default calculation period is used.
E81-element calculation sequence number-DT 081:
the calculated sequence number of the element is a value of the calculated sequence number generated by traversing the logic diagram according to a specified rule.
The traversal starts with the first logic diagram of the first logic loop. Traversing each logic element from left to right and from top to bottom according to the configuration picture. When the traversed logic element has no input, the sequence number accumulated at the moment is assigned to the logic element as a calculated sequence number. When the traversed logic element still has input, the input number is reduced once every time the logic element is traversed until the input number of the current logic element is reduced to 0, and the calculated serial number of the logic element is obtained.
E82-Loop number to which element belongs-DT 082:
the loop number to which the logic element belongs.
E83-element State-DT 083:
state of logic element, 0: initial value, and working states of TA and TD elements. 1: a normal computing state; 2: forced state.
E84—forced value-DT 084:
a forcing value of the logic element in a forcing state.
E85-physical sequence number of next element-DT 085:
the physical sequence number of the last logic element is-1, the others are 0.
E86—address of next element-DT 086:
the address here refers to an address value for numbering each element from 0 according to the traversal of the loop-logic diagram-configuration picture. The next element of the current element refers to the value ordered by element calculation sequence number.
Request URL: logicalanalysis/linkNode;
request parameter format: application/json;
the request mode is as follows: post;
request parameter list:
request format example:
return data type: JSON;
return field:
| sequence number | Name of the name | Data type | Remarks |
| 1 | code | Int | 0: successful operation |
| 2 | msg | String | |
| 3 | data | String |
In summary, the invention has the advantages that:
1. through creating a data structure table for logic link, after the engineering logic is analyzed in grammar, the engineering logic is logically linked based on the data structure table to generate a link file, and finally the link file is downloaded to a control station for execution by the control station, namely, through creating the data structure table for loop link, node link and system link of the engineering logic, each logic link is uniformly managed, so that the conflict of codes compiled among different types of logic links is avoided, and different rules are avoided to compile, namely, the logic links are uniformly managed, and the running stability and efficiency of the control station are greatly improved.
2. By storing the engineering logic to be analyzed, traversing each logic node in the engineering system corresponding to the engineering logic, searching each logic loop under each logic node, traversing each logic graph under each logic loop, sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic graph, compiling and linking the engineering logic subjected to grammar analysis, and finally downloading a link file generated by compiling and linking to a control station, namely carrying out grammar analysis on the engineering logic downloaded to the control station in the engineering system, the logic nodes, the logic loops and the logic graph level, so as to comprehensively detect whether grammar errors exist in the engineering logic, avoid the engineering logic of which the control station operates based on the grammar errors, and greatly improve the operation stability of the control station.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (10)
1. A logic link management method for control logic configuration software is characterized in that: the method comprises the following steps:
step S10, creating a data structure table for logical links;
s20, carrying out grammar analysis on engineering logic;
step S30, logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
step S40, the link file is downloaded to the control station for execution by the control station.
2. The method for logical link management for control logic configuration software according to claim 1, wherein: in the step S10, the data structure table at least includes fields of an array number, a description, a code, a data type definition, and a data type.
3. The method for logical link management for control logic configuration software according to claim 1, wherein: in the step S10, the data structure table includes 90 arrays.
4. The method for logical link management for control logic configuration software according to claim 1, wherein: the step S20 specifically includes:
step S21, saving engineering logic to be analyzed, traversing all logic nodes in an engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
step S22, traversing and searching each logic diagram under each logic loop, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram.
5. The method for logical link management for control logic configuration software according to claim 1, wherein: in the step S22, the parsing for inputting the element to the logic diagram specifically includes:
step S2211, judging whether the logic elements of the logic diagram need to be input, if yes, entering step S2212; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
step S2212, judging whether the number of the required inputs and the actual inputs of the logic element is consistent, if yes, proceeding to step S2213; if not, prompting the logic element to input the quantity error;
step S2213, checking the input sequence of the signal types input by the logic element, and performing syntax analysis of element parameters if the check is successful; if the verification fails, prompting that the input sequence is wrong;
the syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
step S2221, judging whether the logic element of the logic diagram needs to set parameters, if yes, entering step S2222; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
step S2222, traversing each logic element of the logic diagram in a left-to-right and top-to-bottom order, selecting logic elements which are not input elements, output elements and line elements;
step S2223, determining whether a parameter with a value different from 0 exists in each selected logic element, if yes, performing syntax analysis of element output; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
step S2231, determining whether the logic element of the logic diagram needs to be output, if yes, entering step S2232; if not, the grammar analysis output by the element passes;
step S2232, traversing each logic element of the logic diagram in a sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, if so, passing the grammar analysis of the element output; if not, the prompting element outputs an error.
6. A logic link management system for control logic configuration software is characterized in that: the device comprises the following modules:
the data structure table creation module is used for creating a data structure table for logical link;
the grammar analysis module is used for carrying out grammar analysis on the engineering logic;
the link file generation module is used for logically linking the engineering logic after the grammar analysis based on the data structure table to generate a link file;
and the link file downloading module is used for downloading the link file to the control station for execution by the control station.
7. The logical link management system for control logic configuration software of claim 6, wherein: in the data structure table creation module, the data structure table at least comprises fields of an array number, a description, a code, a data type definition and a data type.
8. The logical link management system for control logic configuration software of claim 6, wherein: in the data structure table creation module, the data structure table includes 90 arrays.
9. The logical link management system for control logic configuration software of claim 6, wherein: the grammar analysis module specifically comprises:
the logic loop traversing unit is used for storing engineering logic to be analyzed, traversing all logic nodes in the engineering system corresponding to the engineering logic, and searching all logic loops under all the logic nodes;
the logic diagram analysis unit is used for traversing and searching each logic diagram under each logic circuit, and sequentially carrying out grammar analysis comprising element input, element parameters and element output on each logic diagram.
10. The logical link management system for control logic configuration software of claim 6, wherein: in the logic diagram analysis unit, the syntax analysis for performing element input on the logic diagram specifically includes:
the input demand checking subunit is used for judging whether the logic elements of the logic diagram need to be input or not, if yes, the input quantity comparing subunit is entered; if not, the grammar analysis input by the element passes, and the grammar analysis of the element parameters is carried out;
the input quantity comparison subunit is used for judging whether the quantity of the required input and the actual input of the logic element is consistent, if so, the logic element enters the input sequence checking subunit; if not, prompting the logic element to input the quantity error;
an input sequence checking subunit, configured to check an input sequence of each input signal type of the logic element, and perform syntax analysis on element parameters if the check is successful; if the verification fails, prompting that the input sequence is wrong;
the syntax analysis of the element parameters of the logic diagram specifically comprises the following steps:
the parameter setting requirement checking subunit is used for judging whether the logic element of the logic diagram needs to set parameters or not, and if so, entering the logic element screening subunit; if not, the grammar analysis of the element parameters is passed, and the grammar analysis of the element output is carried out;
a logic element screening subunit for traversing each logic element of the logic diagram in a left-to-right, top-to-bottom order, and selecting logic elements other than the input element, the output element, and the linear element;
the parameter value checking subunit is used for judging whether the selected logic elements have parameters with the value of not 0 or not, and if so, the syntax analysis of element output is carried out; if not, prompting that the element parameters are wrong;
the syntax analysis for performing element output on the logic diagram specifically comprises the following steps:
the output requirement checking subunit is used for judging whether the logic elements of the logic diagram need to be output or not, and if yes, the output requirement checking subunit enters the output information comparing subunit; if not, the grammar analysis output by the element passes;
the output information comparison subunit is used for traversing each logic element of the logic diagram in sequence from left to right and from top to bottom, judging whether the output information of each logic element is consistent with the signal type, and if so, passing the grammar analysis of element output; if not, the prompting element outputs an error.
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| CN117250480B (en) * | 2023-11-08 | 2024-02-23 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
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