CN116256588A - Alternating current detection circuit, chip and emergency lighting system - Google Patents
Alternating current detection circuit, chip and emergency lighting system Download PDFInfo
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- CN116256588A CN116256588A CN202310538735.9A CN202310538735A CN116256588A CN 116256588 A CN116256588 A CN 116256588A CN 202310538735 A CN202310538735 A CN 202310538735A CN 116256588 A CN116256588 A CN 116256588A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/20—Responsive to malfunctions or to light source life; for protection
Abstract
The invention discloses an alternating current detection circuit, a chip and an emergency lighting system, which relate to the technical field of integrated circuits, wherein a first detection end and a second detection end of the alternating current detection circuit are respectively connected with an alternating current power grid, the alternating current detection circuit is used for judging that voltage which is larger than reference voltage VREF1 for the first time is the voltage of the first detection end or the voltage of the second detection end after the alternating current power grid is electrified, and outputting a judgment logic signal; generating a locking signal when the judging logic signal is effective, and locking the judging logic signal based on the locking signal; and then controlling the current direction of power failure detection to flow out from the high-voltage end of the first detection end and the second detection end according to the locking signal, and flowing into the low-voltage end of the first detection end and the second detection end after passing through the alternating current network. The invention realizes that each AC detection circuit connected to the AC power grid can not interfere with each other, and the power failure detection results of the AC power grid are consistent.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an alternating current detection circuit, a chip and an emergency lighting system.
Background
In some situations of ac applications, it is necessary to distinguish between neutral and hot when two or more systems powered by ac are connected to the grid. For example, in a power outage detection application, because of the need to detect the equivalent impedance of the ac grid (the impedance between zero and live lines), the power supply within the emergency lighting system will draw current from one of the inputs, which is returned to the other input after passing through the ac grid. It is clear to those skilled in the art that if the zero line and the live line of the above systems are in mixed connection, an error may occur in detecting the equivalent impedance of the power grid during power outage detection, that is, the mixed connection of the zero line and the live line may generate detection conflict.
Therefore, at present, the industry generally adopts measures that two power wires with different colors are used for distinguishing the zero line wire from the fire line wire when leaving a factory, and when two systems are connected in parallel to an alternating current power grid, strict distinction between the zero line wire and the fire line wire is required. However, for the convenience of installation, the installer cannot distinguish between the zero line and the live line, because this puts higher requirements on the application and wiring construction of the product, in the complex parallel wiring process, the ac wiring is very easy to be unreasonable, and once the zero line of the circuit system product is connected reversely, at this time, the power failure state of the ac power grid may not be correctly detected.
Disclosure of Invention
The embodiment of the invention provides an alternating current detection circuit, a chip and an emergency lighting system, which aim to solve the technical problems, and aim to realize that each alternating current detection circuit connected with an alternating current power grid cannot interfere with each other and have consistent power failure detection results on the alternating current power grid.
In order to solve the above problems, from a first aspect, an embodiment of the present invention discloses an ac detection circuit, which includes a first detection end, a second detection end, an ac synchronization judging module, a digital logic module, and a power failure detecting module, where the first detection end and the second detection end are respectively used for accessing an ac power grid, and the first detection end and the second detection end are: the alternating current synchronous judging module is used for judging that the voltage which is larger than the reference voltage VREF1 for the first time is the first detection terminal voltage or the second detection terminal voltage after the alternating current is electrified, and outputting a judging logic signal; the digital logic module is used for generating a locking signal when the judging logic signal is effective and locking the judging logic signal based on the locking signal; the power failure detection module is used for controlling the current direction of power failure detection to flow out from the high-voltage end of the first detection end and the second detection end according to the locking signal, and flows into the low-voltage end of the first detection end and the second detection end after passing through the alternating current power grid.
In an embodiment of the present invention, if the voltage greater than the reference voltage VREF1 is the voltage of the first detection end for the first time, the first detection end is connected to the live wire of the ac power grid, and the second detection end is connected to the zero line of the ac power grid; if the voltage larger than the reference voltage VREF1 is the voltage of the second detection end for the first time, the second detection end is connected with the live wire of the alternating current power grid, and the first detection end is connected with the zero line of the alternating current power grid.
In an embodiment of the present invention, the ac synchronization judging module includes: a first comparison sub-module, a second comparison sub-module,
the first comparison submodule is used for comparing a sampling voltage VL1 used for representing the voltage of the first detection end with a reference voltage VREF1 after the alternating current power is on, and outputting a first logic signal; the second comparing sub-module is used for comparing a sampling voltage VN1 used for representing the voltage of the second detection end with a reference voltage VREF1 after the alternating current power is on, and outputting a second logic signal; the logic signal is judged to be the combination of the first logic signal and the second logic signal; when the first logic signal and the second logic signal are both in a low level, judging that the logic signals are invalid; when the first logic signal and the second logic signal are at opposite levels, the logic signal is judged to be valid.
In one embodiment of the present invention, a digital logic module includes: a first logic sub-module and a second logic sub-module having the same circuit structure;
the first logic sub-module has a first input end connected with a first logic signal, a second input end connected with a signal EN2, a third input end connected with a signal EN1, and an output end outputting the signal EN1 or an inverted signal EN1B of the signal EN 1;
the first input end of the second logic sub-module is connected with a second logic signal, the second input end of the second logic sub-module is connected with a signal EN1, the third input end of the second logic sub-module is connected with a signal EN2, and the output end of the second logic sub-module outputs the signal EN2 or an inverted signal EN2B of the signal EN 2;
wherein, the signal EN1 and the signal EN2 have the same level at the initial moment of power-on of the alternating current network; when the logic signals are judged to be effective, the signal EN1 output by the first logic submodule and the signal EN2 output by the second logic submodule are used as locking signals; or, the inverted signal EN1B output from the first logic sub-module and the inverted signal EN2B output from the second logic sub-module are used as the lock signals.
In an embodiment of the present invention, the digital logic module further includes a power-on reset sub-module connected to the first logic sub-module and the second logic sub-module, respectively, and the power-on reset sub-module is configured to output a power-on reset signal; the first logic sub-module and the second logic sub-module also comprise a fourth input end, and the fourth input end is used for connecting a power-on reset signal; under the condition that the power-on reset signal is effective and the logic signal is judged to be effective, taking a signal EN1 output by the first logic submodule and a signal EN2 output by the second logic submodule as locking signals; or, the inverted signal EN1B output from the first logic sub-module and the inverted signal EN2B output from the second logic sub-module are used as the lock signals.
In an embodiment of the present invention, the power outage detection module includes: selecting a sub-module, a first clamping sub-module, a second clamping sub-module and a power failure judging sub-module;
the selection submodule is used for controlling the current direction of power failure detection to be from a first detection end to a second detection end or from the second detection end to the first detection end according to the received locking signal, and outputting a power failure detection voltage to the power failure judgment submodule;
the power failure judging submodule is used for comparing the power failure detection voltage with the reference voltage VREF2 and outputting an indication signal representing the power failure of the alternating current power grid under the condition that the power failure detection voltage is larger than the reference voltage VREF2 and the preset duration is continuous; wherein, the reference voltage VREF2 is smaller than the reference voltage VREF1;
the first clamping submodule is connected with the first detection end and the selection submodule, and the second clamping submodule is connected with the second detection end and the selection submodule; if the current direction of the power failure detection is controlled by the selection submodule to be from the first detection end to the second detection end, the first clamping submodule clamps the voltage of the first detection end to be the reference voltage VREF1, and the second clamping submodule generates power failure detection voltage based on the voltage of the first detection end and the equivalent impedance of an alternating current power grid between the first detection end and the second detection end; if the current direction of the power failure detection is controlled by the selection submodule to be from the second detection end to the first detection end, the second clamping submodule clamps the voltage of the second detection end to be the reference voltage VREF1, and the first clamping submodule generates the power failure detection voltage based on the voltage of the second detection end and the equivalent impedance of the alternating current power grid between the first detection end and the second detection end.
In an embodiment of the invention, the selection submodule comprises a first switch and a second switch; the first clamping submodule comprises a third comparator, a first MOS tube, a third MOS tube and a first resistor; one input end of the third comparator is connected with the reference voltage VREF1, the second input end of the third comparator is connected with the voltage of the first detection end, the output end of the third comparator is connected with the gate end of the first MOS tube and the drain end of the third MOS tube, the source end and the drain end of the first MOS tube are connected between the power supply voltage VDD and the first resistor, and the first resistor is grounded; the gate end of the third MOS tube is connected with the locking signal or the reverse signal of the locking signal, and the source end of the third MOS tube is grounded; one end of the first switch is connected between the first MOS tube and the first resistor, and the other end of the first switch is connected with the power failure judging submodule;
the second clamping submodule comprises a fourth comparator, a second MOS tube, a fourth MOS tube and a second resistor; one input end of the fourth comparator is connected with the reference voltage VREF1, the second input end of the fourth comparator is connected with the voltage of the second detection end, the output end of the fourth comparator is connected with the gate end of the second MOS tube and the drain end of the fourth MOS tube, the source end and the drain end of the second MOS tube are connected between the power supply voltage VDD and the second resistor, and the second resistor is grounded; the gate end of the fourth MOS tube is connected with a locking signal or an inverted signal of the locking signal, and the source end of the fourth MOS tube is grounded; one end of the second switch is connected between the second MOS tube and the second resistor, and the other end of the second switch is connected with the power failure judging submodule.
In one embodiment of the present invention, the power outage determination submodule includes: the non-inverting input end of the fifth comparator is connected with the reference voltage VREF2, the inverting input end of the fifth comparator is connected with the power failure detection voltage, the output end of the fifth comparator is connected with the timer through the inverter, and the output end of the timer is the output end of the power failure judging submodule.
In an embodiment of the present invention, the first logic submodule includes an and gate Y1, a nand gate Y2, and a nand gate Y3, where a first input end of the and gate Y1 is connected to a first logic signal through an inverter, and a second input end is connected to a signal EN2; the first input end of the NAND gate Y2 is connected with the output end of the AND gate Y1, and the second input end of the NAND gate Y2 is connected with the signal EN1; the first input end of the NAND gate Y3 is connected with the output end of the NAND gate Y2, the second input end is connected with the signal EN2, the third input end is connected with a power-on reset signal, and the output end outputs a signal EN1 or outputs EN1B after passing through an inverter; the second logic submodule comprises an AND gate Y4, a NAND gate Y5 and a NAND gate Y6, wherein a first input end of the AND gate Y4 is connected with a second logic signal through an inverter, and a second input end of the AND gate Y4 is connected with a signal EN1; the first input end of the NAND gate Y5 is connected with the output end of the AND gate Y4, and the second input end of the NAND gate Y5 is connected with the signal EN2; the first input end of the NAND gate Y6 is connected with the output end of the NAND gate Y5, the second input end is connected with the signal EN1, the third input end is connected with a power-on reset signal, and the output end outputs a signal EN2 or outputs EN2B after passing through an inverter.
In an embodiment of the invention, the ac detection circuit further comprises a driving module and a load switch, wherein one end of the load switch is connected with a power supply of the ac detection circuit, and the other end of the load switch is used for connecting a load; the driving module is connected between the power failure detection module and the load switch, and drives the load switch to conduct the power supply and the load based on the indication signal which is output by the power failure detection module and represents the power failure of the alternating current power grid.
From a second aspect, an embodiment of the present invention further discloses a chip, including an ac detection circuit according to the first aspect of the embodiment of the present invention.
From a third aspect, an embodiment of the present invention further discloses an emergency lighting system, including a load and a chip as in the second aspect of the embodiment of the present invention, where the chip is connected to the load.
The embodiment of the invention has the following advantages:
in the embodiment of the invention, because the alternating current detection circuit controls the current direction of power failure detection to flow out from the high voltage end of the first detection end and the second detection end based on the locking signal of the judgment result that the voltage which is larger than the reference voltage VREF1 for the first time is the first detection end voltage or the second detection end voltage, and flows into the low voltage end of the first detection end and the second detection end after passing through the alternating current power grid, the live wires determined in each alternating current detection circuit are consistent, and the zero wires are consistent. Therefore, whether the two alternating current detection circuits are connected into the alternating current power grid in a mixed connection mode or not, for each alternating current detection circuit, the judged power failure detection direction is from a live wire to a zero wire, all the alternating current detection circuits connected in parallel on the alternating current power grid can be guaranteed not to interfere with each other, and the power failure detection results of the alternating current power grid are consistent.
Compared with a mode of controlling the current direction of power failure detection after detecting the zero line and the live line in real time, the power failure detection result of the alternating current detection circuit is more stable and accurate, detection errors are not easy to occur due to other factors, and power consumption is saved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are only some embodiments of the present application.
FIG. 1 is a schematic diagram of two AC detection circuits connected to an AC power grid in an un-hybrid connection;
FIG. 2 is a schematic diagram of two AC detection circuits connected to an AC power grid in a hybrid connection;
FIG. 3 is a schematic circuit diagram of an AC detection circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of an AC detection circuit according to an embodiment of the present invention;
FIG. 5 is a circuit block diagram of an alternate current detection circuit according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of an AC detection circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a chip according to an embodiment of the invention;
fig. 8 is a schematic structural view of an emergency lighting system according to an embodiment of the present invention.
Reference numerals illustrate:
10-an alternating current synchronous judging module, 20-a digital logic module, 30-a power failure detecting module and 40-a voltage generating module;
101-a first comparison sub-module, 102-a second comparison sub-module; 201-a first logic sub-module, 202-a second logic sub-module; 301-a selection sub-module, 302-a first clamping sub-module, 303-a second clamping sub-module, 304-a power failure judgment sub-module, and 305-a power-on reset sub-module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application.
In practical applications, a plurality of ac detection circuits are connected to an ac power grid, and the connection modes of the ac detection circuits connected to the ac power grid may be mixed or not. Referring to fig. 1, a schematic diagram of two ac detection circuits connected to an ac power grid in an un-mixed connection manner is shown, that is, a first detection end of an ac detection circuit a and a first detection end of an ac detection circuit B are connected to the same ac line, and a second detection end of the ac detection circuit a and a second detection end of the ac detection circuit B are connected to the remaining ac line; as shown in fig. 2, two ac detection circuits are connected to an ac power grid in a mixed connection manner, that is, the ac lines connected to the first detection end of the ac detection circuit a and the first detection end of the ac detection circuit B are opposite, and the ac lines connected to the second detection end of the ac detection circuit a and the second detection end of the ac detection circuit B are opposite.
In some situations of ac applications, such as power outage detection applications, the existing ac detection circuit determines whether the ac power grid has a power outage based on the current direction from the live wire to the neutral wire, and generally defaults to the first detection end being connected to the ac line as the live wire and the second detection end being connected to the ac line as the neutral wire. If two AC detection circuits are connected in a mixed mode in a wiring mode of an AC power grid, namely, zero and live wires judged by the two AC detection circuits are different, mutual interference between the two AC detection circuits can be caused, and the power failure detection results of the two AC detection circuits on the AC power grid are inconsistent.
In view of this, the embodiment of the invention provides an ac detection circuit, which is used for accessing an ac power grid through a first detection end and a second detection end respectively. Referring to fig. 3, a schematic circuit diagram of an ac detection circuit according to an embodiment of the present invention includes: the alternating current detection circuit comprises a first detection end, a second detection end, an alternating current synchronous judging module 10, a digital logic module 20 and a power failure detection module 30, wherein the first detection end and the second detection end are respectively used for being connected into an alternating current power grid, and the alternating current detection circuit comprises:
the ac synchronization determining module 10 is configured to determine that, after the ac power is turned on, a voltage greater than the reference voltage VREF1 is the first detection terminal voltage or the second detection terminal voltage, and output a determination logic signal.
As is well known in the art, an ac power grid may be understood as an ac power source such as a utility power source, and an ac power grid may be understood as a switch for controlling the ac power to be turned on, such as a utility power switch being turned on. Ac grids are generally divided into three cases: (1) closing a mains switch, and electrifying alternating current; (2) closing a mains switch, and cutting off the alternating current; (3) the mains switch is turned off.
In the embodiment of the present invention, the ac synchronization judging module 10 has a voltage comparing function, which can compare the first detection terminal voltage and the second detection terminal voltage with the reference voltage VREF1 at the same time, and output a judging logic signal. The judging logic signal is used for representing a comparison result of the first detection terminal voltage and the reference voltage VREF1 and a comparison result of the second detection terminal voltage and the reference voltage VREF 1. Under the condition that alternating current is electrified, the first detection end and the second detection end are both provided with alternating current input, and because the alternating current is sine wave, the levels of the two alternating current lines have phase differences, the levels of the voltage of the first detection end and the voltage of the second detection end at the same moment are different, and the alternating current synchronous judgment module 10 can judge that the voltage which is larger than the reference voltage VREF1 for the first time is the voltage of the first detection end or the voltage of the second detection end under the condition, and at the moment, the output judgment logic signal is valid; under the condition that the alternating current power is cut off and the mains switch is disconnected, the first detection end and the second detection end are not input with alternating current, the voltage of the first detection end and the voltage of the second detection end are smaller than the reference voltage VREF1, and at the moment, the judgment logic signals output by the alternating current synchronization judgment module 10 are invalid.
The digital logic module 20 is configured to generate a lock signal when the judgment logic signal is valid, and lock the judgment logic signal based on the lock signal.
In the embodiment of the present invention, after the lock signal locks the judgment logic signal, no matter in which of the three situations the ac power grid is, the lock signal is not changed, that is, the lock signal corresponds to the judgment result that the voltage greater than the reference voltage VREF1 for the first time is the first detection terminal voltage, or corresponds to the judgment result that the voltage greater than the reference voltage VREF1 for the first time is the second detection terminal voltage. Based on this concept, the digital logic module 20 can be implemented with various combinations of circuits such as and gates, nand gates, or gates, nor gates, and inverters.
The power failure detection module 30 is configured to control a current direction of power failure detection according to a locking signal to flow out from a high voltage end of the first detection end and the second detection end, and flow into a low voltage end of the first detection end and the second detection end after passing through the ac power grid.
After the alternating current is electrified, the voltage which is larger than the reference voltage VREF1 for the first time is judged to be the first detection terminal voltage or the second detection terminal voltage. Optionally, if the voltage greater than the reference voltage VREF1 is the voltage of the first detection end for the first time, determining the ac line connected to the first detection end as the live line of the ac power grid, and determining the ac line connected to the second detection end as the zero line of the ac power grid; if the voltage which is larger than the reference voltage VREF1 for the first time is the voltage of the second detection end, the alternating current line connected with the second detection end is determined to be the live wire of the alternating current power grid, and the alternating current line connected with the first detection end is determined to be the zero line of the alternating current power grid.
Since each ac detection circuit determines the neutral and hot based on this logic, the hot determined within each ac detection circuit is consistent and the neutral is consistent. Therefore, whether the two alternating current detection circuits are connected into the alternating current power grid in a mixed connection mode or not, for each alternating current detection circuit, the judged power failure detection direction is from a live wire to a zero wire, all the alternating current detection circuits connected in parallel on the alternating current power grid can be guaranteed not to interfere with each other, and the power failure detection results of the alternating current power grid are consistent. In other words, by adopting the alternating current detection circuit, a plurality of alternating current detection circuits can be directly connected in parallel into an alternating current power grid, and the problem of whether zero and live wires are connected in a mixed mode or not is not needed to be considered, namely, zero and live wires are not needed to be strictly distinguished.
It should be emphasized that, since the current direction of the power outage detection can be controlled only by judging whether the voltage larger than the reference voltage VREF1 is the first detection terminal voltage or the second detection terminal voltage for the first time, the present invention can be provided for the first time when the ac detection circuit is installed. The voltage which is larger than the reference voltage VREF1 for the first time is judged to be the first detection terminal voltage or the second detection terminal voltage by the aid of the alternating current detection circuit during installation, then the current direction of power failure detection is fixed based on a locking signal generated when a logic signal is judged to be effective, and in the follow-up operation, as long as a battery of the alternating current detection circuit is powered on, power failure detection can be directly carried out based on the fixed power failure detection current direction without judging any more. Compared with a mode of controlling the current direction of power failure detection after detecting the zero line and the live line in real time, the power failure detection result of the alternating current detection circuit is more stable and accurate, detection errors are not easy to occur due to other factors, and power consumption is saved.
Based on the circuit principle of fig. 3, in an embodiment of the present invention, referring to fig. 4, the circuit structure of the ac detection circuit may be as follows:
as shown in fig. 4, the ac synchronization judging module 10 includes: a first comparison sub-module 101 and a second comparison sub-module 102. The first comparing sub-module 101 is configured to compare a sampling voltage VL1 for representing the voltage of the first detection terminal with a reference voltage VREF1 after the ac power is on, and output a first logic signal; the second comparing sub-module 102 is configured to compare a sampling voltage VN1 representing the second detection terminal voltage with a reference voltage VREF1 after the ac power is on, and output a second logic signal. In the embodiment of the invention, the logic signal is judged to be the combination of the first logic signal and the second logic signal; when the first logic signal and the second logic signal are both at a low level, judging that the logic signals are invalid; when the first logic signal and the second logic signal are at opposite levels, the logic signal is judged to be valid.
In the case that both the first comparison sub-module 101 and the second comparison sub-module 102 are implemented based on a 1-bit comparator, then both the first logic signal and the second logic signal are 1-bit signals, and the judgment logic signal is represented by 2 bits, and based on different ac grid conditions, the judgment logic signal has the following three conditions, "00", "01", and "10", respectively. Under the condition that alternating current is electrified, the first detection end and the second detection end can have alternating current input, the level of the sampling voltage VL1 and the level of the sampling voltage VN1 at the same time are different, at the moment, the judgment logic signals output by the alternating current synchronous judgment module 10 are '01' or '10', when the judgment logic signals are respectively corresponding to the first judgment, the sampling voltage VL1 is larger than the reference voltage VREF1 or the sampling voltage VN1 is larger than the reference voltage VREF1, and the judgment logic signals are effective. In practical applications, the "01" may be used to indicate that the sampled voltage VL1 is greater than the reference voltage VREF1, or the "10" may be used to indicate that the sampled voltage VL1 is greater than the reference voltage VREF1, which is not limited in the present invention. Under the condition that the alternating current power is cut off and the mains switch is turned off, the first detection end and the second detection end have no alternating current input, the sampling voltage VL1 and the sampling voltage VN1 are smaller than the reference voltage VREF1, and at the moment, the judgment logic signal output by the alternating current synchronization judgment module 10 is '00', and the judgment logic signal is invalid.
With continued reference to fig. 4, digital logic module 20 includes: a first logic sub-module 201 and a second logic sub-module 202 having the same circuit structure; the first input end of the first logic sub-module 201 is connected with the first logic signal, the second input end is connected with the signal EN2, the third input end is connected with the signal EN1, and the output end outputs the signal EN1 or an inverted signal EN1B of the signal EN 1; the first input of the second logic sub-module 202 is connected to the second logic signal, the second input is connected to the signal EN1, the third input is connected to the signal EN2, and the output is connected to the signal EN2 or the inverse signal EN2B of the signal EN 2. The signal EN1 and the signal EN2 have the same level at the initial time of power-up of the ac power network, and may specifically be set to be the same high level or the low level. Since the signal EN1 and the signal EN2 have the same level at the initial time, when the logic signal is determined to be valid, the level of the signal EN1 output by the first logic sub-module 201 or the level of the signal EN2 output by the second logic sub-module 202 may change, for example, from a high level to a low level, and at this time, the signal EN1 output by the first logic sub-module 201 and the signal EN2 output by the second logic sub-module 202 may be used as the lock signal, or the inverted signal EN1B output by the first logic sub-module 201 and the inverted signal EN2B output by the second logic sub-module 202 may be used as the lock signal.
As shown in fig. 4, the power outage detection module 30 according to the embodiment of the present invention includes: the selection sub-module 301, the first clamping sub-module 302, the second clamping sub-module 303 and the power outage judgment sub-module 304. The selection sub-module 301 is configured to control a current direction of power outage detection from a first detection end to a second detection end or from the second detection end to the first detection end according to the received locking signal, and output a power outage detection voltage to the power outage judgment sub-module 304; the power failure judging sub-module 304 is configured to compare the power failure detection voltage with a reference voltage VREF2, and output an indication signal indicating that the ac power grid has a power failure if the power failure detection voltage is greater than the reference voltage VREF2 for a preset period of time; wherein, the reference voltage VREF2 is smaller than the reference voltage VREF1; the first clamping sub-module 302 is connected with the first detection end and the selection sub-module 301, and the second clamping sub-module 303 is connected with the second detection end and the selection sub-module 301; if the selection sub-module 301 controls the current direction of the power outage detection to be from the first detection end to the second detection end, the first clamping sub-module 302 clamps the first detection end voltage to be the reference voltage VREF1, and the second clamping sub-module 303 generates the power outage detection voltage based on the first detection end voltage and the equivalent impedance of the ac power grid between the first detection end and the second detection end; if the selection sub-module 301 controls the current direction of the power outage detection to be from the second detection end to the first detection end, the second clamping sub-module 303 clamps the second detection end voltage to the reference voltage VREF1, and the first clamping sub-module 302 generates the power outage detection voltage based on the second detection end voltage and the ac grid equivalent impedance between the first detection end and the second detection end.
In addition, in the embodiment of the present invention, as shown in fig. 4, the ac detection circuit further includes a voltage generation module 40, and the voltage generation module 40 is configured to generate the reference voltage VREF1 and the reference voltage VREF2. The voltage generation module 40 may be implemented using, for example, a bandgap reference voltage source bandgap, etc. In practical circuits, the ac detection circuit according to the embodiments of the present invention may further include some other circuits, such as an OSC oscillator, which is not described herein because it is not important to the present invention.
In another embodiment of the present invention, referring to fig. 5, unlike the previous embodiment, the digital logic module 20 of the present invention may further include a power-on reset sub-module 305 connected to the first logic sub-module 201 and the second logic sub-module 202, respectively, where the power-on reset sub-module 305 is configured to output a power-on reset signal (the power-on reset signal is denoted by POR in fig. 5); the first logic sub-module 201 and the second logic sub-module 202 each further include a fourth input end, where the fourth input end is used to connect to the power-on reset signal; when the power-on reset signal is valid and the logic signal is judged to be valid, the signal EN1 output by the first logic sub-module 201 and the signal EN2 output by the second logic sub-module 202 are used as locking signals; or, the inverted signal EN1B output from the first logic sub-module 201 and the inverted signal EN2B output from the second logic sub-module 202 are used as the lock signals. The embodiment of the invention can effectively fix the level of the signal EN1 and the signal EN2 at the initial moment of power-on of the alternating current network by arranging the power-on reset submodule 305. Optionally, the power-on reset signal is valid at a high level, that is, before the ac power is turned on, the power-on reset signal is at a low level, so that the signal EN1 and the signal EN2 are both at a high level at an initial time of the ac power on; after the ac power is applied, the power-on reset signal remains high.
Furthermore, on the basis of the foregoing embodiment, the ac detection circuit of the present invention may further include a driving module and a load switch, where one end of the load switch is connected to a power supply of the ac detection circuit, and the other end is used to connect to a load; the driving module is connected between the power failure detection module 30 and the load switch, and drives the load switch to conduct the power supply and the load based on the indication signal which is output by the power failure detection module 30 and represents the power failure of the alternating current power grid. Based on this embodiment, for example, an activation of emergency lighting may be achieved.
Taking the technical scheme shown in fig. 5 as an example, a specific circuit of an embodiment is further described below.
As shown in fig. 6, the first comparing sub-module 101 is implemented based on the first comparator AMP1, the second comparing sub-module 102 is implemented based on the second comparator AMP2, the first logic unit includes and gate Y1, nand gate Y2, and nand gate Y3, and the second logic unit includes and gate Y4, nand gate Y5, and nand gate Y6.
The non-inverting input end of the first comparator AMP1 is connected with the sampling voltage VL1, the inverting input end of the first comparator AMP is connected with the reference voltage VREF1, and the output end of the first comparator AMP outputs a first logic signal; the first input end of the AND gate Y1 is connected with a first logic signal through an inverter, and the second input end is connected with a signal EN2; the first input end of the NAND gate Y2 is connected with the output end of the AND gate Y1, and the second input end of the NAND gate Y2 is connected with the signal EN1; the first input end of the NAND gate Y3 is connected with the output end of the NAND gate Y2, the second input end is connected with the signal EN2, the third input end is connected with a power-on reset signal, and the output end outputs a signal EN1 or outputs EN1B after passing through an inverter;
The non-inverting input end of the second comparator AMP2 is connected with the sampling voltage VN1, the inverting input end of the second comparator AMP is connected with the reference voltage VREF1, and the output end of the second comparator AMP outputs a second logic signal; the first input end of the AND gate Y4 is connected with a second logic signal through an inverter, and the second input end is connected with a signal EN1; the first input end of the NAND gate Y5 is connected with the output end of the AND gate Y4, and the second input end of the NAND gate Y5 is connected with the signal EN2; the first input end of the NAND gate Y6 is connected with the output end of the NAND gate Y5, the second input end is connected with the signal EN1, the third input end is connected with a power-on reset signal, and the output end outputs a signal EN2 or outputs EN2B after passing through an inverter.
As shown in fig. 6, the selection sub-module 301 includes a first switch S1 and a second switch S2; the first clamping submodule 302 includes a third comparator AMP3, a first MOS transistor NM1, a third MOS transistor NM3, and a first resistor; the second clamping submodule 303 includes a fourth comparator AMP4, a second MOS transistor NM2, a fourth MOS transistor NM4, and a second resistor.
One input end of the third comparator AMP3 is connected with the reference voltage VREF1, the second input end is connected with the voltage of the first detection end, the output end is connected with the gate end of the first MOS tube NM1 and the drain end of the third MOS tube NM3, the source end and the drain end of the first MOS tube NM1 are connected between the power voltage VDD and the first resistor, and the first resistor is grounded; the gate end of the third MOS tube NM3 is connected with a locking signal or an inverted signal of the locking signal, and the source end of the third MOS tube NM3 is connected with the ground; one end of the first switch S1 is connected between the first MOS tube NM1 and the first resistor, and the other end is connected with the power failure judging submodule 304;
One input end of the fourth comparator AMP4 is connected with the reference voltage VREF1, the second input end is connected with the voltage of the second detection end, the output end is connected with the gate end of the second MOS tube NM2 and the drain end of the fourth MOS tube NM4, the source end and the drain end of the second MOS tube NM2 are connected between the power voltage VDD and the second resistor, and the second resistor is grounded; the gate end of the fourth MOS tube NM4 is connected with a locking signal or an inverted signal of the locking signal, and the source end of the fourth MOS tube NM4 is connected with the ground; one end of the second switch S2 is connected between the second MOS transistor NM2 and the second resistor, and the other end is connected to the power outage determination submodule 304.
The first resistor may be a resistor R1 and a resistor R2, the second resistor may be a resistor R3 and a resistor R4, the voltage on the resistor R2 is the sampling voltage VL1, and the voltage on the resistor R4 is the sampling voltage VN1.
As shown in fig. 6, the power outage determination submodule 304 includes: fifth comparator AMP5, an inverter and a timer.
The non-inverting input terminal of the fifth comparator AMP5 is connected to the reference voltage VREF2, the inverting input terminal thereof is connected to the power failure detection voltage, the output terminal thereof is connected to a timer through an inverter, and the output terminal of the timer is the output terminal of the power failure judgment sub-module 304.
The working process of the embodiment of the invention is as follows:
Before the power-on reset signal is electrified on the alternating current network, the power-on reset signal POR is in a low level, so that the signal EN1 and the signal EN2 are both in a high level at the initial time of the power-on of the alternating current network; after the ac power-on, the power-on reset signal POR remains high.
(1) The mains switch is closed, and the alternating current power grid is electrified:
it is assumed that the first detection of the ac detection circuit a is terminated to the L line of the ac power grid and the second detection is terminated to the N line of the ac power grid. Then the sampling voltage VL1 on the L line is greater than VREF1, the first comparator AMP1 outputs a high level, and after passing through the inverter, outputs a low level, and then the and gate Y1 outputs a low level, and the nand gate Y2 outputs a high level; since the initial levels of the power-on reset signal POR and the signal EN2 are high, the nand gate Y3 outputs a low level at this time, that is, the signal EN1 changes from high level to low level; since the circuits are synchronous, the sampling voltage VN1 on the N line at the same time is necessarily smaller than VREF1, the second comparator AMP2 outputs a low level, and outputs a high level after passing through the inverter, at this time, the signal EN1 and the signal EN2 are still at a high level, the and gate Y4 outputs a high level, the nand gate Y5 outputs a low level, the nand gate Y6 outputs a high level, and the signal EN2 is kept at a high level.
Since the signal EN1 changes from high level to low level, the nand gate Y2 must output high level, and since the signal EN2 and the power-on reset signal POR remain high level, the nand gate Y3 outputs low level, i.e. the signal EN1 remains low level; while the signal EN1 received by the nand gate Y6 remains low, it will also remain high, i.e. the signal EN2 remains high. Therefore, no matter how the first detection terminal voltage and the second detection terminal voltage change, the invention has realized the locking of the judgment result that the voltage which is larger than the reference voltage VREF1 for the first time is the first detection terminal voltage or the second detection terminal voltage.
If EN1B and EN2B are used as the lock signals, EN1B is high and EN2B is low. The switch S1 is kept open based on EN2B, the switch S2 is closed based on EN1B, the second detection terminal is connected to the inverting input terminal of the fifth comparator AMP5, and the current direction of the power failure detection of the ac detection circuit a is from the first detection terminal to the second detection terminal, i.e., from the L line to the N line.
It is assumed that the ac detection circuit B is in hybrid connection with the ac detection circuit a, i.e., the first detection of the ac detection circuit B is terminated with the N line of the ac power grid, and the second detection is terminated with the L line of the ac power grid. The first time is greater than VREF1, the up-sampling voltage VN1 is N lines, the second comparator AMP2 outputs high level, the low level is output after passing through the inverter, the AND gate Y4 outputs low level, and the NOT gate Y5 outputs high level; since the initial levels of the power-on reset signal POR and the signal EN1 are high, the nand gate Y6 outputs a low level at this time, and the signal EN2 changes from high level to low level; since the circuits are synchronized, the sampling voltage VL1 on the L line at the same time is necessarily smaller than VREF1, the first comparator AMP1 outputs a low level, and outputs a high level after passing through the inverter, at this time, the signal EN1 and the signal EN2 are still at a high level, the and gate Y1 outputs a high level, the nand gate Y2 outputs a low level, the nand gate Y3 outputs a high level, and the signal EN1 is kept at a high level.
At this time, the lock signal: EN1B is low and EN2B is high. The switch S1 is closed based on EN2B, the switch S2 is opened based on EN1B, the first detection end is communicated with the inverting input end of the fifth comparator AMP5, and the current direction of the power failure detection of the ac detection circuit B is from the second detection end to the first detection end, i.e., from the L line to the N line.
Therefore, although the ac detection circuit A, B is connected to the ac power grid in a hybrid connection manner, for each ac detection circuit, the power outage detection direction determined by the ac detection circuit is from the live wire to the zero wire, so that all ac detection circuits connected in parallel to the ac power grid can be ensured not to interfere with each other, and the power outage detection results of the ac power grid are consistent.
In this case, since the ac power is usually 50Hz, the high and low levels are continuously output in an interleaved manner, and therefore, for the ac detection circuit a, although the second detection terminal voltage, i.e., the N-line voltage VN2 > VREF1 > VREF2, the fifth comparator AMP5 outputs the low level, and outputs the high level OUT to the timer after passing through the inverter, the high level signal received by the timer cannot last for a preset period of time, such as 1.5S, so the signal out_en output by the timer is still low level, indicating that the ac power grid is not powered off. In this case, the signal out_en output by the ac detection circuit B is still at a low level, and the ac power grid is not powered off, which is not repeated here.
(2) The mains switch is closed, and the alternating current power is cut off:
in the case of an ac power outage, for each ac detection circuit, the first detection terminal voltage and the second detection terminal voltage are both lower than VREF1, and the third comparator AMP3 and the fourth comparator AMP4 both output a high level.
Taking the ac detection circuit a as an example, although the fourth comparator AMP4 outputs a high level, the MOS transistor NM4 is turned on due to EN2 being at a high level, and the NM4 pulls down the gate voltage of the MOS transistor NM2 to 0, so that the NM2 cannot be turned on. The EN1 is low, so that the MOS transistor NM3 cannot be turned on, and therefore the MOS transistor NM1 is turned on based on the high level output by the third comparator AMP3, so that the third comparator AMP3 clamps the first detection terminal voltage to VREF1.
Since the switch S1 is opened based on EN2B, the switch S2 is closed based on EN1B, and the second detection terminal voltage VN2 is connected to the fifth comparator AMP5 as the power outage detection voltage and compared with VREF 2.
VN2 = VREF1 (r1+r2)/(r1+r2+rl+rx+rn), where RL is the L-line impedance, RN is the N-line impedance, and Rx is the ac grid equivalent impedance. If VN2 > VREF2, the fifth comparator AMP5 outputs a low level, outputs a high level OUT after passing through the inverter, and the high level continues for a preset period of time, for example, 1.5S, and finally, the signal out_en output by the timer is a high level, which indicates that the ac power grid has a power failure. In a specific circuit, the signal out_en may be used for practical applications, such as activating emergency lighting, which is not limited in the present invention.
In the ac detection circuit B, the fourth comparator AMP4 clamps the second detection terminal voltage to VREF1, and the first detection terminal VL2 is connected to the fifth comparator AMP5 as the power outage detection voltage and compared with VREF2, that is, vl2=vref 1 (r1+r2)/(r1+r2+rl+rx+rn). The power failure judgment principle is the same as that of the alternating current detection circuit A, and is not repeated here.
(3) The mains switch is turned off:
when the mains switch is turned off, rx becomes infinite, and for each ac detection circuit, the power outage detection voltage=vref 1 (r1+r2)/(r1+r2+rl+rx+rn) must be smaller than VREF2, so the fifth comparator AMP5 outputs a high level, outputs a low level OUT to the timer after passing through the inverter, and the signal out_en output by the timer is still at a low level.
It is noted that the circuit shown in fig. 6 can also implement the invention based on different variants. In particular, the modification may be performed by, for example, increasing or decreasing the inverter, or changing the lock signal to which the switches S1 and S2 are connected.
In different example circuits, the signal EN1 and the signal EN2 are used as the locking signals, the MOS transistor NM3 is still connected to the signal EN1, and the MOS transistor NM4 is connected to the signal EN2; for the ac detection circuit a, the sampling voltage VL1 on the L line is greater than VREF1, the signal EN1 changes from high level to low level, the signal EN2 remains high level, the switch S1 is kept open based on the signal EN1, the switch S2 is closed based on the signal EN2, and the current direction of the power outage detection is from the first detection end to the second detection end, i.e. from the L line to the N line. For the ac detection circuit B, the N-line up-sampling voltage VN1 is greater than VREF1, the signal EN2 changes from high to low, the signal EN1 is kept high, the switch S1 is closed based on the signal EN1, the switch S2 is opened based on the signal EN2, and the current direction of the power outage detection is from the second detection end to the first detection end, i.e. from the L line to the N line. The rest of the similarities may refer to the previous embodiments and are not repeated here.
Based on the same inventive concept, the embodiment of the invention also discloses a chip, as shown in fig. 7, which comprises the ac detection circuit according to the embodiment of the invention.
Based on the same inventive concept, the embodiment of the invention also discloses an emergency lighting system, as shown in fig. 8, comprising a load and a chip according to the embodiment of the invention, wherein the chip is connected with the load. Wherein the load can be selected as a lighting device such as an LED.
When the emergency lighting system of the embodiment of the invention is connected to the alternating current power grid, whether two emergency lighting systems are connected to the alternating current power grid in a mixed connection mode or not, for each emergency lighting system, the judged power failure detection direction is from a live wire to a zero wire, so that all the emergency lighting systems connected in parallel to the alternating current power grid can be ensured not to interfere with each other, and the power failure detection results of the alternating current power grid are consistent. In other words, by adopting the emergency lighting system, a plurality of emergency lighting systems can be directly connected in parallel to an alternating current power grid, and the problem of whether zero lines and live lines are connected in a mixed mode is not required to be considered, namely, the zero lines and the live lines are not required to be strictly distinguished.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. The descriptions of "first" and "second" are used only to distinguish between different descriptive objects and should not be construed as having a sequential or equivalent meaning.
The foregoing has outlined rather broadly the more detailed description of the present application, and the detailed description of the principles and embodiments herein may be better understood as being a limitation on the present application. Also, various modifications in the details and application scope may be made by those skilled in the art in light of this disclosure, and all such modifications and variations are not required to be exhaustive or are intended to be within the scope of the disclosure.
Claims (12)
1. The utility model provides an exchange detection circuit, its characterized in that includes first detection end, second detection end, exchanges synchronous judgement module, digital logic module and outage detection module, first detection end with the second detection end is used for switching in the AC power grid respectively, wherein:
the alternating current synchronous judging module is used for judging that the voltage which is larger than the reference voltage VREF1 for the first time is the first detection terminal voltage or the second detection terminal voltage after the alternating current is electrified, and outputting a judging logic signal;
the digital logic module is used for generating a locking signal when the judging logic signal is effective and locking the judging logic signal based on the locking signal;
The power failure detection module is used for controlling the current direction of power failure detection to flow out from the high-voltage end of the first detection end and the second detection end according to the locking signal, and flows into the low-voltage end of the first detection end and the second detection end after passing through the alternating current power grid.
2. The AC detection circuit of claim 1, wherein,
if the voltage which is larger than the reference voltage VREF1 for the first time is the voltage of the first detection end, the first detection end is connected with a live wire of an alternating current power grid, and the second detection end is connected with a zero line of the alternating current power grid;
if the voltage larger than the reference voltage VREF1 is the voltage of the second detection end for the first time, the second detection end is connected with the live wire of the alternating current power grid, and the first detection end is connected with the zero line of the alternating current power grid.
3. The AC detection circuit of claim 1, wherein,
the alternating current synchronous judging module comprises:
the first comparison submodule is used for comparing a sampling voltage VL1 used for representing the voltage of the first detection end with a reference voltage VREF1 after the alternating current power is on, and outputting a first logic signal;
the second comparison sub-module is used for comparing a sampling voltage VN1 used for representing the voltage of the second detection end with a reference voltage VREF1 after the alternating current power is on, and outputting a second logic signal;
Wherein the judgment logic signal is a combination of the first logic signal and the second logic signal; when the first logic signal and the second logic signal are both at a low level, the judgment logic signal is invalid; when the first logic signal and the second logic signal are at opposite levels, the judgment logic signal is valid.
4. The AC detection circuit as claimed in claim 3, wherein,
the digital logic module includes: a first logic sub-module and a second logic sub-module having the same circuit structure;
the first logic sub-module has a first input terminal connected to the first logic signal, a second input terminal connected to the signal EN2, a third input terminal connected to the signal EN1, and an output terminal outputting the signal EN1 or an inverted signal EN1B of the signal EN 1;
the first input end of the second logic sub-module is connected with the second logic signal, the second input end of the second logic sub-module is connected with the signal EN1, the third input end of the second logic sub-module is connected with the signal EN2, and the output end of the second logic sub-module outputs the signal EN2 or an inverted signal EN2B of the signal EN 2;
wherein, the signal EN1 and the signal EN2 have the same level at the initial moment of power-on of the alternating current network;
when the judging logic signal is valid, taking a signal EN1 output by the first logic sub-module and a signal EN2 output by the second logic sub-module as the locking signals; or, the inverted signal EN1B output by the first logic sub-module and the inverted signal EN2B output by the second logic sub-module are used as the locking signals.
5. The AC detection circuit as claimed in claim 4, wherein,
the digital logic module further comprises a power-on reset sub-module which is respectively connected with the first logic sub-module and the second logic sub-module, and the power-on reset sub-module is used for outputting a power-on reset signal;
the first logic sub-module and the second logic sub-module each further comprise a fourth input end, and the fourth input ends are used for being connected with the power-on reset signal;
under the condition that the power-on reset signal is effective and the judging logic signal is effective, taking a signal EN1 output by the first logic submodule and a signal EN2 output by the second logic submodule as the locking signals; or, the inverted signal EN1B output by the first logic sub-module and the inverted signal EN2B output by the second logic sub-module are used as the locking signals.
6. The ac detection circuit of any one of claims 2-5, wherein the power outage detection module comprises: selecting a sub-module, a first clamping sub-module, a second clamping sub-module and a power failure judging sub-module;
the selection submodule is used for controlling the current direction of power failure detection to be from a first detection end to a second detection end or from the second detection end to the first detection end according to the received locking signal, and outputting a power failure detection voltage to the power failure judgment submodule;
The power failure judging submodule is used for comparing the power failure detection voltage with a reference voltage VREF2 and outputting an indication signal representing power failure of the alternating current power grid under the condition that the power failure detection voltage is larger than the reference voltage VREF2 and lasts for a preset period of time; wherein, the reference voltage VREF2 is smaller than the reference voltage VREF1;
the first clamping submodule is connected with the first detection end and the selection submodule, and the second clamping submodule is connected with the second detection end and the selection submodule; if the current direction of the power failure detection is controlled to be from a first detection end to a second detection end by the selection submodule, the first clamping submodule clamps the voltage of the first detection end to the reference voltage VREF1, and the second clamping submodule generates the power failure detection voltage based on the voltage of the first detection end and the equivalent impedance of an alternating current power grid between the first detection end and the second detection end; if the current direction of the power failure detection is controlled by the selection submodule to be from the second detection end to the first detection end, the second clamping submodule clamps the voltage of the second detection end to the reference voltage VREF1, and the first clamping submodule generates the power failure detection voltage based on the voltage of the second detection end and the equivalent impedance of an alternating current power grid between the first detection end and the second detection end.
7. The AC detection circuit of claim 6, wherein,
the selection submodule comprises a first switch and a second switch;
the first clamping submodule comprises a third comparator, a first MOS tube, a third MOS tube and a first resistor;
one input end of the third comparator is connected with a reference voltage VREF1, the second input end of the third comparator is connected with a first detection end voltage, the output end of the third comparator is connected with the gate end of the first MOS tube and the drain end of the third MOS tube, the source end and the drain end of the first MOS tube are connected between a power supply voltage VDD and the first resistor, and the first resistor is grounded; the gate end of the third MOS tube is connected with the locking signal or the reverse signal of the locking signal, and the source end of the third MOS tube is grounded; one end of the first switch is connected between the first MOS tube and the first resistor, and the other end of the first switch is connected with the power failure judging submodule;
the second clamping submodule comprises a fourth comparator, a second MOS tube, a fourth MOS tube and a second resistor;
one input end of the fourth comparator is connected with a reference voltage VREF1, the second input end of the fourth comparator is connected with a second detection end voltage, the output end of the fourth comparator is connected with the gate end of the second MOS tube and the drain end of the fourth MOS tube, the source end and the drain end of the second MOS tube are connected between a power supply voltage VDD and the second resistor, and the second resistor is grounded; the gate end of the fourth MOS tube is connected with the locking signal or the reverse signal of the locking signal, and the source end of the fourth MOS tube is grounded; one end of the second switch is connected between the second MOS tube and the second resistor, and the other end of the second switch is connected with the power failure judging submodule.
8. The AC detection circuit of claim 6, wherein,
the power failure judging submodule comprises: a fifth comparator, an inverter and a timer,
the non-inverting input end of the fifth comparator is connected with the reference voltage VREF2, the inverting input end of the fifth comparator is connected with the power failure detection voltage, the output end of the fifth comparator is connected with the timer through the inverter, and the output end of the timer is the output end of the power failure judging sub-module.
9. The AC detection circuit as claimed in claim 5, wherein,
the first logic submodule comprises an AND gate Y1, a NAND gate Y2 and a NAND gate Y3,
the first input end of the AND gate Y1 is connected with the first logic signal through an inverter, and the second input end of the AND gate Y1 is connected with a signal EN2; the first input end of the NAND gate Y2 is connected with the output end of the AND gate Y1, and the second input end of the NAND gate Y2 is connected with a signal EN1; the first input end of the NAND gate Y3 is connected with the output end of the NAND gate Y2, the second input end of the NAND gate Y2 is connected with the signal EN2, the third input end of the NAND gate Y3 is connected with the power-on reset signal, and the output end of the NAND gate Y3 outputs the signal EN1 or outputs EN1B after passing through an inverter;
the second logic submodule comprises an AND gate Y4, a NAND gate Y5 and a NAND gate Y6,
the first input end of the AND gate Y4 is connected with the second logic signal through an inverter, and the second input end is connected with a signal EN1; the first input end of the NAND gate Y5 is connected with the output end of the AND gate Y4, and the second input end of the NAND gate Y5 is connected with a signal EN2; the first input end of the NAND gate Y6 is connected with the output end of the NAND gate Y5, the second input end of the NAND gate Y5 is connected with the signal EN1, the third input end of the NAND gate Y6 is connected with the power-on reset signal, and the output end of the NAND gate Y6 outputs the signal EN2 or outputs EN2B after passing through an inverter.
10. The alternating current detection circuit according to claim 1, further comprising a driving module and a load switch, wherein one end of the load switch is connected with a power supply of the alternating current detection circuit, and the other end of the load switch is used for connecting a load;
the driving module is connected between the power failure detection module and the load switch, and drives the load switch to conduct the power supply with the load based on the indication signal which is output by the power failure detection module and represents the power failure of the alternating current power grid.
11. A chip comprising an ac detection circuit as claimed in any one of claims 1 to 10.
12. An emergency lighting system comprising a load and the chip of claim 11, the chip being coupled to the load.
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| WO2022062776A1 (en) * | 2020-09-28 | 2022-03-31 | 上海南麟电子股份有限公司 | Alternating current resistance detection circuit and system |
| CN218868412U (en) * | 2023-01-09 | 2023-04-14 | 江西量一光电科技有限公司 | LED emergency dimming circuit with multiple parallel lamps and no LN line |
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| CN116256588B (en) | 2023-08-01 |
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