CN116248144A

CN116248144A - Communication equipment, communication equipment performance tuning method and device

Info

Publication number: CN116248144A
Application number: CN202211730835.3A
Authority: CN
Inventors: 郭希蕊; 张涛; 王东洋; 马艳君; 李福昌
Original assignee: China United Network Communications Group Co Ltd
Current assignee: China United Network Communications Group Co Ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-06-09

Abstract

The application provides communication equipment, a communication equipment performance tuning method and a communication equipment performance tuning device, which relate to the field of communication and are used for solving the problem that pRRU of a domestic device existing in the current stage cannot meet the performance requirements of operators, wherein the communication equipment comprises: the system comprises a field programmable gate array FPGA module, a transceiver module and a radio frequency subsystem module; the FPGA module is used for receiving the first downlink digital signal; decompressing and filtering the first downlink digital signal to obtain a second downlink digital signal; the transceiver module is used for receiving the downlink digital signal sent by the FPGA module; converting the second downlink digital signal to obtain a downlink analog signal; the radio frequency subsystem module is used for receiving the downlink analog signals sent by the transceiver module; performing power amplification treatment on the downlink analog signals to obtain downlink analog signals after power amplification; and transmitting the downlink analog signal with amplified power to the radio frequency antenna. The method is used for pRRU performance tuning.

Description

Communication equipment, communication equipment performance tuning method and device

Technical Field

The present disclosure relates to the field of communications, and in particular, to a communications device, and a performance tuning method and apparatus for the communications device.

Background

In the current background of Zhongmei trade war, operators need to promote autonomous controllability of network equipment hardware, and home-made core components are introduced to avoid risks.

At present, the technology of the domestic chip is still immature, and in the field of transceiver chips, the domestic dual-purpose transceiver chip can only support a single-transmission single-reception 1T1R mode of 100MHz NR by adopting a low-voltage differential signaling (low-voltage differenti al signaling, LVDS) interface, and can meet the requirements of operators only by adopting equipment with 2 transceiver chips combined into double-transmission double-reception 2T 2R. And 2 transducer chips have the problem of relatively high interface delay and synchronization difficulty. Meanwhile, the sensitivity and stability of the domestic device are insufficient, tuning is needed, and the requirements of a pico-remote radio unit (pRRU) radio remote unit of a pico base station are met.

Disclosure of Invention

The application provides communication equipment, a communication equipment performance tuning method and a communication equipment performance tuning device, which can perform performance tuning on pRRU using domestic devices, so that the pRRU using the domestic devices can meet the performance requirements of operators.

In order to achieve the above purpose, the present application adopts the following technical scheme:

in a first aspect, the present application provides a communication device comprising: the system comprises a field programmable gate array FPGA module, a transceiver module and a radio frequency subsystem module; the FPGA module is used for receiving the first downlink digital signal; decompressing and filtering the first downlink digital signal to obtain a second downlink digital signal; a second downstream digital signal to the transceiver module; the transceiver module is used for receiving the downlink digital signal sent by the FPGA module; converting the second downlink digital signal to obtain a downlink analog signal; transmitting a downlink analog signal to the radio frequency subsystem module; the radio frequency subsystem module is used for receiving the downlink analog signals sent by the transceiver module; performing power amplification treatment on the downlink analog signals to obtain downlink analog signals after power amplification; and transmitting the downlink analog signal with amplified power to the radio frequency antenna.

With reference to the first aspect, in one possible implementation manner, the FPGA module includes: the system comprises a CP RI interface module, a compression decompression module and a digital filter module; the CPRI interface module is used for receiving a first downlink digital signal; the compression and decompression module is used for carrying out decompression processing on the first downlink digital signal to obtain a decompressed first downlink digital signal; and the digital filter module is used for carrying out filtering processing on the decompressed first downlink digital signal to obtain a second downlink digital signal.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: and controlling the CPRI interface module to receive the first downlink digital signal according to the CPRIIP of the open source.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: and controlling the compression and decompression module to decompress the first downlink digital signal according to a preset DC algorithm.

With reference to the first aspect, in one possible implementation manner, the digital filter module performs a filtering process by using a frequency response mask FRM digital filter.

With reference to the first aspect, in one possible implementation manner, the second downlink digital signal includes a third downlink digital signal and a fourth downlink digital signal, the downlink analog signal includes a first downlink analog sub-signal and a second downlink analog sub-signal, and the transceiver module includes a first transceiver and a second transceiver; the wiring connection between the FPGA module and the first transceiver is axisymmetric with the wiring connection between the FPGA module and the second transceiver; the first transceiver is used for converting the third downlink digital signal to obtain a first downlink analog sub-signal; and the second transceiver is used for converting the fourth downlink digital signal to obtain a second downlink analog sub-signal.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: transmitting a third downstream digital signal to the first transceiver; transmitting a fourth downstream digital signal to the second transceiver; and carrying out data alignment processing on the third downlink digital signal and the fourth downlink digital signal according to a first preset algorithm.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: optimizing interface timing between the FPGA module and the first transceiver; the interface timing between the FPGA module and the second transceiver is optimized.

With reference to the first aspect, in one possible implementation manner, the FPGA module includes at least one first functional pin corresponding to the first transceiver and at least one second functional pin corresponding to the second transceiver; the first functional pins and the second functional pins are the same in number, and the first functional pins and the second functional pins are symmetrically distributed inside the FPGA module.

With reference to the first aspect, in one possible implementation manner, the transceiver module includes: a plurality of QEC calibration modules, a plurality of DC calibration modules; the first transceiver comprises at least one QEC calibration module and at least one DC calibration module, and the second transceiver comprises at least one QEC calibration module and at least one DC calibration module; the QEC calibration module is used for carrying out QEC calibration on the downlink analog signals; and the DC calibration module is used for carrying out DC calibration on the downlink analog signals.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: according to a preset QEC calibration algorithm, controlling a QEC calibration module to perform QEC calibration on the downlink analog signal; and controlling the DC calibration module to perform DC calibration on the downlink analog signals according to a preset DC calibration algorithm.

With reference to the first aspect, in one possible implementation manner, the radio frequency subsystem module includes: a power amplifier PA module; and the PA module is used for carrying out power amplification processing on the downlink analog signals to obtain the downlink analog signals after power amplification.

With reference to the first aspect, in one possible implementation manner, the FPGA module is specifically configured to: and controlling the output power of the PA module according to a preset grid voltage control algorithm.

With reference to the first aspect, in one possible implementation manner, the communication device further includes: a clock module; and the clock module is used for guaranteeing clock alignment during signal interaction among the FPGA module, the first transceiver and the second transceiver.

Based on the technical scheme, the communication equipment provided by the application can receive downlink digital signals from communication equipment adopting other main stream manufacturer devices based on the CPRI interface in the downlink transmission process, and decompress and filter the downlink digital signals; meanwhile, a dual transceiver chip is adopted in the communication equipment to realize a 2T2R mode, and the downlink analog signal is calibrated while the downlink digital signal is converted into the downlink analog signal; finally, the power amplifier in the radio frequency subsystem amplifies the downlink analog signal and sends the amplified signal to the radio frequency antenna to be sent out by the radio frequency in the sky. Therefore, when the communication equipment in the application is in downlink transmission, a 2T2R mode can be realized, high bandwidth requirements are realized through a low-rate interface, and meanwhile, the downlink signals are subjected to filtering, calibration, power amplification and other processes, so that the performance of the communication equipment is improved, and the performance requirements of a communication operator on the communication equipment are met.

In a second aspect, the present application provides a communication device comprising: the system comprises an FPGA module, a transceiver module and a radio frequency subsystem module; the radio frequency subsystem module is used for receiving the uplink analog signals sent by the radio frequency antenna; transmitting an upstream analog signal to a transceiver module; the transceiver module is used for receiving the uplink analog signals sent by the radio frequency subsystem module; converting the uplink analog signal to obtain a first uplink digital signal; sending a first uplink digital signal to an FPGA module; the FPGA module is used for receiving the first uplink digital signal sent by the transceiver module; filtering and compressing the first uplink digital signal to obtain a second uplink digital signal; and sending a second uplink digital signal to the upper-level equipment.

With reference to the second aspect, in one possible implementation manner, the FPGA module includes: CPRI interface module, compression decompression module, digital filter module; and the digital filter module is used for carrying out filtering processing on the first uplink digital signal to obtain a filtered first uplink digital signal. The compression and decompression module is used for decompressing the filtered first uplink digital signal to obtain a second uplink digital signal; and the CPRI interface module is used for sending the second uplink digital signal.

With reference to the second aspect, in one possible implementation manner, the FPGA module is specifically configured to: and controlling the CPRI interface module to send a second uplink digital signal according to the CPRIIP of the open source.

With reference to the second aspect, in one possible implementation manner, the FPGA module is specifically configured to: and controlling the compression and decompression module to decompress the filtered first uplink digital signal according to a preset DC algorithm.

With reference to the second aspect, in one possible implementation manner, the digital filter module performs a filtering process with a FRM digital filter.

With reference to the second aspect, in one possible implementation manner, the uplink analog signal includes a first uplink analog sub-signal and a second uplink analog sub-signal, the first uplink digital signal includes a third uplink digital signal and a fourth uplink digital signal, and the transceiver module includes a first transceiver and a second transceiver; the wiring connection between the FPGA module and the first transceiver is axisymmetric with the wiring connection between the FPGA module and the second transceiver; the first transceiver is used for converting the first uplink analog sub-signal to obtain a third uplink digital signal; and the second transceiver is used for converting the second uplink analog sub-signal to obtain a fourth uplink digital signal.

With reference to the second aspect, in one possible implementation manner, the FPGA module is specifically configured to: receiving a third uplink digital signal sent by the first transceiver; receiving a fourth uplink digital signal sent by the second transceiver; and carrying out data alignment processing on the third uplink digital signal and the fourth uplink digital signal according to a first preset algorithm.

With reference to the second aspect, in one possible implementation manner, the FPGA module is specifically configured to: optimizing interface timing between the FPGA module and the first transceiver; the interface timing between the FPGA module and the second transceiver is optimized.

With reference to the second aspect, in one possible implementation manner, the FPGA module includes at least one first functional pin corresponding to the first transceiver and at least one second functional pin corresponding to the second transceiver; the first functional pins and the second functional pins are the same in number, and the first functional pins and the second functional pins are symmetrically distributed inside the FPGA module.

With reference to the second aspect, in one possible implementation manner, the transceiver module includes: a plurality of QEC calibration modules, a plurality of DC calibration modules; the first transceiver comprises at least one QEC calibration module and at least one DC calibration module, and the second transceiver comprises at least one QEC calibration module and at least one DC calibration module; the QEC calibration module is used for carrying out QEC calibration on the first uplink digital signal; and the DC calibration module is used for carrying out DC calibration on the first uplink digital signal.

With reference to the second aspect, in one possible implementation manner, the FPGA module is specifically configured to: according to a preset QEC calibration algorithm, controlling a QEC calibration module to perform QEC calibration on the first uplink digital signal; and controlling the DC calibration module to perform DC calibration on the first uplink digital signal according to a preset DC calibration algorithm.

With reference to the second aspect, in one possible implementation manner, the communication device further includes: a clock module; and the clock module is used for guaranteeing clock alignment during signal interaction among the FPGA module, the first transceiver and the second transceiver.

Based on the technical scheme, in the uplink transmission process, the communication equipment provided by the application can send the uplink analog signal to the radio frequency subsystem after the radio frequency antenna receives the uplink analog signal, and the radio frequency subsystem sends the uplink analog signal to the transceiver module which adopts the dual transceiver chip to realize the 2T2R mode; then, the transceiver module converts the uplink analog signal into an uplink digital signal, and the communication equipment also calibrates the uplink analog signal because the communication equipment adopts a double transceiver chip to realize a 2T2R mode; finally, the communication device performs filtering and compression processing on the downlink digital signal, and sends an uplink digital signal to an upper-level communication device of the communication device based on the CPRI interface. Therefore, when the communication equipment in the application transmits uplink, the 2T2R mode can be realized, the high bandwidth requirement is realized through the low-rate interface, and meanwhile, the uplink signals are subjected to the processes of filtering, calibration, compression and the like, so that the performance of the communication equipment is improved, and the performance requirement of a communication operator on the communication equipment is met.

In a third aspect, the present application provides a method for tuning performance of a communication device, the method including: receiving a first downlink digital signal and generating a second downlink digital signal according to the first downlink digital signal; converting the second downlink digital signal to obtain a downlink analog signal; performing power amplification processing on the downlink analog signals to obtain downlink analog signals after power amplification; and transmitting the downlink analog signal after power amplification to a radio frequency antenna.

In a fourth aspect, the present application provides a method for tuning performance of a communication device, the method including: receiving an uplink analog signal; converting the uplink analog signal to obtain a first uplink digital signal; filtering and compressing the first uplink digital signal to obtain a second uplink digital signal; and sending the second uplink digital signal to the upper-level equipment.

In a fifth aspect, the present application provides a communication device performance tuning apparatus, the apparatus comprising: and the communication unit is used for receiving the first downlink digital signal. And the processing unit is used for generating a second downlink digital signal according to the first downlink digital signal. And the processing unit is also used for converting the second downlink digital signal to obtain a downlink analog signal. And the processing unit is also used for carrying out power amplification processing on the downlink analog signals to obtain the downlink analog signals after power amplification. And the communication unit is also used for transmitting the downlink analog signals after power amplification to the radio frequency antenna.

In a sixth aspect, the present application provides a communications device performance tuning apparatus, the apparatus comprising: and the communication unit is used for receiving the uplink analog signals. And the processing unit is used for converting the uplink analog signals to obtain first uplink digital signals. And the processing unit is also used for filtering and compressing the first uplink digital signal to obtain a second uplink digital signal. And the communication unit is also used for sending a second uplink digital signal to the upper-level equipment.

In a seventh aspect, the present application provides a communication device, the apparatus comprising: a processor and a communication interface; the communication interface is coupled to a processor for executing a computer program or instructions to implement the communication device performance tuning method as described in the third or fourth aspect.

In an eighth aspect, the present application provides a computer-readable storage medium having instructions stored therein that, when run on a terminal, cause the terminal to perform a communication device performance tuning method as described in the third or fourth aspect.

In a ninth aspect, the present application provides a computer program product comprising instructions which, when run on a communication device, cause the communication device to perform a communication device performance tuning method as described in the third or fourth aspect.

In a tenth aspect, the present application provides a chip comprising a processor and a communications interface, the communications interface and the processor being coupled, the processor being for running a computer program or instructions to implement a communications device performance tuning method as described in the third or fourth aspect.

In particular, the chip provided in the present application further includes a memory for storing a computer program or instructions.

It should be noted that the above-mentioned computer instructions may be stored in whole or in part on a computer-readable storage medium. The computer readable storage medium may be packaged together with the processor of the apparatus or may be packaged separately from the processor of the apparatus, which is not limited in this application.

The description of the second aspect to the tenth aspect in the present application may refer to the detailed description of the first aspect; also, the advantageous effects described in the second aspect to the tenth aspect may refer to the advantageous effect analysis of the first aspect, and are not described here again.

In this application, the names of the above communication devices do not constitute limitations on the devices or function modules themselves, and in actual implementation, these devices or function modules may appear under other names. Insofar as the function of each device or function module is similar to the present application, it is within the scope of the claims of the present application and the equivalents thereof.

These and other aspects of the present application will be more readily apparent from the following description.

Drawings

Fig. 1 is a schematic architecture diagram of a communication device according to an embodiment of the present application;

fig. 2 is a schematic architecture diagram of another communication device according to an embodiment of the present application;

fig. 3 is a schematic architecture diagram of another communication device according to an embodiment of the present application;

fig. 4 is a schematic circuit diagram of an internal part of a communication device according to an embodiment of the present application;

fig. 5 is a schematic layout diagram of the inside of a communication device according to an embodiment of the present application;

fig. 6 is a schematic architecture diagram of another communication device according to an embodiment of the present application;

fig. 7 is a schematic diagram of signal calibration performed by a communication device according to an embodiment of the present application;

fig. 8 is a schematic architecture diagram of another communication device according to an embodiment of the present application;

fig. 9 is a schematic flow chart of a method for optimizing performance of a communication device according to an embodiment of the present application;

fig. 10 is a flowchart of another method for optimizing performance of a communication device according to an embodiment of the present application;

fig. 11 is a schematic architecture diagram of a performance tuning device for a communication device according to an embodiment of the present application;

fig. 12 is a schematic architecture diagram of another performance tuning apparatus for a communication device according to an embodiment of the present application;

Fig. 13 is a schematic architecture diagram of another performance tuning apparatus for a communication device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.

The terms "first" and "second" and the like in the description and in the drawings are used for distinguishing between different objects or for distinguishing between different processes of the same object and not for describing a particular sequential order of objects.

Furthermore, references to the terms "comprising" and "having" and any variations thereof in the description of the present application are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed but may optionally include other steps or elements not listed or inherent to such process, method, article, or apparatus.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more.

1. Pico base station (pico site)

A pico station, also called pico station for short. Skin is referred to mathematically as parts per million, which is a small unit. Thus, a pico base station is a base station that is smaller than a micro base station.

Typically, the pico base station has a transmit power between 0.1 watts and 0.5 watts and a coverage radius between 20 meters and 50 meters. For example, a pico-cell installed in a home is typically artificially limited to below 0.1 watts and coverage of 20 meters.

2. Pi base station remote radio unit (pico remote radio unit pRRU)

The remote radio unit (remote radio unit, RRU) is one of the core components of the base station. The RRU is divided into a near-end machine (Radio Server, RS) and a far-end machine (Radio remote control (RRU)), which are connected by optical fibers, and the interface is based on an open CPRI or IR interface, so that the RRU can be stably connected with equipment of a main stream manufacturer.

The RS can be installed at a proper machine room position, the RRU is installed at an antenna end, so that a part of a previous base station module is separated, the troublesome maintenance work can be simplified to the RS end by separating the RS from the RRU, and one RS can be connected with a plurality of RRUs, thereby saving the space, reducing the setting cost and improving the networking efficiency. Meanwhile, an interface between the two connectors is made of optical fibers, so that the loss is low.

In the application, the RRU and the tuning method of the pico-cell using the domestic device are improved.

3. Field programmable gate array (field programmable gate array, FPGA)

FPGA is a semi-custom circuit in the field of application specific integrated circuits, and is a product of further development on the basis of programmable devices such as programmable array logic, general array logic and the like. The FPGA solves the defects of a custom circuit and the defect of limited gate circuit number of the original programmable device.

FPGA design is not a simple chip study, and mainly uses the modes of FPGAs to design products in other industries.

Compared with the chip design in the traditional mode, the FPGA chip is not limited to the research and design chip, but can be optimally designed by means of a specific chip model for products in more fields.

From the chip device perspective, the FPGA itself constitutes a typical integrated circuit in a semi-custom circuit, which contains a digital management module, embedded units, output units, input units, and the like. On the basis, the FPGA chip is necessary to look at comprehensive chip optimization design comprehensively by changing

And a brand new chip function is added to the current chip design, so that the simplification 5 and the performance improvement of the whole chip structure are realized.

The FPGA has wide application in the communication industry and is generally used in RRU equipment.

In the application, the FPGA is used as a control core of the pRRU and is used for controlling the performance tuning of the pRRU based on various stored algorithms.

4. Transceiver0 a transceiver is a radio transmitter and receiver mounted on a component and sharing a portion of the same circuitry.

The transceiver chip produced by the domestic manufacturer at the present stage can only support a single-emission single-reception (1T 1R) mode of 100MHz NR due to the limitation of a low-voltage differential signaling (low-voltage differential signaling, LVDS) interface. In order to meet the requirements of the communication carrier on the pRRU, 5, two transceiver chips are required to be combined to form a device in a dual-transmission dual-reception (2T 2R) mode.

However, two transceiver chips are combined to form a device with a dual-transmission and dual-reception (2T 2R) mode, and the problems of interface delay and high synchronization difficulty are caused. Meanwhile, the sensitivity and stability of the domestic transducer chip are insufficient, and tuning is needed to meet the requirements of pRRU.

The technical terms related to the present application are explained above.

At the 0 th stage, under the background of the current Zhongmei trade war, operators need to improve the autonomous controllability of network equipment hardware, and home-made core components are introduced to avoid risks.

In combination with the description of technical terms in the application, it can be known that the technology of the domestic chip is still immature, and in the field of transceiver chips, the domestic transceiver chip is used for adopting

With low-voltage differential signaling (low-voltage differential signaling, LVDS) interface, only 5 can support single-transmission single-receiving 1T1R mode of 100MHz NR, and can meet the requirements of operators by adopting 2 transceiver chips to combine into double-transmission double-receiving 2T2R equipment. And 2 transducer chips have the problem of relatively high interface delay and synchronization difficulty. Meanwhile, the sensitivity and stability of the domestic device are insufficient, tuning is needed, and the requirement of a pico-remote radio unit (pRRU) of a pico-base station is met.

0 in order to solve the problem that pRRU of domestic devices in the prior art cannot meet performance requirements of operators, the application provides communication equipment, which adopts unique wiring design and various algorithms to perform good conversion, amplification, filtering and other optimization treatments on uplink analog signals or downlink digital signals, and realizes performance tuning of pRRU adopting domestic devices.

The following describes embodiments of the present application in detail with reference to the drawings.

Fig. 1 is a schematic architecture diagram of a communication device 10 according to an embodiment of the present application. The communication device 10 is configured to implement pRRU functions, and specifically includes: a field programmable gate array FPGA module 11, a transceiver module 12, a radio frequency subsystem module 13, and a radio frequency antenna 14.

The FPGA module 11 is connected to the transceiver module 12, and is configured to compress, decompress, and filter the digital signals after receiving the digital signals, and send the digital signals to corresponding devices or modules according to uplink or downlink types of the digital signals.

Illustratively, as shown in fig. 2, the FPGA module 11 in the present application may include the following three sub-modules: a common public radio interface (Common Public Radio Interface, CPRI) module 111, a compression decompression module 112, a digital filter module 113.

Optionally, the CPRI interface module 111 is configured to receive a downlink digital signal from an upper device of the pRRU and send an uplink digital signal to the upper device of the pRRU.

Optionally, the compression and decompression module 112 is configured to compress or decompress the digital signal. Specifically, when the digital signal is a downlink digital signal, the compression and decompression module 112 decompresses the digital signal; when the digital signal is an uplink digital signal, the compression and decompression module 112 performs compression processing on the digital signal.

Optionally, the digital filter module 113 is configured to perform filtering processing on the digital signal.

The sub-modules that the FPGA module 11 may include are described above.

The use of the transceiver module 11, and one possible architecture, is described below:

the transceiver module 12 is configured to convert the received signal. Further, when the transceiver module 12 receives a downlink digital signal sent by the FPGA module 11, the transceiver module 12 converts the digital signal into an analog signal and sends the analog signal to the rf subsystem module 13; similarly, when the transceiver module 12 receives an uplink analog signal sent by the rf subsystem module 13, the transceiver module 12 converts the analog signal into a digital signal and sends the digital signal to the FPGA module 11.

Optionally, the transceiver module 12 is further configured to calibrate the received digital or analog signal. For example, transceiver module 12 specifically performs QEC calibration and DC calibration on a received digital signal or analog signal.

Illustratively, as shown in fig. 3, since pRRU of the present application is in 2T2R mode, transceiver module 12 includes two transceivers: the first transceiver 121, the second transceiver 122, and to implement the signal calibration function, the transceiver module 12 further includes: QEC calibration module 123, DC calibration module 124.

Alternatively, the first transceiver 121 and the second transceiver 122 may be implemented as a transceiver chip as described in the introduction.

Illustratively, taking the implementation of the first transceiver 121 and the second transceiver 122 as transceiver chips as shown in fig. 4, fig. 4 is a schematic circuit diagram between two transceiver chips inside the communication device 10 provided in the present application.

In one possible implementation, as shown in fig. 5, fig. 5 is a circuit wiring diagram between the FPGA module 11 and the first transceiver 121 and the second transceiver 122. As can be seen from fig. 5, the wiring connection between the FPGA module 11 and the first transceiver 121 is axisymmetric with the wiring connection between the FPGA module 11 and the second transceiver 122.

It can be understood that, since the first transceiver 121 and the second transceiver 122 are transceiver chips, and the chips use LVDS interfaces, the wiring method shown in fig. 5 is used to ensure that two signals sent from the transceiver module 11 to the FPGA module 11 are aligned.

Specifically, the first transceiver 121 cooperates with the second transceiver 122 to jointly convert between digital signals and analog signals. For example, when the transceiver module 12 receives a downlink digital signal sent by the FPGA module 11, the first transceiver 121 and the second transceiver 122 can process a part of conversion work of the digital signal, respectively, so as to convert the downlink digital signal into a downlink analog signal; similarly, when the transceiver module 12 receives an uplink analog signal sent by the rf subsystem module 13, the first transceiver 121 and the second transceiver 122 can process a part of the conversion operation of the analog signal, so as to convert the uplink analog signal into a downlink digital signal.

Alternatively, the QEC calibration module 123 and the DC calibration module 124 can perform QEC calibration and DC calibration on the signals under the control of the FPGA module 11. For example, the FPGA module 11 is built with a corresponding QEC algorithm to calibrate the analog signal or the digital signal. It should be noted that, the flow of the FPGA module 11 controlling the QEC calibration module 123 and the DC calibration module 124 to calibrate the analog signal or the digital signal is referred to the embodiments described in detail below in conjunction with the uplink and the downlink, and will not be described herein.

One possible architecture for transceiver module 11 is described above.

The following describes the use of the rf subsystem module 13, and the sub-modules that it may comprise:

the rf subsystem module 13 is configured to send the received analog signal to other corresponding modules. Specifically, when the rf subsystem module 13 receives a downlink analog signal sent by the transceiver module 12, the rf subsystem module 13 sends the downlink analog signal to the rf wire 14, so that the rf antenna 14 sends the analog signal out; similarly, when the rf subsystem module 13 receives an uplink analog signal sent by the rf antenna 14, the rf subsystem module 13 sends the uplink analog signal to the transceiver module 12.

Optionally, after the rf subsystem module 13 receives the downlink analog signal sent by the transceiver module 12, it further performs power amplification processing on the downlink analog signal to obtain a power-amplified downlink analog signal.

Illustratively, as shown in fig. 6, the radio frequency subsystem module 13 may further include a Power Amplifier (PA) module 131.

Optionally, the PA module 131 is configured to perform power amplification processing on the downlink analog signal, so as to obtain a downlink analog signal after power amplification.

The description above describes sub-modules that may be included in the radio frequency sub-system module 13.

The following describes the rf antenna 14:

the radio frequency antenna 14 is used for receiving the downlink analog signal sent by the radio frequency subsystem module 13 and sending out the signal; and the uplink analog signal is used for receiving uplink analog signals sent by other radio frequency equipment and sending the uplink analog signals to the radio frequency subsystem module 13.

The architecture of a communication device 10 provided in the embodiments of the present application is described above. The signal transmission process in the present application relates to downlink transmission and uplink transmission.

Specifically, in the downlink transmission process, the FPGA module 11 receives a downlink digital signal sent by an upper device and sends the downlink digital signal to the transceiver module 12, the transceiver module 12 converts the received downlink digital signal into a downlink analog signal and sends the downlink analog signal to the radio frequency subsystem module 13, the radio frequency subsystem module 13 performs power amplification processing on the received downlink analog signal and sends the downlink analog signal to the radio frequency antenna 14, and the radio frequency antenna 14 sends the power-amplified analog signal.

And, in the uplink transmission process, the radio frequency antenna 14 receives uplink analog signals sent by other radio frequency devices and sends the uplink analog signals to the radio frequency subsystem module 13, the radio frequency subsystem module 13 sends the received uplink analog signals to the transceiver module 12, the transceiver module 12 converts the received uplink analog signals into uplink digital signals and sends the uplink digital signals to the FPGA module 11, and the FPGA module 11 sends the received uplink digital signals to the upper-level devices.

The following describes a technical solution provided in the embodiments of the present application with respect to a downlink transmission process:

the FPGA module 11 is configured to receive the first downlink digital signal, decompress and filter the first downlink digital signal, and obtain a second downlink digital signal. Wherein the first downstream digital signal may be from an upstream communication device of the communication device 10.

Optionally, the FPGA module 11 includes a submodule CPRI interface module 111, configured to receive the first downlink digital signal.

Optionally, the FPGA module 11 includes a submodule compression decompression module 112, configured to decompress the first downlink digital signal to obtain a decompressed first downlink digital signal.

Optionally, the FPGA module 11 includes a submodule digital filter module 113, configured to perform filtering processing on the decompressed first downlink digital signal to obtain a second downlink digital signal.

After this, the FPGA module 11 transmits a second downstream digital signal to the transceiver module 12. Accordingly, the transceiver module 12 is configured to receive the second downlink digital signal from the FPGA module 11.

The transceiver module 12 is configured to convert the received second downlink digital signal into a downlink analog signal.

In one possible implementation, the second downstream digital signal includes a third downstream digital signal and a fourth downstream digital signal. At this time, the FPGA module is configured to send a third downlink digital signal to the first transceiver and send a fourth downlink digital signal to the second transceiver.

Correspondingly, the transceiver module 12 includes a first transceiver 121 for converting the third downlink digital signal to obtain a first downlink analog sub-signal; the transceiver module 12 includes a second transceiver 122 for converting the fourth downstream digital signal to obtain a second downstream analog sub-signal.

The transceiver module 12 is further configured to determine a downstream analog signal from the first downstream analog sub-signal and the second downstream analog sub-signal and send the determined downstream analog signal to the rf subsystem module 13. It is understood that the downstream analog signal includes a downstream analog sub-signal and a second downstream analog sub-signal.

Accordingly, the rf subsystem module 13 receives the downstream analog signals from the transceiver module 12.

Optionally, the rf subsystem module 13 includes a submodule PA module 131 configured to perform power amplification processing on the downlink analog signal, so as to obtain a power-amplified downlink analog signal. The rf subsystem module 13 then transmits the power amplified downstream analog signal to the rf cable 14.

Accordingly, the rf antenna 14 receives the amplified downlink analog signal and then transmits the downlink analog signal.

Based on the above technical scheme, in the downlink transmission process, the communication device pRRU provided in the present application can receive downlink digital signals from communication devices adopting other mainstream manufacturer devices based on the CPRI interface, and decompress and filter the downlink digital signals; meanwhile, a dual transceiver chip is adopted in pRRU to realize a 2T2R mode, and the downlink analog signal is calibrated while the downlink digital signal is converted into the downlink analog signal; finally, the power amplifier in the radio frequency subsystem amplifies the downlink analog signal and sends the amplified signal to the radio frequency antenna to be sent out by the radio frequency in the sky. Therefore, when the communication equipment pRRU in the application transmits in the downlink, the 2T2R mode can be realized, the high bandwidth requirement is realized through a low-rate interface, meanwhile, the downlink signals are subjected to filtering, calibration, power amplification and other processing, the performance of the pRRU is improved, and the performance requirement of a communication carrier on the pRRU is met.

The downlink transmission procedure related to the present application is described above.

The following describes a technical solution provided in the embodiments of the present application with respect to an uplink transmission process:

the rf subsystem module 13 is configured to receive the uplink analog signal sent by the rf antenna 14, and send the uplink analog signal to the transceiver module 12.

Correspondingly, the transceiver module 12 receives the uplink analog signal from the rf subsystem module 13 and converts the uplink analog signal to obtain a first uplink digital signal.

In one possible implementation, the upstream analog signal includes a first upstream analog sub-signal and a second upstream analog sub-signal.

Correspondingly, the transceiver module 12 includes a first transceiver 121 configured to convert the first uplink analog sub-5 signal to obtain a third uplink digital signal; the transceiver module 12 includes a second transceiver 122 for converting the second uplink analog sub-signal to obtain a fourth uplink digital signal.

After that, the transceiver module 12 is further configured to determine the first uplink digital signal according to the third uplink digital signal and the fourth uplink digital signal, and send the first uplink digital signal to the FPGA module 11. It is understood that the first upstream digital signal includes a third upstream digital signal and a fourth upstream digital signal.

And 0, the FPGA module 11 is configured to receive the first uplink digital signal from the transceiver module 12, and perform filtering and compression processing on the first uplink digital signal to obtain a second uplink digital signal. After that, the FPGA module 11 transmits a second digital signal to the upper level communication device of the communication device 10.

Optionally, the FPGA module 11 includes a submodule digital filter module 113, configured to perform filtering processing on the 5 th uplink digital signal to obtain a filtered first uplink digital signal.

Optionally, the FPGA module 11 includes a submodule compression decompression module 112, configured to decompress the filtered first uplink digital signal to obtain a second uplink digital signal.

Optionally, the FPGA module 11 includes a submodule CPRI interface module 111, configured to send the second uplink digital signal.

0 based on the above technical solution, in the uplink transmission process of the communication device pRRU provided in the present application, after receiving an uplink analog signal, the radio frequency antenna sends the uplink analog signal to the radio frequency subsystem, and the radio frequency subsystem sends the uplink analog signal to the transceiver module that adopts the dual transceiver chip to realize the 2T2R mode; the transceiver module then converts the uplink analog signal into uplink data

At the same time of word signal, pRRU uses double transmitter chip to implement 2T2R mode, so that pRRU can calibrate said up-line analog signal; finally, the pRRU performs filtering and compression processing on the downlink digital signal, and sends an uplink digital signal to an upstream communication device of the pRRU based on the CPRI interface. Therefore, when the communication device pRRU in the application transmits uplink, the 2T2R mode can be realized, the high bandwidth requirement is realized through a low-rate interface, and uplink signals can be simultaneously processed

And the processing such as filtering, calibration and compression improves the performance of pRRU and meets the performance requirement of a communication carrier on p0 RRU.

The uplink transmission procedure according to the present application is described above.

In the following description, how the CPRI interface module 111 in the communication device 10 specifically performs sending the second uplink digital signal and receiving the first downlink digital signal in the foregoing uplink transmission and downlink transmission processes will be described:

as a possible embodiment, the CPRI interface module 111 adopts a CPRI interface, which is optimized and adjusted according to the open source CPRI IP, to realize the docking with the communication devices of the main stream manufacturer devices such as intel, XILINX, etc. so as to open the interaction between the synchronization plane and the data plane.

Optionally, the FPGA module 11 is further configured to control the CPRI interface module to receive the first downlink digital signal according to the CPRI IP of the open source.

In the uplink and downlink transmission processes, the description is given above on how the CPRI interface module 111 in the communication device 10 specifically transmits the second uplink digital signal and receives the first downlink digital signal.

The following describes how the compression and decompression module 112 in the communication device 10 decompresses the first downlink digital signal and compresses the second uplink digital signal during the foregoing uplink and downlink transmission processes:

in the existing compression and decompression process, the problem that the direct current signal is large and the overall signal transmission performance is affected exists. Accordingly, the present application provides a dc-removing algorithm, and the compression and decompression module 112 in the communication device 10 can ensure that the compressed and decompressed dc signal does not generate a dc signal affecting demodulation after the dc-removing algorithm is adopted.

As a possible embodiment, the specific flow of the dc removal algorithm is as follows:

(1) After forward frequency shift of the baseband data, compressing to a preset bit width to obtain compressed data;

(2) Decompressing the compressed data to obtain decompressed data containing a direct current component, wherein the direct current component is positioned at a zero frequency position of the decompressed data;

(3) Reversely frequency-shifting the zero frequency position of the direct current component to be out of the signal bandwidth of the decompressed data to obtain reverse frequency-shifting data;

(4) And filtering direct current components in the reverse frequency shift data to obtain filtered data.

In a possible implementation manner, the above dc-off algorithm may be pre-stored in the FPGA module 11, and at this time, the FPGA module 11 is further configured to control the compression and decompression module to decompress the first downlink digital signal according to a preset dc-off algorithm.

In the foregoing uplink and downlink transmission, the compression and decompression module 112 in the communication device 10 has been described as to how to decompress the first downlink digital signal and compress the second uplink digital signal.

In the following description, the digital filter module 113 in the communication device 10 specifically performs filtering processing on the decompressed first downlink digital signal and performs filtering processing on the first uplink digital signal in the uplink transmission and downlink transmission processes:

it should be noted that, the existing pRRU using a domestic device lacks a necessary digital filter with finite-length unit impulse response, and cannot meet the requirement of a communication carrier on the filtering performance of the pRRU.

As one possible embodiment, for the above-mentioned problem, the digital filter module 113 in the present application applies a digital filter of the frequency-response-masking (FRM) type to filter the decompressed first downlink digital signal and to filter the first uplink digital signal to meet the filtering performance requirement of the communication carrier on the pRRU.

In the above description, the digital filter module 113 in the communication device 10 specifically performs the filtering processing on the decompressed first downlink digital signal and performs the filtering processing on the first uplink digital signal in the uplink transmission and the downlink transmission.

As a possible embodiment, in the communication device 10 provided in the present application, the FPGA module 11 includes at least one first functional pin corresponding to the first transceiver 121, and at least one second functional pin corresponding to the second transceiver 122.

Optionally, the number of the first functional pins is the same as the number of the second functional pins, and the first functional pins and the second functional pins are symmetrically distributed inside the FPGA module.

Optionally, the FPGA module 11 is further configured to optimize the interface timing between the FPGA module 11 and the first transceiver 121. And, the FPGA module 11 is further configured to optimize interface timing between the FPGA module 11 and the second transceiver 122.

Thus, the communication device 10 in the present application can ensure the phase alignment of the data between the FPGA module 11 and the first transceiver 121 and the second transceiver 122.

It should be noted that, an algorithm for optimizing the timing of the interface between the FPGA module 11 and the first transceiver 121 and the second transceiver 122 may be stored in the FPGA module 11. The algorithm for specifically optimizing the interface timing is not specifically limited in this application.

As a possible embodiment, in the communication device 10 provided in the present application, an interface data alignment algorithm is also pre-stored in the FPGA module 11 to align data between the FPGA module 11 and the LVDS interfaces of the first transceiver 121 and the second transceiver 122.

In the following description, the QEC calibration module 123 and the DC calibration module 124 in the communication device 10 calibrate the downlink analog signal and calibrate the first uplink digital signal in the uplink and downlink transmission processes:

as a possible embodiment, in the communication device 10 provided in the present application, the QEC calibration module 123 performs QEC calibration on the downstream analog signal and the first upstream digital signal based on the QEC algorithm,

specifically, the QEC algorithm obtains a phase imbalance error estimated value and a gain imbalance error estimated value of the current symbol through an algorithm by using an in-phase vector and a quadrature vector of the output previous symbol; according to the phase compensation coefficient of the previous symbol and the phase unbalance estimation value, calculating to obtain the phase compensation coefficient of the current symbol; meanwhile, according to the gain compensation coefficient of the previous symbol and the gain imbalance estimated value, calculating to obtain the gain compensation coefficient of the current symbol; and compensating the in-phase vector and the quadrature vector of the received/transmitted current symbol according to the phase compensation coefficient and the gain compensation coefficient, and outputting the compensated current symbol.

In addition, the DC calibration module 124 performs DC calibration on the downstream analog signal and the first upstream digital signal based on the mean algorithm for the purpose of DC removal.

In one possible implementation, the QEC algorithm and the mean algorithm described above may be pre-stored in the FPGA module 11.

At this time, the FPGA module 11 is further configured to control the QEC calibration module to perform QEC calibration on the first uplink digital signal according to a preset QEC calibration algorithm. And the PGA module 11 is further configured to control the DC calibration module to perform DC calibration on the first uplink digital signal according to a preset DC calibration algorithm.

As shown in fig. 7, fig. 7 is a schematic diagram of how the QEC calibration module 123 and the DC calibration module 124 specifically calibrate signals in the communication device 10 provided in the present application.

In fig. 7, QEC calibration module 123 estimates Δa and ΔΦ based on the QEC algorithm, thereby performing compensation calibration on the signal based on the circuit shown in fig. 7.

In the foregoing uplink and downlink processes, the QEC calibration module 123 and the DC calibration module 124 in the communication device 10 calibrate the downlink analog signal and calibrate the first uplink digital signal.

As a possible embodiment, in the communication device 10 provided in the present application, the PA module 131 controls the output power of the PA module based on a preset gate voltage control algorithm.

Alternatively, the preset gate voltage control algorithm may be pre-stored in the FPGA module 11. At this time, the FPGA module 11 is further configured to control the output power of the PA module 131 according to a preset gate voltage control algorithm.

Illustratively, in connection with fig. 1, as shown in fig. 8, as a possible embodiment, the communication device 10 provided in the present application further includes a clock module 15.

The clock module 15 is configured to ensure clock alignment during signal interaction among the FPGA module 11, the first transceiver 121, and the second transceiver 122.

As a possible embodiment of the present application, as shown in fig. 9, fig. 9 is a schematic flow chart of a method for adjusting performance of a communication device according to an embodiment of the present application, which is applied to an uplink transmission process of the communication device 10 shown in fig. 1. The method specifically comprises the following steps:

s901, the communication equipment receives a first downlink digital signal and generates a second downlink digital signal according to the first downlink digital signal.

S902, the communication equipment converts the second downlink digital signal to obtain a downlink analog signal.

S903, the communication device performs power amplification processing on the downlink analog signal to obtain a downlink analog signal after power amplification.

S904, the communication equipment transmits the downlink analog signals with amplified power to the radio frequency antenna.

The description and the beneficial effects may refer to the description of the communication device 10 in the uplink transmission process, which is not repeated here.

As yet another possible embodiment of the present application, as shown in fig. 10, fig. 10 is a flow chart of a method for optimizing performance of a communication device according to embodiment 5 of the present application, which is applied to an uplink transmission process of the communication device 10 shown in fig. 1. The method specifically comprises the following steps:

s1001, the communication equipment receives an uplink analog signal.

S1002, the communication device converts the uplink analog signal to obtain a first uplink digital signal.

And 0S1003, the communication equipment performs filtering and compression processing on the first uplink digital signal to obtain a second uplink digital signal.

And S1004, the communication device transmits the second uplink digital signal to the upper-level device.

The embodiment of the present application may divide the functional modules or functional units of the communication device performance tuning apparatus according to the above method example, for example, each functional module or functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing module.

The integrated modules can be realized in the form of hardware, software functional modules or

And the functional units are realized in the form of. In this embodiment, the division of the modules or units is 0 schematically, which is merely a logic function division, and other division manners may be implemented in practice.

As a possible embodiment, as shown in fig. 11, a schematic structural diagram of a communication device performance tuning apparatus 1100 provided in an embodiment of the present application is provided, where the apparatus includes:

the communication unit 1101 is configured to receive a first downlink data signal.

The processing unit 1102 is configured to generate a second downlink digital signal according to the first downlink digital signal. And the processing unit 1102 is further configured to convert the second downlink digital signal to obtain a downlink analog signal.

The processing unit 1102 is further configured to perform power amplification processing on the downlink analog signal, to obtain a downlink analog signal after power amplification.

The communication unit 1101 is further configured to send the power-amplified downlink analog signal to a radio frequency antenna. 0 optionally, the communication device performance tuning apparatus 1100 may further include a storage unit (shown in a dashed box in fig. 11) storing a program or an instruction, which when executed by the processing unit 1102, enables the communication device performance tuning apparatus 1100 to perform the communication device performance tuning method of the above-described method embodiment.

In addition, the technical effects of the communication device performance tuning apparatus of fig. 11 may refer to the technical effects of the communication device performance tuning method of the foregoing embodiment, and will not be described herein.

As a possible embodiment, as shown in fig. 12, a schematic structural diagram of a performance tuning apparatus 1200 for a communication device according to an embodiment of the present application is provided, where the apparatus includes:

a communication unit 1201 is configured to receive an uplink analog signal.

The processing unit 1202 converts the uplink analog signal to obtain a first uplink digital signal.

The processing unit 1202 is further configured to perform filtering and compression processing on the first uplink digital signal to obtain a second uplink digital signal.

The communication unit 1201 is further configured to send a second uplink digital signal to the higher-level device.

Optionally, the communication device performance tuning apparatus 1200 may further include a storage unit (shown in a dashed box in fig. 12) storing a program or an instruction, which when executed by the processing unit 1202, enables the communication device performance tuning apparatus 1200 to perform the communication device performance tuning method described in the above method embodiment.

In addition, the technical effects of the communication device performance tuning apparatus described in fig. 12 may refer to the technical effects of the communication device performance tuning method described in the foregoing embodiments, and are not repeated here.

Fig. 13 is a schematic view illustrating still another possible configuration of the communication device performance tuning apparatus according to the above embodiment. As shown in fig. 13, the communication device performance tuning apparatus 1300 includes: a processor 1302.

The processor 1302 is configured to control and manage the actions of the performance tuning apparatus of the communication device, for example, perform the steps performed by the communication unit 1101, the processing unit 1102, the communication unit 1201, and the processing unit 1202, and/or perform other processes of the technical solutions described herein.

The processor 1302 may be implemented or executed with various exemplary logic blocks, modules, and circuits described in connection with the present application. The processor may be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.

Optionally, the communication device performance tuning apparatus 1300 may further include a communication interface 1303, a memory 1301, and a bus 1304. The communication interface 1303 is used to support communication between the communication device performance tuning apparatus 1300 and other network entities. The memory 1301 is used for storing program codes and data of the communication apparatus performance tuning apparatus.

Wherein the memory 1301 may be a memory in the communication apparatus performance tuning apparatus, which may include a volatile memory, such as a random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, hard disk or solid state disk; the memory may also comprise a combination of the above types of memories.

Bus 1304 may be an extended industry standard architecture (Extended Industry Standard Ar chitecture, EISA) bus or the like. The bus 1304 may be classified as an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in fig. 13, but not only one bus or one type of bus.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and modules may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.

Embodiments of the present application provide a computer program product containing instructions, which when executed on an electronic device of the present application, cause the computer to perform the method for optimizing performance of a communication device according to the method embodiments described above.

The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores instructions, and when the computer executes the instructions, the electronic device of the application executes each step executed by the communication device performance tuning device in the method flow shown in the method embodiment.

The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: electrical connections having one or more wires, portable computer diskette, hard disk. Random access Memory (Random Access Memory, RAM), read-Only Memory (ROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), registers, hard disk, optical fiber, portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any other form of computer-readable storage medium suitable for use by a person or combination of the foregoing, or as a numerical value in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (Application Specific Integ rated Circuit, ASIC). In the context of the present application, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A communication device, the method comprising: the system comprises a field programmable gate array FPGA module, a transceiver module and a radio frequency subsystem module;

the FPGA module is used for receiving a first downlink digital signal; decompressing and filtering the first downlink digital signal to obtain a second downlink digital signal; transmitting the second downstream digital signal to the transceiver module;

the transceiver module is used for receiving the downlink digital signal sent by the FPGA module; converting the second downlink digital signal to obtain a downlink analog signal; transmitting the downlink analog signal to the radio frequency subsystem module;

the radio frequency subsystem module is used for receiving the downlink analog signals sent by the transceiver module; performing power amplification processing on the downlink analog signals to obtain downlink analog signals after power amplification; and transmitting the downlink analog signal after power amplification to a radio frequency antenna.

2. The communication device of claim 1, wherein the FPGA module comprises: CPRI interface module, compression decompression module, digital filter module;

the CPRI interface module is configured to receive the first downlink digital signal;

the compression and decompression module is used for performing decompression processing on the first downlink digital signal to obtain a decompressed first downlink digital signal;

and the digital filter module is used for carrying out filtering processing on the decompressed first downlink digital signal to obtain the second downlink digital signal.

3. The communication device according to claim 2, wherein the FPGA module is specifically configured to:

and controlling the CPRI interface module to receive the first downlink digital signal according to the CPRI IP of the open source.

4. A communication device according to claim 3, characterized in that the FPGA module is specifically configured to:

and controlling the compression and decompression module to decompress the first downlink digital signal according to a preset DC algorithm.

5. The communication device of claim 4, wherein the digital filter module performs the filtering process using a frequency response mask FRM digital filter.

6. The communication device of claim 5, wherein the second downstream digital signal comprises the third downstream digital signal and the fourth downstream digital signal, the downstream analog signal comprises a first downstream analog sub-signal and a second downstream analog sub-signal, and the transceiver module comprises a first transceiver and a second transceiver; the wiring connection between the FPGA module and the first transceiver is axisymmetric with the wiring connection between the FPGA module and the second transceiver;

the first transceiver is configured to convert the third downlink digital signal to obtain the first downlink analog sub-signal;

the second transceiver is configured to convert the fourth downlink digital signal to obtain the second downlink analog sub-signal.

7. The communication device according to claim 6, wherein the FPGA module is specifically configured to:

transmitting the third downstream digital signal to the first transceiver;

transmitting the fourth downstream digital signal to the second transceiver;

and carrying out data alignment processing on the third downlink digital signal and the fourth downlink digital signal according to the first preset algorithm.

8. The communication device according to claim 7, wherein the FPGA module is specifically configured to:

optimizing interface timing between the FPGA module and the first transceiver;

and optimizing interface time sequence between the FPGA module and the second transceiver.

9. The communication device of claim 8, wherein the FPGA module comprises at least one first functional pin corresponding to the first transceiver and at least one second functional pin corresponding to the second transceiver;

the first function pins and the second function pins are the same in number, and the first function pins and the second function pins are symmetrically distributed inside the FPGA module.

10. The communication device of claim 9, wherein the transceiver module comprises: a plurality of QEC calibration modules, a plurality of DC calibration modules; the first transceiver comprises at least one QEC calibration module and at least one DC calibration module, and the second transceiver comprises at least one QEC calibration module and at least one DC calibration module;

the QEC calibration module is used for QEC calibration of the downlink analog signals;

and the DC calibration module is used for carrying out DC calibration on the downlink analog signals.

11. The communication device according to claim 10, wherein the FPGA module is specifically configured to:

according to the preset QEC calibration algorithm, controlling the QEC calibration module to perform QEC calibration on the downlink analog signal;

and controlling the DC calibration module to perform DC calibration on the downlink analog signal according to the preset DC calibration algorithm.

12. The communication device of claim 11, wherein the radio frequency subsystem module comprises: a power amplifier PA module;

and the PA module is used for carrying out power amplification processing on the downlink analog signals to obtain the downlink analog signals after power amplification.

13. The communication device according to claim 12, wherein the FPGA module is specifically configured to:

and controlling the output power of the PA module according to a preset grid voltage control algorithm.

14. The communication device according to claim 13, characterized in that the communication device further comprises: a clock module;

the clock module is used for guaranteeing clock alignment during signal interaction among the FPGA module, the first transceiver and the second transceiver.

15. A communication device, the communication device comprising: the system comprises an FPGA module, a transceiver module and a radio frequency subsystem module;

The radio frequency subsystem module is used for receiving the uplink analog signals sent by the radio frequency antenna; transmitting the upstream analog signal to the transceiver module;

the transceiver module is used for receiving the uplink analog signal sent by the radio frequency subsystem module; converting the uplink analog signal to obtain a first uplink digital signal; sending the first uplink digital signal to the FPGA module;

the FPGA module is used for receiving the first uplink digital signal sent by the transceiver module; filtering and compressing the first uplink digital signal to obtain a second uplink digital signal; and sending the second uplink digital signal to the upper-level equipment.

16. The communication device of claim 15, wherein the FPGA module comprises: CPRI interface module, compression decompression module, digital filter module;

the digital filter module is used for carrying out filtering processing on the first uplink digital signal to obtain a filtered first uplink digital signal;

the compression and decompression module is used for decompressing the filtered first uplink digital signal to obtain the second uplink digital signal;

The CPRI interface module is configured to send the second uplink digital signal.

17. The communication device according to claim 16, wherein the FPGA module is specifically configured to:

and controlling the CPRI interface module to send the second uplink digital signal according to the CPRI IP of the open source.

18. The communication device according to claim 17, wherein the FPGA module is specifically configured to:

and controlling the compression decompression module to decompress the filtered first uplink digital signal according to a preset DC algorithm.

19. The communication device of claim 18, wherein the digital filter module performs the filtering process using a FRM digital filter.

20. The communication device of claim 19, wherein the upstream analog signal comprises a first upstream analog sub-signal and a second upstream analog sub-signal, the first upstream digital signal comprises a third upstream digital signal and a fourth upstream digital signal, and the transceiver module comprises a first transceiver and a second transceiver; the wiring connection between the FPGA module and the first transceiver is axisymmetric with the wiring connection between the FPGA module and the second transceiver;

The first transceiver is configured to convert the first uplink analog sub-signal to obtain the third uplink digital signal;

the second transceiver is configured to convert the second uplink analog sub-signal to obtain the fourth uplink digital signal.

21. The communication device according to claim 20, wherein the FPGA module is specifically configured to:

receiving the third uplink digital signal sent by the first transceiver;

receiving the fourth uplink digital signal sent by the second transceiver;

and carrying out data alignment processing on the third uplink digital signal and the fourth uplink digital signal according to the first preset algorithm.

22. The communication device according to claim 21, wherein the FPGA module is specifically configured to:

optimizing interface timing between the FPGA module and the first transceiver;

23. The communication device of claim 22, wherein the FPGA module comprises at least one first functional pin corresponding to the first transceiver and at least one second functional pin corresponding to the second transceiver;

24. The communication device of claim 23, wherein the transceiver module comprises: a plurality of QEC calibration modules, a plurality of DC calibration modules; the first transceiver comprises at least one QEC calibration module and at least one DC calibration module, and the second transceiver comprises at least one QEC calibration module and at least one DC calibration module;

the QEC calibration module is used for QEC calibration of the first uplink digital signal;

the DC calibration module is used for carrying out DC calibration on the first uplink digital signal.

25. The communication device according to claim 24, wherein the FPGA module is specifically configured to:

according to the preset QEC calibration algorithm, controlling the QEC calibration module to perform QEC calibration on the first uplink digital signal;

and controlling the DC calibration module to perform DC calibration on the first uplink digital signal according to the preset DC calibration algorithm.

26. The communication device of claim 25, wherein the communication device further comprises: a clock module;

27. A method for optimizing performance of a communication device, the method comprising:

receiving a first downlink digital signal and generating a second downlink digital signal according to the first downlink digital signal;

converting the second downlink digital signal to obtain a downlink analog signal;

performing power amplification processing on the downlink analog signals to obtain downlink analog signals after power amplification;

and transmitting the downlink analog signal after power amplification to a radio frequency antenna.

28. A method for optimizing performance of a communication device, the method comprising:

receiving an uplink analog signal;

converting the uplink analog signal to obtain a first uplink digital signal;

filtering and compressing the first uplink digital signal to obtain a second uplink digital signal;

and sending the second uplink digital signal to the upper-level equipment.