CN116247147B - LED chip preparation method and LED substrate - Google Patents
LED chip preparation method and LED substrate Download PDFInfo
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- CN116247147B CN116247147B CN202310311286.4A CN202310311286A CN116247147B CN 116247147 B CN116247147 B CN 116247147B CN 202310311286 A CN202310311286 A CN 202310311286A CN 116247147 B CN116247147 B CN 116247147B
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 141
- 229910052751 metal Inorganic materials 0.000 claims abstract description 125
- 239000002184 metal Substances 0.000 claims abstract description 125
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 230000000903 blocking effect Effects 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 229910002601 GaN Inorganic materials 0.000 claims description 21
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 229910052594 sapphire Inorganic materials 0.000 claims description 12
- 239000010980 sapphire Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000005083 Zinc sulfide Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
Abstract
The application specifically relates to a preparation method of an LED chip and an LED substrate, wherein the preparation method comprises the following steps: providing a substrate; forming a first metal film layer on a substrate, and performing photoetching treatment on the first metal film layer to form first metal barrier blocks; forming a protective layer on the substrate and the first metal barrier block, and carrying out photoetching treatment on the protective layer to obtain a protective block; forming a second metal film layer on the substrate, the protection block and the blocking part, and carrying out photoetching treatment on the second metal film layer to form a second metal blocking block; forming an epitaxial layer on the substrate, the second metal barrier block and the barrier portion; etching the epitaxial layer to remove the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier part; removing the first metal barrier block and the second metal barrier block; an electrode is formed on a side of the epitaxial layer remote from the substrate. According to the scheme, the protection block is added on the side wall of the epitaxial layer, and the side wall of the epitaxial layer is protected during inductively coupled plasma etching, so that the luminous efficiency of the LED chip is guaranteed.
Description
Technical Field
The application belongs to the technical field of chips, and particularly relates to a preparation method of an LED chip and an LED substrate.
Background
With the development of light emitting diode (Light Emitting Diode, simply referred to as LED) technology, LED chips have been widely used in lighting, indication, display and backlight sources, and the dicing technology of semiconductor wafers has a certain influence on the brightness of the produced LED chips.
Among them, the microled display technology is considered to be the best display technology in the future because of its high stability, long life, better display effect, and higher resolution. When the micro chip is etched by utilizing inductively coupled plasma in the manufacturing process, the side wall of the LED is easily damaged, so that the luminous efficiency of the edge of the LED is reduced.
Disclosure of Invention
The invention aims to provide a preparation method of an LED chip and an LED substrate, which can protect the side wall of an LED during inductively coupled plasma etching.
The first aspect of the application provides a preparation method of an LED chip, which comprises the following steps:
providing a substrate;
forming a first metal film layer on the substrate, and performing photoetching treatment on the first metal film layer to form a first metal barrier block; the first metal blocking block comprises a carrying part and a blocking part, the blocking part is arranged on one side of the carrying part far away from the substrate, and the orthographic projection of the carrying part on the substrate is positioned in the orthographic projection of the blocking part on the substrate;
forming a protective layer on the substrate and the first metal barrier block, and performing photoetching treatment on the protective layer to obtain a protective block, wherein the protective block covers the bearing part and is arranged around the barrier part;
forming a second metal film layer on the substrate, the protection block and the blocking part, and performing photoetching treatment on the second metal film layer to form a second metal blocking block, wherein the second metal blocking block is arranged on one side, far away from the substrate, of the protection block;
forming an epitaxial layer on the substrate, the second metal barrier block and the barrier part, wherein the side wall of the epitaxial layer on the substrate is connected with the protection block, and the height of the epitaxial layer on the substrate is smaller than or equal to the sum of the heights of the protection block and the receiving part; etching the epitaxial layer to remove the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier part;
removing the first metal barrier block and the second metal barrier block;
an electrode is formed on a side of the epitaxial layer remote from the substrate.
In one exemplary embodiment of the present application, forming the protection block includes the steps of:
an alumina protective layer is formed on the substrate and the first barrier block by atomic layer deposition with trimethylaluminum and water vapor as reactive gases and nitrogen as a carrier gas.
In an exemplary embodiment of the present application, after forming the protection block, the method further includes the steps of:
and annealing the protection block at a temperature of 700-1200 ℃.
In one exemplary embodiment of the present application, removing the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier portion comprises the steps of:
and forming photoresist on the epitaxial layer on the substrate, and removing the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier part through inductively coupled plasma etching.
In one exemplary embodiment of the present application, removing the first metal barrier block and the second metal barrier block includes the steps of:
etching the first metal barrier block and the second metal barrier block through acid liquor.
In an exemplary embodiment of the present application, the epitaxial layer includes undoped gallium nitride, N-type gallium nitride, multiple quantum wells, and P-type gallium nitride sequentially formed in a thickness direction of the substrate, and a height of the undoped gallium nitride is greater than a height of the socket.
In one exemplary embodiment of the present application, the overall height of the second metal barrier block, the protective block and the receptacle is equal to or higher than the sum of the heights of the receptacle and the barrier.
In an exemplary embodiment of the present application, the sum of the height of the susceptor and the height of the barrier is higher than the height of the epitaxial layer.
In an exemplary embodiment of the present application, the substrate is sapphire.
The second aspect of the application provides an LED substrate, which comprises at least one LED chip prepared by the preparation method of the LED chip, wherein the LED chip comprises a substrate, an epitaxial layer, a first electrode and a second electrode, the epitaxial layer is formed on the substrate, and the first electrode and the second electrode are formed on one side of the epitaxial layer away from the substrate.
The scheme of the application has the following beneficial effects:
according to the scheme, the protection block is added to the side wall of the epitaxial layer before the epitaxial layer is formed, and when the inductively coupled plasma etching is utilized, the side wall of the epitaxial layer is protected through the protection block, so that the integrity of the side wall of the LED chip is guaranteed, and the integrity of the edge of the LED chip is guaranteed.
In addition, this application scheme still includes the LED base plate, includes at least one LED chip that utilizes this LED chip preparation method to prepare on the LED base plate, and the LED chip is through forming the protection piece on the lateral wall of epitaxial layer, avoids taking place the damage to the LED lateral wall when inductively coupled plasma etching, guarantees LED edge luminous efficacy, and then guarantees the luminous efficacy of LED chip.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 shows a flowchart of a method for manufacturing an LED chip according to an embodiment of the present application;
fig. 2 is a schematic structural diagram illustrating a first metal film layer formed on a substrate according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a first metal spacer obtained by performing a photolithography process on a first metal film layer according to an embodiment of the present application;
FIG. 4 is a flow chart illustrating the formation of a protection block according to one embodiment of the present application;
fig. 5 is a schematic structural view of forming a protective layer on a substrate, a receiving portion and a blocking portion according to the first embodiment of the present application;
FIG. 6 shows a first embodiment of the present application for performing a photolithography process on a protective layer to obtain a protective block;
fig. 7 is a schematic structural diagram of forming a second metal film layer on a substrate, a protection block and a barrier according to the first embodiment of the present application;
fig. 8 is a schematic structural diagram of a second metal spacer obtained by performing a photolithography process on a second metal film according to an embodiment of the present application;
fig. 9 shows a flowchart for forming an epitaxial layer according to an embodiment of the present application;
fig. 10 is a schematic view of a structure of an epitaxial layer formed on a substrate, a second metal barrier block and a barrier according to an embodiment of the present application;
fig. 11 is a schematic structural view of removing an epitaxial layer, a first metal spacer and a second metal spacer according to an embodiment of the present application;
fig. 12 is a schematic diagram showing a structure of forming an electrode on an epitaxial layer according to the first or second embodiment of the present application.
Reference numerals illustrate:
11. a substrate; 12. a first metal film layer; 13. a first metal spacer block; 131. a receiving part; 132. a blocking portion; 14. a protective layer; 15. a protection block; 16. a second metal film layer; 17. a second metal spacer block; 18. an epitaxial layer; 19. an electrode.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
In this application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly, and may be, for example, fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
Example 1
The side wall of the LED is easy to damage when the inductively coupled plasma is etched, and the micro LED chip is small in size, so that the side wall of the micro LED is damaged, the edge luminous efficiency of the micro LED is greatly influenced, and the luminous efficiency of the micro LED chip is obviously reduced.
Fig. 1 shows a flowchart of a method for manufacturing an LED chip according to an embodiment of the present application.
In order to avoid damage to the side wall of the micro LED chip during inductively coupled plasma etching, the embodiment of the present application provides a method for manufacturing an LED chip, as shown in fig. 1, which includes the following steps:
in step S10, a substrate 11 is provided.
First, a substrate 11 is provided, and the substrate 11 may be a sapphire (Al 2O 3) substrate 11, a silicon carbide (SiC) substrate 11, a gallium arsenide (GaAs) substrate 11, zinc oxide (ZnO), zinc sulfide (ZnS), or the like suitable for use in manufacturing an LED chip. In the embodiment of the present application, the substrate 11 is a sapphire substrate 11.
Fig. 2 is a schematic structural diagram of forming a first metal film layer on a substrate according to an embodiment of the present application; fig. 3 is a schematic structural diagram of a first metal spacer obtained by performing a photolithography process on a first metal film according to an embodiment of the present application.
Step S20, referring to fig. 1, 2 and 3, of forming a first metal film layer 12 on a substrate 11, and performing a photolithography process on the first metal film layer 12 to form first metal barrier ribs 13; the first metal barrier block 13 includes a receiving portion 131 and a barrier portion 132, the barrier portion 132 is disposed on a side of the receiving portion 131 away from the substrate 11, and an orthographic projection of the receiving portion 131 on the substrate 11 is located in an orthographic projection of the barrier portion 132 on the substrate 11.
The first metal film layer 12 is formed on the sapphire substrate 11 by physical vapor deposition (Physical Vapor Deposition, PVD) or by evaporation or the like. And the first metal film layer 12 is subjected to patterning (photolithography) treatment by a photolithography technique, thereby forming a plurality of first metal barrier ribs 13, the first metal barrier ribs 13 being used for separating the LEDs.
In this embodiment, the first metal spacer 13 includes a receiving portion 131 and a blocking portion 132, the blocking portion 132 is disposed on one side of the receiving portion 131 away from the sapphire substrate 11, an inverted T-shaped structure is formed between the receiving portion 131 and the blocking portion 132, and the orthographic projection of the receiving portion 131 on the substrate 11 is located in the orthographic projection of the blocking portion 132 on the substrate 11. Gaps are arranged between the bearing parts 131 of the adjacent two first metal barrier blocks 13 so as to separate the LEDs independently; the height of the receiving portion 131 is in the range of 0.5 μm to 2. Mu.m, for example, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm.
In the embodiment of the present application, the blocking portion 132 is located at the center of the receiving portion 131, so as to ensure that the LEDs formed on both sides of the first metal blocking block 13 are the same in size. The width of the receiving portion 131 from the edge of the blocking portion 132 is, for example, 0.1 μm to 10 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, 10 μm.
FIG. 4 shows a flowchart for forming a protection block provided by an embodiment of the present application; FIG. 5 shows a schematic view of a structure for forming a protective layer on a substrate, a susceptor and a barrier according to an embodiment of the present application; fig. 6 illustrates a protection block obtained by performing a photolithography process on a protection layer according to an embodiment of the present application.
In step S30, as shown in fig. 1, 4, 5 and 6, a protective layer 14 is formed on the substrate 11 and the first metal barrier rib 13, and the protective layer 14 is subjected to a photolithography process to obtain a protective block 15, the protective block 15 covering the receiving portion 131 and being disposed around the barrier portion 132.
Referring to fig. 4, forming the protection block 15 on the first metal barrier block 13 includes the steps of:
step S31 of forming an aluminum oxide (Al 2O 3) protective layer 14 on the substrate 11 and the first metal barrier ribs 13 by Atomic Layer Deposition (ALD) using trimethylaluminum and water vapor as a reaction gas and nitrogen as a carrier gas, as shown in fig. 5;
in step S32, the protective layer 14 of alumina (Al 2O 3) formed on the substrate 11 and the first metal barrier rib 13 is subjected to a photolithography process, leaving the protective rib 15 on the side of the receiving portion 131 away from the substrate 11, the protective rib 15 being disposed around the barrier portion 132.
Step S33, annealing the protection block 15 at a temperature of 700 to 1200 ℃, as shown in fig. 6.
For example, the protection block 15 is subjected to a high-temperature annealing treatment at a temperature of 700 ℃ to crystallize the alumina; at 800 ℃, the protection block 15 is subjected to high-temperature annealing treatment to crystallize the alumina; at 900 ℃, the protection block 15 is subjected to high-temperature annealing treatment to crystallize the alumina; at 1000 ℃, the protection block 15 is subjected to high-temperature annealing treatment to crystallize the alumina; at 1100 deg.c, the protecting block 15 is annealed at high temperature to crystallize alumina; the protection block 15 was subjected to a high temperature annealing treatment at 1200 c to crystallize alumina.
It can be understood that crystallizing the alumina at 700 to 1200 ℃ can improve the combination degree of the alumina and the epitaxial layer 18, so that the alumina protection block 15 protects the outer wall of the epitaxial layer 18 better, prevents damage to the outer wall of the epitaxial layer 18 during inductively coupled plasma etching, ensures the integrity of the edge of the LED, and further ensures the luminous efficiency of the LED chip.
Fig. 7 is a schematic structural diagram of forming a second metal film layer on a substrate, a protection block and a barrier according to an embodiment of the present application; fig. 8 is a schematic structural diagram of a second metal spacer obtained by performing a photolithography process on a second metal film according to an embodiment of the present application.
In step S40, referring to fig. 1, 7 and 8, a second metal film layer 16 is formed on the substrate 11, the protection block 15 and the barrier portion 132, and the second metal film layer 16 is subjected to a photolithography process to form a second metal barrier block 17, where the second metal barrier block 17 is disposed on a side of the protection block 15 away from the substrate 11.
The second metal film layer 16 is formed on the sapphire substrate 11, the protection block 15 and the barrier 132 by physical vapor deposition (Physical Vapor Deposition, PVD) or by evaporation or the like. And patterning the second metal film layer 16 by photolithography, forming second metal barrier ribs 17 on the barrier 132 and the side of the protection block 15 away from the substrate 11.
In the embodiment of the present application, referring to fig. 8, the top surface of the second metal barrier block 17 is flush with the top surface of the barrier 132 or the top surface of the second metal barrier block 17 is higher than the top surface of the barrier 132.
In some embodiments, the top surface of the second metal barrier block 17 may also be lower than the top surface of the barrier 132.
Fig. 9 shows a flowchart for forming an epitaxial layer according to an embodiment of the present application; fig. 10 shows a schematic structural diagram of an epitaxial layer formed on a substrate, a second metal spacer and a spacer provided in an embodiment of the present application.
Step S50, as shown in fig. 1, 9 and 10, forming an epitaxial layer 18 on the substrate 11, the second metal barrier rib 17 and the barrier portion 132, wherein the sidewall of the epitaxial layer 18 on the substrate 11 is connected to the protection block 15, and the height of the epitaxial layer 18 on the substrate 11 is less than or equal to the sum of the heights of the protection block 15 and the receiving portion 131; the epitaxial layer 18 is subjected to an etching process to remove the epitaxial layer 18 on the second metal barrier ribs 17 and the epitaxial layer 18 on the barrier 132.
A U-GaN (undoped gallium nitride) layer, N-GaN (N-type gallium nitride), MQW (multiple quantum well), P-GaN (P-type gallium nitride) which constitutes a light emitting layer is epitaxially grown in this order on the sapphire substrate 11, the second metal barrier rib 17, and the barrier portion 132 using Metal Organic Chemical Vapor Deposition (MOCVD).
It should be noted that the annealing temperature reaches 1000 ℃ after the preparation of the epitaxial layer 18, and the aluminum oxide needs to be crystallized at a temperature of 700 ℃ to 1200 ℃ when the aluminum oxide protection block 15 is manufactured, so in order to avoid damage to the first metal barrier block 13 during the annealing of the epitaxial layer 18 or the aluminum oxide, the first metal film 12 may be made of a metal with a melting point above 1200 ℃ such as iron (Fe), titanium (Ti) or molybdenum (Mo), so as to ensure the integrity of the first metal barrier block 13, and support the protection block 15 better, so that the protection block 15 is formed outside the epitaxial layer 18 better.
It will be appreciated that the second metal film layer 16 may also be made of the same metal as the first metal film layer 12, for example: metals having a melting point of 1200 ℃ or higher, such as iron (Fe), titanium (Ti) and molybdenum (Mo).
In addition, the height of the epitaxial layer 18 may be less than or equal to the sum of the heights of the protection block 15 and the receiving part 131, so that the protection block 15 protects the sidewall of the epitaxial layer 18 from damage caused to the sidewall of the epitaxial layer 18 during the inductively coupled plasma etching.
In the embodiment of the present application, referring to fig. 10, the height of the epitaxial layer 18 is equal to the sum of the heights of the receiving part 131 and the protection block 15, and in order to avoid damage to the light emitting layer of the epitaxial layer 18 during the inductively coupled plasma etching, the protection block 15 should completely cover the N-GaN (N-type gallium nitride), MQW (multiple quantum well), P-GaN (P-type gallium nitride) light emitting layer. That is, the protection block 15 should cover the sidewalls of N-GaN (N-type gallium nitride), MQW (multiple quantum well), and P-GaN (P-type gallium nitride), and the height of the receiving portion 131 should be less than or equal to the height of the U-GaN (undoped gallium nitride) layer, so as to ensure that the height of the protection block 15 can completely cover the height of the light emitting layer, further ensure that the sidewalls of the epitaxial layer 18 are protected during inductively coupled plasma etching, avoid damaging the light emitting layer, and further ensure the light emitting efficiency of the LED chip.
In some embodiments, the height of the epitaxial layer 18 may be smaller than the sum of the height of the receiving part 131 and the height of the protection block 15, and in addition, the height of the receiving part 131 should be smaller than or equal to the height of the U-GaN (undoped gallium nitride) layer, so as to ensure that the height of the protection block 15 can completely cover the height of the light emitting layer, further ensure that the sidewall of the epitaxial layer 18 is protected during inductively coupled plasma etching, so as to avoid damage to the light emitting layer, and further ensure the light emitting efficiency of the LED chip.
In addition, since the protection block 15 is placed on the receiving portion 131 of the first metal spacer 13, the bottom surface of the alumina is not in contact with the sapphire substrate 11, and when the LED chip is peeled from the sapphire substrate 11, the peeling method is simpler, and the LED is not damaged.
Further, referring to fig. 9, the removal of the second metal spacer 17 and the epitaxial layer 18 on the spacers 132 further comprises the steps of:
in step S51, photoresist is coated on the epitaxial layer 18 on the substrate 11, and the second metal barrier ribs 17 and the epitaxial layer 18 on the barrier portion 132 are removed by inductively coupled plasma etching, so as to protect the required epitaxial layer 18 and avoid damaging the required epitaxial layer 18 during inductively coupled plasma etching.
It should be noted that, in the embodiment of the present application, the height of the sum of the second metal barrier block 17, the protection block 15 and the receiving portion 131 is greater than the height of the epitaxial layer 18 located on the substrate 11; and, the height of the sum of the barrier 132 and the susceptor 131 is also greater than the height of the epitaxial layer 18 on the substrate 11. Therefore, the height of the epitaxial layer 18 formed on the barrier portion 132 and the second metal barrier rib 17 is different from the height of the epitaxial layer 18 on the substrate 11, and when the epitaxial layer 18 on the second metal barrier rib 17 and the barrier portion 132 is removed by inductively coupled plasma etching, the reaction with the epitaxial layer 18 on the substrate 11 is reduced, so that the side wall of the epitaxial layer 18 can be further protected, the integrity of the light-emitting layer of the LED is ensured, and the light-emitting efficiency of the LED is further ensured.
Fig. 11 shows a schematic structural diagram of removing an epitaxial layer, a first metal spacer and a second metal spacer according to an embodiment of the present application.
In step S60, referring to fig. 1 and 11, the first metal spacer 13 and the second metal spacer 17 are removed.
Wherein, in the present embodiment, removing the first metal spacer 13 and the second metal spacer 17 comprises etching the first metal spacer 13 and the second metal spacer 17 by an acid solution.
It can be understood that, because the crystallized alumina protection block 15 has high lattice strength, the alumina protection block 15 is not damaged when the first metal barrier block 13 and the second metal barrier block 17 are removed by acid etching, so that the light-emitting layer in the epitaxial layer 18 can be protected, and the light-emitting efficiency of the LED can be ensured.
The acid solution may be an acidic solution such as hydrochloric acid, acetic acid or nitric acid.
Fig. 12 is a schematic diagram of a structure of forming an electrode on an epitaxial layer according to an embodiment of the present application.
In step S70, referring to fig. 1 and 12, an electrode 19 is formed on the side of the epitaxial layer 18 remote from the substrate 11.
Forming an electrode on a side of epitaxial layer 18 remote from substrate 11 includes: and manufacturing a first electrode on the P-GaN (P-type gallium nitride), manufacturing a second electrode on the N-GaN (N-type gallium nitride), wherein the first electrode and the second electrode can be a positive electrode and a negative electrode respectively, and the positive electrode and the negative electrode are made of Cr/Au, and the thickness is 50/1000nm.
In addition, in the finally formed LED chip, the alumina protection block 15 is still on the light-emitting layer on the sidewall of the epitaxial layer 18, so that the sidewall of the LED chip can be protected during the subsequent transfer of the LED chip, thereby ensuring the light-emitting efficiency of the LED chip.
According to the scheme, the aluminum oxide protection block 15 is formed on the side wall of the light-emitting layer in the epitaxial layer 18, so that the side wall of the LED can be prevented from being protected when the independent LED chips are divided by inductively coupled plasma etching, the side wall of the LED is prevented from being damaged, and the light-emitting efficiency of the LED chips is ensured.
It is understood that the preparation method of the LED chip is not only applicable to micro LEDs, but also applicable to other LED chips.
Example two
Referring to fig. 12, a second embodiment of the present application provides an LED substrate, which includes at least one LED chip prepared by the method for preparing an LED chip according to the first embodiment.
In the embodiment of the application, the LED chips on the LED substrate may be all LED chips prepared by the preparation method of embodiment one, so as to ensure the integrity of the side walls of all LED chips and ensure the overall luminous efficiency. It can be understood that the LED chips on the LED substrate are all LED chips prepared by the preparation method according to the first embodiment, the preparation process of the LED chips is simpler, the operation flow is less, and the production cost is reduced.
In some embodiments, the LED chips in a certain area on the LED substrate may be LED chips prepared by the preparation method as in the first embodiment, and the remaining area may be LED chips prepared by a conventional preparation method for preparing LED chips.
When the LED chip on the LED substrate is an LED chip prepared by the method according to the first embodiment, the LED chip includes a substrate 11, an epitaxial layer 18, a first electrode and a second electrode, the epitaxial layer 18 is disposed on the sapphire substrate 11, and the first electrode and the second electrode are formed on a side of the epitaxial layer 18 away from the substrate 11.
In the embodiment of the application, the first electrode is manufactured on P-GaN (P-type gallium nitride), the second electrode is manufactured on N-GaN (N-type gallium nitride), the first electrode and the second electrode can be a positive electrode and a negative electrode respectively, cr/Au is selected as the materials of the positive electrode and the negative electrode, and the thickness is 50/1000nm.
In the finally formed LED chip, the alumina protection block 15 is still on the light-emitting layer on the sidewall of the epitaxial layer 18, so that the sidewall of the LED chip can be protected during the subsequent transfer of the LED chip, thereby ensuring the light-emitting efficiency of the LED chip.
In addition, since the protection block 15 on the sidewall of the epitaxial layer 18 is placed on the receiving part 131 of the first metal barrier block 13, the bottom surface of the alumina is not in contact with the sapphire substrate 11, and when the LED chip is peeled from the sapphire substrate 11, the peeling mode is simpler, and no damage is caused to the LED.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it should be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the embodiments by one of ordinary skill in the art within the scope of the application, and therefore all changes and modifications that fall within the spirit and scope of the invention as defined by the claims and the specification of the application are intended to be covered thereby.
Claims (10)
1. The preparation method of the LED chip is characterized by comprising the following steps of:
providing a substrate;
forming a first metal film layer on the substrate, and performing photoetching treatment on the first metal film layer to form a first metal barrier block; the first metal blocking block comprises a carrying part and a blocking part, the blocking part is arranged on one side of the carrying part far away from the substrate, and the orthographic projection of the carrying part on the substrate is positioned in the orthographic projection of the blocking part on the substrate;
forming a protective layer on the substrate and the first metal barrier block, and performing photoetching treatment on the protective layer to obtain a protective block, wherein the protective block covers the bearing part and is arranged around the barrier part;
forming a second metal film layer on the substrate, the protection block and the blocking part, and performing photoetching treatment on the second metal film layer to form a second metal blocking block, wherein the second metal blocking block is arranged on one side, far away from the substrate, of the protection block;
forming an epitaxial layer on the substrate, the second metal barrier block and the barrier part, wherein the side wall of the epitaxial layer on the substrate is connected with the protection block, and the height of the epitaxial layer on the substrate is smaller than or equal to the sum of the heights of the protection block and the receiving part; etching the epitaxial layer to remove the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier part;
removing the first metal barrier block and the second metal barrier block;
an electrode is formed on a side of the epitaxial layer remote from the substrate.
2. The method of manufacturing an LED chip of claim 1, wherein forming the protective block comprises the steps of:
an alumina protective layer is formed on the substrate and the first metal barrier block by atomic layer deposition with trimethylaluminum and water vapor as reactive gases and nitrogen as a carrier gas.
3. The method of manufacturing an LED chip of claim 2, further comprising the steps of, after forming the protective block:
and annealing the protection block at a temperature of 700-1200 ℃.
4. A method of manufacturing an LED chip according to claim 1 or 3, characterized in that removing the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier comprises the steps of:
and forming photoresist on the epitaxial layer on the substrate, and removing the epitaxial layer on the second metal barrier block and the epitaxial layer on the barrier part through inductively coupled plasma etching.
5. A method of manufacturing an LED chip according to any one of claims 1-3, wherein removing the first and second metal barrier blocks comprises the steps of:
etching the first metal barrier block and the second metal barrier block through acid liquor.
6. The method according to claim 1, wherein the epitaxial layer includes undoped gallium nitride, N-type gallium nitride, multiple quantum wells, and P-type gallium nitride sequentially formed in a thickness direction of the substrate, and a height of the undoped gallium nitride is larger than a height of the socket.
7. The method of manufacturing an LED chip according to claim 6, wherein the overall height of the second metal spacer block, the protective block, and the receiving portion is equal to or higher than the sum of the heights of the receiving portion and the spacer portion.
8. The method of manufacturing an LED chip according to claim 6 or 7, wherein a sum of a height of the receiving portion and a height of the blocking portion is higher than a height of the epitaxial layer.
9. The method of manufacturing an LED chip of claim 1, wherein said substrate is sapphire.
10. An LED substrate, characterized in that the LED substrate comprises at least one LED chip prepared by the method for preparing an LED chip according to any one of claims 1 to 9, the LED chip comprises a substrate, an epitaxial layer, a first electrode and a second electrode, the epitaxial layer is formed on the substrate, and the first electrode and the second electrode are formed on a side of the epitaxial layer away from the substrate.
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| CN103887377A (en) * | 2014-03-12 | 2014-06-25 | 江苏新广联科技股份有限公司 | Device process for reducing GaN-based vertical structure LED leakage currents |
| CN112071964A (en) * | 2020-08-28 | 2020-12-11 | 东莞市中麒光电技术有限公司 | Preparation method of Micro LED chip |
| WO2021196008A1 (en) * | 2020-03-31 | 2021-10-07 | 京东方科技集团股份有限公司 | Inorganic light emitting diode chip and fabrication method therefor |
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| US9548332B2 (en) * | 2012-04-27 | 2017-01-17 | Apple Inc. | Method of forming a micro LED device with self-aligned metallization stack |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103887377A (en) * | 2014-03-12 | 2014-06-25 | 江苏新广联科技股份有限公司 | Device process for reducing GaN-based vertical structure LED leakage currents |
| WO2021196008A1 (en) * | 2020-03-31 | 2021-10-07 | 京东方科技集团股份有限公司 | Inorganic light emitting diode chip and fabrication method therefor |
| CN112071964A (en) * | 2020-08-28 | 2020-12-11 | 东莞市中麒光电技术有限公司 | Preparation method of Micro LED chip |
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