CN116247078A - Mixed channel compound semiconductor device - Google Patents

Mixed channel compound semiconductor device Download PDF

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Publication number
CN116247078A
CN116247078A CN202310371331.5A CN202310371331A CN116247078A CN 116247078 A CN116247078 A CN 116247078A CN 202310371331 A CN202310371331 A CN 202310371331A CN 116247078 A CN116247078 A CN 116247078A
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China
Prior art keywords
layer
channel
effect transistor
field effect
barrier layer
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CN202310371331.5A
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Chinese (zh)
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请求不公布姓名
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Dingnuo Microelectronics Wuxi Co ltd
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Dingnuo Microelectronics Wuxi Co ltd
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Priority to CN202310371331.5A priority Critical patent/CN116247078A/en
Publication of CN116247078A publication Critical patent/CN116247078A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present invention discloses a mixed channel compound semiconductor device, wherein a groove-shaped gate electrode of the device realizes a normally-off compound semiconductor device by controlling a vertical electron channel and a transverse electron channel. The device avoids the risk of high-voltage short circuit caused by using the normally-open compound semiconductor transistor in the power module, and can safely and fully exert the advantages of high efficiency and high voltage resistance of the compound semiconductor transistor in power electronics.

Description

Mixed channel compound semiconductor device
The present application is a divisional application of the invention with the application number of 201810631911.2 and the name of a mixed channel compound semiconductor device, wherein the application number is 2018, 6, 20.
Technical Field
The invention relates to the technical field of semiconductors, in particular to a mixed channel compound high-voltage device.
Background
The power electronic switch module is widely applied to power electronics and power supplies and is a basic functional module in current direct current/direct current and alternating current/direct current conversion.
Conventional solid state power electronic switch modules are implemented using silicon materials. Its performance has approached the limits of improvement in terms of module efficiency, heat dissipation, speed, etc., due to constraints on the basic properties of the silicon material.
The use of compound semiconductor materials, such as gallium nitride, to construct power electronic switch modules has been a trend in the power electronics industry. This is because the compound semiconductor material has the characteristics of high withstand voltage, low resistance and low capacitance, and has hundreds to thousands times of performance improvement potential compared with silicon.
Compound semiconductor power electronic modules face a challenge that is not found in silicon material modules-normally-off compound semiconductor power transistors are difficult to obtain. Most of the compound semiconductor transistors are normally-on devices. The disadvantage of using only normally-on compound semiconductor devices to construct a power module is that the module safety is not guaranteed.
Specifically, for a normally open device, a negative voltage needs to be provided to the control terminal to ensure that the device is turned off. In the natural state where the system is not yet energized, the normally open device is conductive. This results in the fact that in the event of failure of the negative voltage control module, the normally open device is unable to block the high voltage, providing a path from the high voltage to ground, which may cause dangerous conditions such as system short circuit burnout.
To solve this problem, one solution is to manufacture a normally-off compound semiconductor transistor. This approach is attempted to the greatest extent by compound semiconductor devices. For example, U.S. patent No. 8193562B2 describes a structure for achieving a normally-off compound semiconductor power transistor using P-type gate technology.
Disclosure of Invention
Based on this, it is necessary to provide an enhanced compound high voltage device capable of effectively solving the problem of having a positive threshold voltage.
A mixed channel compound field effect transistor comprises a substrate, and a buffer layer, a first channel layer, a first barrier layer, a second channel layer and a second barrier layer which are sequentially laminated on the substrate; a groove-shaped grid deposition area penetrating to exceed the lower surface of the second barrier layer but not exceed the lower surface of the first barrier layer is arranged on the upper surface of the second barrier layer, source deposition areas penetrating to not exceed the lower surface of the second barrier layer are respectively arranged on two sides of the grid deposition area, and drain deposition areas penetrating to exceed the lower surface of the second barrier layer but not exceed the lower surface of the first barrier layer from the upper surface of the second barrier layer; the mixed channel compound field effect transistor further comprises a gate dielectric layer, a gate electrode layer, a source electrode layer and a drain electrode layer, wherein the gate dielectric layer covers the bottom surface and the side surface of the gate electrode deposition area and extends to the upper part of the second barrier layer towards two sides; the grid electrode layer extends from the upper part of the grid dielectric layer at one side of the grid electrode deposition area to the upper part of the grid dielectric layer at the other side along the grid dielectric layer; the source layer and the drain layer extend from the bottom of the source deposition region and the bottom of the drain deposition region, respectively, along respective sides to above the barrier layer; wherein a path of electron flow in a vertical direction through the second channel layer is introduced through the second channel layer and the gate deposition region, thereby introducing a longitudinal channel; simultaneously, horizontal two-dimensional electron gas is respectively realized in the first channel layer and the second channel layer, so that a transverse channel is introduced; the gate electrode layer can control the current in the transverse channel and the longitudinal channel in the second channel layer through the gate dielectric layer by an electric field.
In one embodiment, more than one recessed gate deposition region and source deposition region are arranged on one side of the source deposition region.
In one embodiment, the source deposition regions form a two-dimensional array, and are separated by a recessed gate deposition region.
In one embodiment, the source deposition regions and the surrounding semiconductor are spaced apart by the recessed gate deposition regions in a two-dimensional array of cells having, but not limited to, circular, square, and hexagonal horizontal cross-sections.
In one embodiment, the first barrier layer has a thickness of 2 nm to 100 nm.
In one embodiment, the first barrier layer comprises Al x Ga 1-x N material, wherein X is atBetween 0 and 1, including 0 and 1 themselves.
In one embodiment, the first channel layer comprises GaN material.
In one embodiment, the material of the first channel layer comprises an impurity doping.
In one embodiment, the second channel layer comprises GaN material.
In one embodiment, the second channel layer has a thickness of 2 nanometers to 10 micrometers.
In one embodiment, the material of the second channel layer comprises an impurity doping.
In one embodiment, the second barrier layer has a thickness of 2 nm to 100 nm.
In one embodiment, the second barrier layer comprises Al x Ga 1-x N material, wherein X is between 0 and 1, including 0 and 1 itself.
In one embodiment, the gate dielectric is, but is not limited to, siO 2 、SiN、Al 2 O 3 、AlN、HfO 2 And Ga 2 O 3 One or a combination of several of them, the thickness is 0.5 nm to 100 nm.
Due to the implementation of the technical scheme, compared with the prior art, the invention has the following advantages: the compound device provided by the invention has a combination of a longitudinal channel and a transverse channel, and the effect that the total threshold voltage is positive can be achieved by controlling the threshold voltages of the two channels. Specifically, by introducing the second channel layer and the groove-shaped gate deposition region, a path through which electrons flow in a vertical direction through the second channel layer is introduced, thereby introducing a longitudinal channel; meanwhile, under the first barrier layer and the second barrier layer, horizontal two-dimensional electron gas is realized in the first channel layer and the second channel layer, respectively, due to the piezoelectric effect, thereby introducing a lateral channel. The threshold voltages of the two channels are controlled by different crystal orientations and surface states of the channel surfaces.
Drawings
Fig. 1 is a cross-sectional view of a hybrid channel compound device.
Fig. 2 is a cross-sectional view of a hybrid channel compound device with repeated recessed gate deposition regions.
Fig. 3 is a top view of a hybrid channel compound device with repeated recessed gate deposition regions.
Fig. 4 is a top view of a hybrid channel compound device with repeated recessed gate deposition regions.
Wherein the shape of the drain electrode (8) is hexagonal.
Fig. 5 is a top view of a hybrid channel compound device with repeated recessed gate deposition regions.
Wherein the shape of the drain electrode (8) is circular.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the hybrid channel compound field effect transistor according to an embodiment includes a substrate 1, and a buffer layer 2, a first channel layer 3, a first barrier layer 4, a second channel layer 5, and a second barrier layer 6, which are stacked in this order on the substrate 1.
In the present embodiment, the hybrid channel compound device is provided with a groove-shaped gate deposition region 102 penetrating from the upper surface of the second barrier layer 6 to not more than the lower surface of the first barrier layer 4, and is provided with source deposition regions (103) formed penetrating from the upper surface of the second barrier layer 6 to not more than the lower surface of the first barrier layer 4 and drain deposition regions 104 penetrating from the upper surface of the second barrier layer 6 to not more than the lower surface of the first barrier layer 4, respectively, on both sides of the gate deposition region 102.
The hybrid channel compound field effect transistor further comprises a drain layer 7, a source layer 8, a gate dielectric layer 9 and a gate layer 10. Wherein, the gate dielectric layer 9 covers the bottom surface and two side surfaces of the gate deposition region 102 and extends to the upper side of the second barrier layer 6 to two sides.
The gate layer 10 extends from above the gate dielectric layer 9 on one side of the gate deposition region 102 along the gate dielectric layer 9 to above the gate dielectric layer 9 on the other side.
In one embodiment, more than one recessed gate deposition region 102 and source deposition region 103 are arranged on one side of the source deposition region 103.
In one embodiment, the source deposition regions 103 form a two-dimensional array that is separated by a trench-like gate deposition region 102.
In one embodiment, the source deposition region 103 and the surrounding semiconductor are spaced apart by the gate deposition region 102 into a two-dimensional array of cell horizontal cross-sections including, but not limited to, circular, square, and hexagonal.
In a specific embodiment, the thickness of the first barrier layer 4 is 2 nm to 100 nm.
In a specific embodiment, the first barrier layer 4 comprises Al x Ga 1-x N material, wherein X is between 0 and 1, including 0 and 1 itself.
In a specific embodiment, the first channel layer 3 comprises GaN material.
In a specific embodiment, the material of the first channel layer 3 comprises an impurity doping.
In a specific embodiment, the second channel layer 5 comprises GaN material.
In one specific embodiment, the thickness of the second channel layer 5 is 2 nanometers to 10 micrometers.
In one embodiment, the material of the second channel layer 5 comprises an impurity doping.
In a specific embodiment, the thickness of the second barrier layer 6 is 2 nm to 100 nm.
In a specific embodiment, the second barrier layer 6 comprises Al x Ga 1-x N material, wherein X is between 0 and 1, including 0 and 1 itself.
In one embodiment, the gate dielectric 9 is, but is not limited to, siO 2 、SiN、Al 2 O 3 、AlN、HfO 2 And Ga 2 O 3 One or a combination of several of them, the thickness is 0.5 nm to 100 nm.
Compared with the prior art, the compound device has a longitudinal channel combination and a transverse channel combination, and the effect that the total threshold voltage is positive can be achieved by controlling the threshold voltages of the two channels. Specifically, by introducing the second channel layer and the groove-shaped gate deposition region, a path through which electrons flow in a vertical direction through the second channel layer is introduced, thereby introducing a longitudinal channel; meanwhile, under the first barrier layer and the second barrier layer, horizontal two-dimensional electron gas is realized in the first channel layer and the second channel layer, respectively, due to the piezoelectric effect, thereby introducing a lateral channel. The threshold voltages of the two channels are controlled by different crystal orientations and surface states of the channel surfaces.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (14)

1. A mixed channel compound field effect transistor comprises a substrate, and a buffer layer, a first channel layer, a first barrier layer, a second channel layer and a second barrier layer which are sequentially laminated on the substrate;
a groove-shaped grid deposition area penetrating to exceed the lower surface of the second barrier layer but not exceed the lower surface of the first barrier layer is arranged on the upper surface of the second barrier layer, source deposition areas penetrating to not exceed the lower surface of the second barrier layer are respectively arranged on two sides of the grid deposition area, and drain deposition areas penetrating to exceed the lower surface of the second barrier layer but not exceed the lower surface of the first barrier layer from the upper surface of the second barrier layer;
the mixed channel compound field effect transistor further comprises a gate dielectric layer, a gate electrode layer, a source electrode layer and a drain electrode layer, wherein the gate dielectric layer covers the bottom surface and the side surface of the gate electrode deposition area and extends outwards to the upper part of the second barrier layer;
the grid electrode layer extends from the upper part of the grid dielectric layer at one side of the grid electrode deposition area to the upper part of the grid dielectric layer at the other side along the grid dielectric layer;
the source layer and the drain layer extend from the bottom of the source deposition region and the bottom of the drain deposition region, respectively, along respective sides to above the second barrier layer;
wherein a path of electron flow in a vertical direction through the second channel layer is introduced through the second channel layer and the gate deposition region, thereby introducing a longitudinal channel; simultaneously, horizontal two-dimensional electron gas is respectively realized in the first channel layer and the second channel layer, so that a transverse channel is introduced;
the gate electrode layer can control the current in the transverse channel and the longitudinal channel in the second channel layer through the gate dielectric layer by an electric field.
2. The hybrid channel compound field effect transistor of claim 1 having more than one recessed gate deposition region and source deposition region.
3. The hybrid channel compound field effect transistor of claim 1 wherein said source deposition regions are separated by said gate deposition regions in a two-dimensional array.
4. The hybrid channel compound field effect transistor of claim 3, wherein the horizontal cross section of the array elements of the two-dimensional array comprises circular, square, and hexagonal.
5. The hybrid channel compound field effect transistor of claim 1, wherein the first barrier layer has a thickness of 2 nm to 100 nm.
6. The hybrid channel compound field effect transistor of claim 1, wherein the first barrier layer comprises Al x Ga 1-x N material, wherein X is between 0 and 1, including 0 and 1 itself.
7. The hybrid channel compound field effect transistor of claim 1, wherein the first channel layer comprises a GaN material.
8. The hybrid channel compound field effect transistor of claim 1, wherein the material of the first channel layer comprises impurity doping.
9. The hybrid channel compound field effect transistor of claim 1, wherein the second channel layer comprises a GaN material.
10. The hybrid channel compound field effect transistor of claim 1, wherein the thickness of the second channel layer is 2 nanometers to 10 microns.
11. The hybrid channel compound field effect transistor of claim 1, wherein the material of the second channel layer comprises impurity doping.
12. The hybrid channel compound field effect transistor of claim 1, wherein the second barrier layer has a thickness of 2 nm to 100 nm.
13. The hybrid channel compound field effect transistor of claim 1, wherein the second barrier layer comprises Al x Ga 1-x N material, wherein X is between 0 and 1, including 0 and 1 itself.
14. The hybrid channel compound field effect transistor of claim 1, wherein said gate dielectric comprises SiO 2 、SiN、Al 2 O 3 、AlN、HfO 2 And Ga 2 O 3 One or a combination of several of them, the thickness is 0.5 nm to 100 nm.
CN202310371331.5A 2018-06-20 2018-06-20 Mixed channel compound semiconductor device Pending CN116247078A (en)

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JP3303601B2 (en) * 1995-05-19 2002-07-22 日産自動車株式会社 Groove type semiconductor device
US7352036B2 (en) * 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
JP2010135640A (en) * 2008-12-05 2010-06-17 Panasonic Corp Field-effect transistor
US7884394B2 (en) * 2009-02-09 2011-02-08 Transphorm Inc. III-nitride devices and circuits
JP2011176195A (en) * 2010-02-25 2011-09-08 Toshiba Corp Nitride semiconductor device
JP2012114320A (en) * 2010-11-26 2012-06-14 Nippon Telegr & Teleph Corp <Ntt> Nitride semiconductor field effect transistor
WO2014174550A1 (en) * 2013-04-23 2014-10-30 パナソニックＩｐマネジメント株式会社 Nitride semiconductor device
JP6214978B2 (en) * 2013-09-17 2017-10-18 株式会社東芝 Semiconductor device
CN107735863A (en) * 2015-07-01 2018-02-23 香港科技大学 Enhanced double channel HEMT

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