CN116246690A - EEPROM data reliability verification method - Google Patents
EEPROM data reliability verification method Download PDFInfo
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- CN116246690A CN116246690A CN202310319689.3A CN202310319689A CN116246690A CN 116246690 A CN116246690 A CN 116246690A CN 202310319689 A CN202310319689 A CN 202310319689A CN 116246690 A CN116246690 A CN 116246690A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the technical field of data storage, and particularly provides an EEPROM data reliability verification method which is used for judging whether data stored in an EEPROM have unexpected changes or not. The invention comprises the following steps: ECC checking and self-checking functions, and writing the highest address of the EEPROM into a result of CRC calculation on all data; the ECC check includes: ECC encoding and ECC decoding, wherein the ECC encoding encodes and writes data to be written; the ECC decoding performs decoding check on the read data and feeds error information back to the host; the host sends a self-checking request and sequentially reads data from all addresses of the EEPROM, the read data is decoded and checked and then is input into the self-checking module for CRC calculation, if the ECC check result is not wrong and the CRC calculation result is 0, the data is judged to be reliable, otherwise, the data is judged to be unreliable. The invention realizes the verification of EEPROM data reliability by combining ECC verification and self-checking functions, thereby achieving the purpose of improving the system reliability.
Description
Technical Field
The invention belongs to the technical field of data storage, and particularly provides an EEPROM data reliability verification method.
Background
EEPROM refers to an electrified erasable programmable read-only memory, which is a memory device with no data loss after power failure; in electronic system design, it is common to use EEPROM to hold important information such as ID, adjustable parameters, and function switches. However, when abnormal power failure, electromagnetic interference, etc. occur in the process of performing read, write, and erase operations on the EEPROM, errors may occur in the data that is ultimately used.
For the above situation, the existing solutions mainly include: redundant storage, which is to use three or more groups of memories for storage, and to determine correct data according to a few methods subject to majority when the data is taken out, so that a large amount of resources are consumed; the same CRC algorithm (cyclic redundancy check) or ECC algorithm (error checking correction) is used for checking the data read during writing and use, and if the checking result passes, the data is judged to be valid, and the coverage rate of a single algorithm is limited, namely different data can obtain the same checking result.
It is therefore of great importance to implement an EEPROM data reliability verification method to address one or more of the problems described above.
Disclosure of Invention
The invention aims to provide an EEPROM data reliability checking method which is used for judging whether the data stored in an EEPROM has unexpected change or not; according to the method, the verification result is fed back to the host, and the host judges whether the EEPROM storage data is effective or not according to the feedback result, so that the reliability of the system can be improved.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an EEPROM data reliability verification method, comprising: ECC checking and self-checking functions;
the highest address of the EEPROM is used as a self-checking check bit, other addresses are used as data storage bits, and the self-checking check bit is written into the result of CRC calculation on the data in all the data storage bits;
the ECC check includes: ECC encoding and ECC decoding, wherein the ECC encoding encodes the data to be written into the EEPROM, and the ECC encoding result is written into the EEPROM; ECC decoding is carried out on the data read out by the EEPROM, and error information is fed back to the host;
the self-checking function includes: the self-checking module is powered on or any other moment, the host sends a self-checking request and simultaneously sequentially reads data from all addresses of the EEPROM, the read data is input to the self-checking module for CRC calculation after ECC decoding and checking, and whether the data is reliable or not is judged according to a CRC calculation result and an ECC checking result: if the ECC check result is not wrong and the CRC calculation result is 0, the data is judged to be reliable, otherwise, the data is judged to be unreliable.
Further, the ECC encoded input data bit width is equal to the data width of the data to be stored.
Further, the bit width of the self-checking module is equal to the data width of the data to be stored, and the number of the data input by the self-checking module is equal to the address number of the EEPROM.
Further, the sequential data reading operation specifically includes: starting from a low address to a high address of the EEPROM.
Based on the technical scheme, the invention has the beneficial effects that:
the invention provides a EEPROM data reliability checking method, which is characterized in that the written and read EERPOM numbers are respectively encoded and decoded by an ECC algorithm to realize the functions of 2bit error detection and 1bit error correction, and the data stored in the EEPROM is subjected to CRC checking by a self-checking request sent by a host, so that the limitation of insufficient coverage rate of a single algorithm is overcome; finally, the EEPROM data reliability checking method provided by the invention realizes the reliability check of EEPROM storage data and has the advantage of high coverage rate.
In summary, the invention can carry out reliability check on the data stored in the EEPROM, namely, the errors of the data stored in the EEPROM can be found and corrected to a certain extent, and the invention has obvious help to improve the reliability of the system.
Drawings
Fig. 1 is a flow chart of an EEPROM data reliability checking method according to the present invention.
FIG. 2 is a diagram illustrating ECC (8, 5) encoding and decoding according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a calculation flow of a self-check bit (crc_check_sum) according to an embodiment of the present invention.
Fig. 4 is a schematic flow chart of a self-checking function in an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the embodiments and the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
The invention provides a method for checking the reliability of EEPROM data, which comprises the following steps: ECC checking and self-checking functions;
the highest address of the EEPROM is used as a self-checking check bit, other addresses are used as data storage bits, and the self-checking check bit is written into the result of CRC calculation on the data in all the data storage bits;
the ECC check includes: the method comprises the steps of ECC encoding and ECC decoding, wherein the ECC encoding encodes data to be written into the EEPROM, and the ECC encoding result is written into the EEPROM; ECC decoding is carried out on the data read out by the EEPROM (2 bit errors can be checked and 1bit data errors can be corrected), and if 1bit or 2bit errors occur, error information is fed back to the host;
the self-checking function includes: the self-checking module comprises the following specific processes: after the system is powered on or at any other moment, the host sends a self-checking request, and simultaneously sequentially reads data from all addresses of the EEPROM, the read data is firstly subjected to ECC decoding check, and then sequentially input into the self-checking module to carry out CRC calculation, and whether the check passes or not is judged according to a CRC calculation result and an ECC check result: if the ECC check result is not wrong and the CRC calculation result is 0, the data is judged to be reliable (self-checking passing), otherwise, the data is judged to be unreliable (self-checking not passing).
Examples
The method for verifying the reliability of the EEPROM data in the embodiment is realized based on the structure shown in fig. 1, and comprises the following steps: a host, an ECC encoding, EEPROM, EEPROM controller, an ECC decoding and self-checking module; the EEPROM controller receives an EEPROM read-write request from a host and realizes corresponding operation on the EEPROM; in the self-checking process, a host sends a self-checking request to a self-checking module, and simultaneously sends continuous read data requests to an EEPROM controller, the read EEPROM data is firstly decoded by ECC and sent to the self-checking module for CRC calculation, and after the self-checking is finished, the self-checking module feeds back a self-checking result to the host; the ECC encoding module finishes the encoding process of the written data, and the ECC decoding module finishes the decoding detection error correction function of the EEPROM output data and feeds back information to the host.
In one embodiment, the data width to be stored is 8 bits, and the number of addresses of the EEPROM is 16, which corresponds to 0 to F; addresses 0 to E store user data, and address F stores CRC calculation results CRC_CHECKSUM based on the user data; encoding and decoding the stored data by ECC (8, 5), the ECC (8, 5) encoding and decoding process is shown in FIG. 2; the host sends out self-checking request and continuous EEPROM reading request, the self-checking module inputs the data of addresses 0 to F decoded by ECC (8, 5) in EPROM in sequence, and the total number is 16.
In one embodiment, the ECC (8, 5) encoding process is to input 8bit data, encode and output 13bit data, and the decoding process is to input 13bit data, decode and output 8bit data; if a 1bit or 2bit error occurs, the error information is fed back to the host.
In one embodiment, the calculation and writing of the crc_check sum are completed by a user, the data from 0 to E address of the crc_check sum are sequentially input into the CRC8 in order from small to large for calculation, and the calculation process is shown in fig. 3.
In one embodiment, the self-checking module CRC8 calculates that the output is 0 and the ECC decoding module is not in error, so that the probability of data change after power failure is small, the data reliability is high, and the self-checking is passed; otherwise, after power failure, the data is changed, the data is unreliable, and the self-test is failed; the flow of the self-test is shown in fig. 4.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (4)
1. An EEPROM data reliability verification method, comprising: ECC checking and self-checking functions;
the highest address of the EEPROM is used as a self-checking check bit, other addresses are used as data storage bits, and the self-checking check bit is written into the result of CRC calculation on the data in all the data storage bits;
the ECC check includes: the method comprises the steps of ECC encoding and ECC decoding, wherein the ECC encoding encodes data to be written into the EEPROM, and the ECC encoding result is written into the EEPROM; ECC decoding is carried out on the data read out by the EEPROM, and error information is fed back to the host;
the self-checking function includes: the self-checking module is powered on or any other moment, the host sends a self-checking request and simultaneously sequentially reads data from all addresses of the EEPROM, the read data is input to the self-checking module for CRC calculation after ECC decoding and checking, and whether the data is reliable or not is judged according to a CRC calculation result and an ECC checking result: if the ECC check result is not wrong and the CRC calculation result is 0, the data is judged to be reliable, otherwise, the data is judged to be unreliable.
2. The EEPROM data reliability verification method of claim 1, characterized in that the ECC encoded input data bit width is equal to the data width of the data to be stored.
3. The method for verifying the reliability of EEPROM data according to claim 1, wherein the bit width of the self-checking module is equal to the data width of the data to be stored, and the number of the data inputted by the self-checking module is equal to the address number of the EEPROM.
4. The EEPROM data reliability verification method of claim 1, characterized in that the sequential data reading operations are specifically: starting from a low address to a high address of the EEPROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310319689.3A CN116246690A (en) | 2023-03-28 | 2023-03-28 | EEPROM data reliability verification method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310319689.3A CN116246690A (en) | 2023-03-28 | 2023-03-28 | EEPROM data reliability verification method |
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| CN116246690A true CN116246690A (en) | 2023-06-09 |
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| CN202310319689.3A Pending CN116246690A (en) | 2023-03-28 | 2023-03-28 | EEPROM data reliability verification method |
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