CN116233036B - DMA transmission control method and device - Google Patents
DMA transmission control method and device Download PDFInfo
- Publication number
- CN116233036B CN116233036B CN202310242771.0A CN202310242771A CN116233036B CN 116233036 B CN116233036 B CN 116233036B CN 202310242771 A CN202310242771 A CN 202310242771A CN 116233036 B CN116233036 B CN 116233036B
- Authority
- CN
- China
- Prior art keywords
- priority
- register
- buffer block
- information
- indication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000013507 mapping Methods 0.000 claims abstract description 37
- 238000012546 transfer Methods 0.000 claims description 30
- 230000009286 beneficial effect Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003139 buffering effect Effects 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000012217 deletion Methods 0.000 description 2
- 230000037430 deletion Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9005—Buffering arrangements using dynamic buffer space allocation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer And Data Communications (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a DMA transmission control method and a device, wherein the method comprises the following steps: when receiving the message information, acquiring the priority of the message information; searching an idle buffer block in a buffer block queue, storing the message information into the searched idle buffer block, and recording a buffer block index number corresponding to the message information; determining a target position of the message information in an indication queue of a priority register based on the priority of the message information, and filling a buffer block index number of the message information in a corresponding indication bit in a block index register so that the priority register, the block index register and the buffer block form a mapping relation; when the DMA uploads the message information, the DMA is controlled to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and the mapping relation between the priority indication queue and the index number of each buffer block. The invention can rapidly and preferentially transmit the data with high priority, and is beneficial to alleviating the influence of time delay on data transmission.
Description
Technical Field
The present invention relates to the field of network communications, and in particular, to a DMA transmission control method and apparatus.
Background
The TSN (time sensitive network) is increasingly applied, and many fields such as high-end industrial pipelines, high-speed railway control systems, aircraft control systems, automobile control systems, 5G front-end transmission and the like need time sensitive transmission.
DMA (direct memory access) transfer is a very mature memory access control technology, and DMA transfer is very commonly applied in ethernet, and data transfer is performed through an independent DMA controller, so that the overhead of master control can be greatly reduced.
At present, most DMA transmissions are sequential transmissions at the device end, mainly through two modes: (1) The DMA controller performs actual transmission by setting the address and the length through the main control. The equipment sequentially stores the received data in the internal buffer, then notifies the main control through interruption, the main control reads the corresponding register to acquire the length, and finally the DMA controller is arranged to transmit the actual data; (2) The main control divides the memory buffer into a plurality of blocks, and gathers the corresponding description information into a plurality of descriptors, and independently acquires the descriptors when the DMA controller needs to transmit each time, and transmits the device data to the memory buffer appointed by the descriptors. From the device side, this approach still uses buffering inside the device sequentially.
The internal sequence of the device uses buffering, which is not problematic in normal applications, but affects latency in time sensitive applications. The messages with high priority and definite requirements on delay are mixed in the common messages, and cannot be transmitted preferentially, so that the delay is uncertain. This uncertainty is mainly limited by the buffering of the device itself, the larger the buffering the greater the delay uncertainty. Because the transmission bandwidth of the existing network is larger and larger, in order to adapt to the large bandwidth, data is not lost as much as possible, the buffer of the equipment is also larger, and the influence of corresponding delay is also larger.
Disclosure of Invention
In order to solve the technical problems, the invention provides a DMA transmission control method and a device.
Specifically, the technical scheme of the invention is as follows:
in one aspect, the present invention provides a DMA transfer control method, including:
when receiving message information, acquiring the priority of the message information;
searching an idle buffer block in a buffer block queue, and storing the message information into the searched idle buffer block; recording the buffer block index number corresponding to the message information;
determining a target position of the message information in an indication queue of a priority register based on the priority of the message information, and filling a buffer block index number of the message information in a corresponding indication bit in a block index register so that the priority register, the block index register and a buffer block form a mapping relation;
When the DMA uploads the message information, the DMA is controlled to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and the mapping relation between the priority indication queue and the index number of each buffer block.
In some embodiments, the searching for an idle buffer block in the buffer block queue stores the message information into the searched idle buffer block; comprising the following steps:
acquiring the length information of the message information, and writing the length information into a corresponding indicating bit in a length indicating register;
searching a target idle buffer block according to the idle indicating bit information of each buffer block;
acquiring and recording an index number of the target idle buffer block; so that the index number of the target idle buffer block is stored in the corresponding indication bit in the block index register;
storing the message information into the target idle buffer block, and updating a storage state of a corresponding indication bit in a storage completion indication register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
In some embodiments, when the DMA uploads the message information, the DMA is controlled to transmit the message information in the corresponding buffer block to the upper host according to the order of the priority indication queue and the mapping relationship between the priority indication queue and the index number of each buffer block, including:
Judging whether the storage of the message corresponding to the first indication bit in the priority queue is finished or not according to the priority queue sequence in the priority register and combining the corresponding relation between the priority register and the storage finishing indication register;
when the fact that the message storage corresponding to the first indication bit in the priority queue is completed is judged, the first indication bit in the priority queue is used as a target indication bit;
when judging that the message storage corresponding to the first indicating bit in the priority queue is not completed, continuing to judge whether the message storage of the next indicating bit in the priority queue is completed or not until the indicating bit with completed storage is found out as a target indicating bit;
acquiring a target buffer block address corresponding to a target indication bit in the priority queue according to the corresponding relation between the priority register and the block index register;
controlling the DMA to transmit the message information stored in the target buffer block to an upper host according to the target buffer block address;
after the transmission is completed, the corresponding storage completion indication register, length register, priority register and block index register are all moved forward by one position, and the idle indication bit information of the buffer block for which the transmission is completed is set as idle information.
In some embodiments, the acquiring the priority of the message information includes: identifying port information in the message information; inquiring the port information in a pre-constructed priority list, and acquiring the priority of the message information matched with the port information.
In some embodiments, further comprising: receiving priority information issued by a priority server in a local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information; and generating a priority list according to the priority information.
In another aspect, the present invention provides a DMA transfer control apparatus, including:
the acquisition module is used for acquiring the priority of the message information when the message information is received;
the storage module is used for searching an idle buffer block in the buffer block queue and storing the message information into the searched idle buffer block; recording the buffer block index number corresponding to the message information;
the index module is used for determining the target position of the message information in the indication queue of the priority register based on the priority of the message information, and filling the buffer block index number of the message information in the corresponding indication bit in the block index register so that the priority register, the block index register and the buffer block form a mapping relation;
And the transmission module is used for controlling the DMA to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and the mapping relation between the priority indication queue and the index number of each buffer block when the DMA uploads the message information.
In some embodiments, the memory module comprises:
the first acquisition unit is used for acquiring the length information of the message information and writing the length information into a corresponding indicating bit in a length indicating register;
the first searching unit is used for searching the target idle buffer block according to the idle indicating bit information of each buffer block;
the second acquisition unit is used for acquiring and recording the index number of the target idle buffer block; so that the index number of the target idle buffer block is stored in the corresponding indication bit in the block index register;
the storage unit is used for storing the message information into the target idle buffer block and updating the storage state of the corresponding indication bit in the storage completion indication register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
In some embodiments, the indexing module comprises:
the judging unit is used for judging whether the storage of the message corresponding to the first indication bit in the priority queue is finished or not according to the priority queue sequence in the priority register and the corresponding relation between the priority register and the storage finishing indication register;
the judging unit is further configured to, when judging that the storage of the message corresponding to the first indication bit in the priority queue is completed, use the first indication bit in the priority queue as a target indication bit;
the judging unit is further configured to, when judging that the message storage corresponding to the first indication bit in the priority queue is not completed, continue to judge whether the message storage of the next indication bit in the priority queue is completed or not until the indication bit with completed storage is found as the target indication bit;
a third obtaining unit, configured to obtain a target buffer block address corresponding to a target indication bit in the priority queue according to a correspondence between the priority register and the block index register;
the transmission unit is used for controlling the DMA to transmit the message information stored in the target buffer block to an upper host according to the target buffer block address;
And the setting unit is used for shifting the corresponding storage completion indication register, the length register, the priority register and the block index register by one position and setting the idle indication bit information of the buffer block which completes transmission as idle information after the transmission is completed.
In some embodiments, the acquisition module includes: the identification unit is used for identifying port information in the message information; and the query unit is used for querying the port information in a pre-constructed priority list and acquiring the priority of the message information matched with the port information.
In some embodiments, further comprising: the receiving module is used for receiving the priority information issued by the priority server in the local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information; and the generating module is used for generating a priority list according to the priority information.
Compared with the prior art, the invention has at least one of the following beneficial effects:
(1) The invention can transmit the data with high priority to the upper host according to the priority of the data at the equipment end of message transmission. Compared with the prior DMA executing sequence transmission at the equipment end, the invention is beneficial to improving the data transmission rate with high priority and is more suitable for the transmission network with high requirement on data transmission delay.
(2) The invention can avoid complex buffer management, the buffer block storing a large amount of data in the buffer area does not need to be moved, and the data transmission is carried out according to the priority order by indicating the shift of the registers and the mapping relation among the registers.
(3) The invention can realize the dynamic management of the priority, can establish the priority list without the intervention of upper application according to the priority information received in real time, and can dynamically adjust the priority list in real time for judging the priority of the message information.
(4) Because the transmission bandwidth of the existing network is larger and larger, in order to adapt to the large bandwidth, data is not lost as much as possible, and the buffer of the equipment is also larger, the influence on delay is correspondingly increased. The invention is beneficial to solving the problem of delay uncertainty caused by overlarge self-buffering of the equipment and leading message data with clear requirements on delay to be transmitted preferentially.
(5) In the invention, for the acquisition determination of the priority, after the information message MAC header is acquired, the IP message is confirmed, the IP header continues to confirm the TCP message, the TCP port is further acquired, then the priority level of the acquired information message is determined according to the priority list constructed by the priority information transmitted in advance by the priority server, and the priority information is issued by the priority server in the local area network, so that when the priority is updated, the priority order can be freely modified by the priority server, more flexible priority setting is realized, and the priority is not felt and transparent to the host of the upper layer, and the control part of the upper layer is changed as little as possible.
Drawings
The above features, technical features, advantages and implementation of the present application will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a flow chart of one embodiment of a DMA transfer control method of the present application;
FIG. 2 is a diagram illustrating a process for determining a message destination in one embodiment of a DMA transfer control method according to the present application;
FIG. 3 is a flow chart of another embodiment of a DMA transfer control method of the present application;
FIG. 4 is a diagram illustrating a message storage process according to the present application;
FIG. 5 is a schematic diagram of a priority network in accordance with the present application;
FIG. 6 is a block diagram of one embodiment of a DMA transfer control apparatus of the present application;
fig. 7 is a schematic diagram of a message transmission completion according to an embodiment of the present application.
Reference numerals illustrate:
the device comprises an acquisition module 10, a storage module 20, an indexing module 30 and a transmission module 40.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
DMA (direct memory access) transfer is a very mature method of memory access, which copies data from one address space to another, providing high speed data transfer between peripheral and memory or between memory and memory. The DMA transmission mode does not need a CPU to directly control transmission, the transmission action is realized and completed by the DMA controller, and the data transmission is not performed by the CPU but is performed through an independent DMA transmission channel.
In one embodiment of the present application, referring to fig. 1 of the drawings, a DMA transfer control method is applied to a terminal layer, and includes the steps of:
s101, when receiving the message information, acquiring the priority of the message information.
Specifically, in conventional message transmission, a sequential transmission mode is often adopted, that is, the priority of the messages is not differentiated, and the messages are sequentially sent to an upper host according to the sequence of receiving the messages. In the scheme, when the terminal receives the message information, the terminal can acquire the priority of the message information, so that the DMA can transmit the message information according to the priority.
S102, searching an idle buffer block in a buffer block queue, and storing message information into the searched idle buffer block; and recording the buffer block index number corresponding to the message information.
Specifically, a certain storage space is reserved in the memory space of the terminal, and the storage space is used for temporarily storing input or output data, and the reserved space is a buffer zone, wherein the buffer zone comprises a plurality of buffer blocks to form a buffer block queue. When the buffer block stores data, the buffer block is occupied; otherwise, the buffer block is an idle buffer block. The received message information is stored by the free buffer block, and generally, one message information is stored in one buffer block.
The number of buffer blocks in the buffer queue is limited, in order to fully utilize the buffer blocks, before the message storage, whether an idle buffer block exists in the current buffer queue is required to be judged, and if yes, the message information is stored in the idle buffer block; otherwise, waiting is needed until an idle buffer block appears in the buffer queue.
S103, determining the target position of the message information in an indication queue of the priority register based on the priority of the message information, and filling buffer block index numbers of the message information in corresponding indication bits in the block index register so that the priority register, the block index register and the buffer blocks form a mapping relation.
Specifically, the priority register includes a plurality of indication bits for indicating priorities of different message information. The indication bits indicating the same priority form indication sub-queues, and each indication bit in each indication sub-queue is arranged according to the entering sequence of the message; the different indication sub-queues are arranged according to the priority, so as to form a priority indication queue.
The target position, i.e. the position of the priority indication bit corresponding to one message information in the priority indication queue, is usually the tail of the corresponding indication sub-queue. The determination of the target position is achieved by a register shift. For example, setting "0" as the highest priority, the higher the number from "0" is, the lower the corresponding priority, and when a message with priority "2" is entered, the target position of the message in the priority indication queue is shown in fig. 2, that is, the tail of the indication sub-queue with priority "2". The indicator bits with priority "3" are all shifted back by one bit, while the other indicator bits stay in place. At this point, the priority indication queue is left empty by one bit, and priority "2" is then inserted into that position.
When the target position is determined, buffer block index numbers of message information are filled in corresponding indication bits in the block index register, so that a one-to-one mapping relation is formed between the priority register and the block index register. Similarly, the block index register also includes a plurality of indication bits, in which the buffer block index number of the message information is recorded, for indicating the address of the buffer block storing the message information. The block index indicating bits are in one-to-one correspondence with the buffer blocks, so that a mapping relationship is formed between the block index registers and the buffer blocks. Finally, a mapping relation about message information is formed among the priority register, the block index register and the buffer block, so that DMA (direct memory access) can conveniently transmit data according to the mapping relation when transmitting the data, and the transmission rate is improved.
And S104, when the DMA uploads the message information, controlling the DMA to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and combining the mapping relation between the priority indication queue and the index number of each buffer block.
Specifically, since there is a mapping relationship among the priority register, the block index register and the buffer block, each indicating bit in the priority indicating queue also forms a mapping relationship with the buffer block index number. The transmission sequence of the message information can be obtained by indicating the sequence of the queues through the priority, and the buffer blocks for storing the message information to be transmitted can be accurately positioned by combining the mapping relation.
In this embodiment, first, the transmission priority of the message information is obtained, the message information is stored in the corresponding idle buffer block, and the message information is sent to the upper host by forming a mapping relationship among the priority register, the block index register and the buffer block. Compared with the conventional message transmission method, the scheme can further improve the transmission rate and reduce the influence of delay on the transmission process during message transmission, and is particularly suitable for transmission networks with high delay requirements.
Referring to fig. 3 of the drawings, referring to an embodiment of the present invention, a DMA transfer control method includes the steps of:
s201, when receiving the message information, acquiring the priority and length information of the message information.
S202 writes the length information to the corresponding indicator bit in the length indicator register.
Specifically, the length indication register includes a plurality of indication bits, which are used for indicating the length of the message information, so that the upper host is convenient to receive the message with the corresponding length. The length indication bit of each message information corresponds to the priority indication bit of the message information in the priority register.
S203, searching a target idle buffer block according to the idle indicating bit information of each buffer block.
Specifically, for example, whether the buffer block is idle is indicated by a bit, 1bit indicates that the corresponding buffer block is occupied, and 0bit indicates that the corresponding buffer block is an idle buffer block. In the buffer block queue, there are a plurality of idle buffer blocks, and one idle buffer block is arbitrarily selected as a target idle buffer block.
S204, acquiring and recording an index number of a target idle buffer block; so that the corresponding indication bits in the block index register store the index number of the target free buffer block.
Specifically, in order to quickly find a corresponding buffer block storing the message information when the message information is subsequently sent, the address (index number) of the target idle buffer block is recorded in the block index register. The block index indicator bit of each message information corresponds to the priority indicator bit of the message information in the priority register.
S205, storing the message information into a target idle buffer block, and updating a storage state by a corresponding indication bit in a storage completion indication register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
Specifically, after the storage of the message information is completed, the storage state of the message information is updated by the indication bit in the storage completion register, and the storage state indication bit of each message information corresponds to the priority indication bit of the message information in the priority register. Because the priority indicating bit and the length indicating bit, the storage state indicating bit and the block index indicating bit form a corresponding relation, the priority register, the length indicating register, the storage completion indicating register and the block index register are also in one-to-one corresponding mapping relation.
S206, determining the target position of the message information in the indication queue of the priority register based on the priority of the message information, and filling the buffer block index number of the message information in the corresponding indication bit in the block index register so as to enable the priority register, the block index register and the buffer block to form a mapping relation.
And S207, when the DMA uploads the message information, controlling the DMA to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and combining the mapping relation between the priority indication queue and the index number of each buffer block.
The embodiment further describes a process of storing the message information, and the scheme utilizes the mapping relation among the registers, when the message information is sent, the corresponding buffer block for storing the message information can be found accurately according to the priority information in the priority indicating bit, and the message information in the buffer block is transmitted to the upper host.
In one embodiment, acquiring the priority of the message information includes: identifying port information in the message information; inquiring port information in a pre-constructed priority list, and acquiring the priority of message information matched with the port information. Specifically, in network transmission, a transmission port is generally used as a basis for judging priority. Therefore, when a message enters the terminal, the message information is identified, and the corresponding port information is extracted. The priority list includes various transmission ports and priorities corresponding to each transmission port. And searching the priority matched with the port information of the message in the priority list according to the port information.
In one embodiment, step S208 includes:
s208-1 judges whether the storage of the message corresponding to the first indication bit in the priority queue is completed according to the priority queue sequence in the priority register and by combining the corresponding relation between the priority register and the storage completion indication register, and if the storage is completed, step S208-2 is executed; otherwise, step S208-3 is performed.
Specifically, the priority register comprises a plurality of indication bits, the indication bits indicating the same priority form indication sub-queues, and each indication bit in each indication sub-queue is arranged according to the sequence of entering the message; the different indication sub-queues are arranged according to the priority, and the arrangement order of the indication sub-queues is the priority queue order.
And during transmission, the message information corresponding to each priority indication bit is sequentially uploaded to an upper host according to the priority queue order. It should be noted that there may be a case where the message information is not stored before transmission, but the priority of the message information is already included in the priority queue. As shown in fig. 4, the storage status indication bits corresponding to the message information with the lengths of "0xF7" and "0xA9" are respectively 1, which indicates that the two messages are stored, but the storage status indication bit corresponding to the message information with the length of "0x85" is 0, that is, the message information is not yet stored. However, the priority "0" corresponding to the message information with the length of "0x85" is already written into the priority register through the priority indicating bit, so as to form a priority queue. According to the current priority queue order, message information with the length of 0xF7, 0x85 and 0xA9 is transmitted in sequence during transmission, but the message with the length of 0x85 is not stored, so that during actual transmission, the message information with the length of 0xF7 is sent to an upper host, and then the message information with the length of 0xA9 is uploaded.
S208-2 takes the first indication bit in the priority queue as the target indication bit, and step S208-4 is executed.
S208-3 continues to judge whether the message storage of the next indicating bit in the priority queue is completed, if not, step S208-3 is repeatedly executed until the indicating bit of which storage is completed is found as the target indicating bit, and step S208-4 is executed.
S208-4, according to the corresponding relation between the priority register and the block index register, obtaining the target buffer block address corresponding to the target indication bit in the priority queue.
Specifically, after the target indication bit is determined, because of the corresponding relation between the priority register and the block index register, a corresponding buffer block index number can be obtained through the target indication bit, and the target buffer block for storing the message information can be directly positioned through the index number.
S208-5, according to the address of the target buffer block, controlling the DMA to transmit the message information stored in the target buffer block to the upper host.
S208-6, after the transmission is completed, the corresponding storage completion indication register, the length register, the priority register and the block index register are all moved forward by one position, and the idle indication bit information of the buffer block for completing the transmission is set as idle information.
In the scheme, the buffer block for storing the message data does not need to be moved, and the management of the message data is realized by indicating the displacement of various registers. It should be noted that the shifting of all registers is a hardware level operation and is mutually exclusive, i.e. the insertion of a received message and the deletion of the end of transmission cannot be performed simultaneously.
In one embodiment, on the basis of any one of the above embodiments, the method further includes: receiving priority information issued by a priority server in a local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information; and generating a priority list according to the priority information.
Specifically, in network transmission, a transmission port is generally used as a basis for judging priority. The priority server determines priorities corresponding to various port information according to preset port rules, and then distributes the priority information to the terminal through the priority server. After receiving the priority information, the terminal does not need to upload to an upper host, but directly processes the priority information, and generates a priority list in the terminal.
Further, when there are a plurality of terminals, as shown in fig. 5, the terminals are chip terminals, and priority information is sent to each chip terminal through a priority server. Each chip end can dynamically construct own priority queue, and an upper host can completely avoid any operation, and all changes of priority are transparent to the upper host, so that a priority network irrelevant to upper application is logically formed.
Referring to fig. 6 of the drawings, a DMA transfer control apparatus according to an embodiment of the present invention includes an acquisition module 10, a storage module 20, an index module 30, and a transfer module 40, where:
the acquiring module 10 is configured to acquire the priority of the message information when the message information is received.
The storage module 20 is configured to search for an idle buffer block in the buffer block queue, and store the message information into the searched idle buffer block; and recording the buffer block index number corresponding to the message information.
The indexing module 30 is configured to determine, based on the priority of the message information, a target position of the message information in the indication queue of the priority register, and fill a buffer block index number of the message information in a corresponding indication bit in the block index register, so that the priority register, the block index register, and the buffer block form a mapping relationship.
And the transmission module 40 is used for controlling the DMA to transmit the message information in the corresponding buffer blocks to the upper host according to the sequence of the priority indication queue and the mapping relation between the priority indication queue and the index numbers of each buffer block when the DMA uploads the message information.
In this embodiment, the acquiring module acquires the transmission priority of the message information, the storage module stores the message information into the corresponding idle buffer block, then the index module forms a mapping relationship among the priority register, the block index register and the buffer block, and finally the transmission module sends the message information to the upper host. Compared with the conventional message transmission method, the scheme can further improve the transmission rate and reduce the influence of delay on the transmission process during message transmission, and is particularly suitable for transmission networks with high delay requirements.
In one embodiment, the acquisition module 20 includes: the identification unit is used for identifying port information in the message information; and the inquiring unit is used for inquiring the port information in the pre-constructed priority list and acquiring the priority of the message information matched with the port information.
In one embodiment, the storage module 20 includes a first acquisition unit 21, a first lookup unit 22, a second acquisition unit 23, and a storage unit 24, wherein:
the first obtaining unit 21 is configured to obtain length information of the message information, and write the length information into a corresponding indicator bit in the length indicator register.
The first searching unit 22 is configured to search for a target idle buffer block according to the idle indicator bit information of each buffer block.
A second obtaining unit 23, configured to obtain and record an index number of the target idle buffer block; so that the corresponding indication bits in the block index register store the index number of the target free buffer block,
a storage unit 24, configured to store the message information into the target idle buffer block, and update the storage state of the corresponding indicator bit in the storage completion indicator register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
According to the scheme, when the message information is sent, the mapping relation among the registers is utilized, the corresponding buffer block for storing the message information can be found accurately according to the priority information in the priority indicating bit, and the message information in the buffer block is transmitted to an upper host.
In one embodiment, the index module 30 includes a judging unit 31, a third acquiring unit 32, a transmitting unit 33, and a setting unit 34, wherein:
and the judging unit 31 is configured to judge whether the storage of the message corresponding to the first indication bit in the priority queue is completed according to the priority queue sequence in the priority register and in combination with the corresponding relationship between the priority register and the storage completion indication register.
The judging unit 31 is further configured to, when it is determined that the storing of the message corresponding to the first indication bit in the priority queue is completed, take the first indication bit in the priority queue as the target indication bit.
And the judging unit 31 is further configured to, when it is determined that the message storage corresponding to the first indication bit in the priority queue is not completed, continue to determine whether the message storage of the next indication bit in the priority queue is completed, until the indication bit for completing the storage is found as the target indication bit.
Specifically, the priority register comprises a plurality of indication bits, the indication bits indicating the same priority form indication sub-queues, and each indication bit in each indication sub-queue is arranged according to the sequence of entering the message; the different indication sub-queues are arranged according to the priority, and the arrangement order of the indication sub-queues is the priority queue order. According to the priority queue order and the message information corresponding to each priority indication bit is transmitted, before transmission, whether the message information is stored is judged, and only the stored message can be sent to an upper host computer, so that data loss is avoided, and the stability and safety of the data transmission process are improved.
A third obtaining unit 32 that obtains a target buffer block address corresponding to the target indication bit in the priority queue according to the correspondence between the priority register and the block index register;
a transmission unit 33, configured to control the DMA to transmit the message information stored in the target buffer block to the upper host according to the target buffer block address;
and a setting unit 34, configured to, after the transmission is completed, advance all the corresponding storage completion indication register, length register, priority register, and block index register by one position, and set the idle indication bit information of the buffer block for which the transmission is completed to idle information.
According to the embodiment, the management of the message data is realized by indicating the displacement of various registers without operating the buffer block for storing the message, so that complex buffer management can be avoided, the operation is simple and convenient, and the stability and the safety of the data transmission process are improved.
In one embodiment, on the basis of any one of the apparatus embodiments above, the method further includes: the receiving module is used for receiving the priority information issued by the priority server in the local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information; and the generating module is used for generating a priority list according to the priority information.
In this embodiment, the priority list may be dynamically established, and a priority network may be formed between the terminal and the server, which is beneficial to flexibly setting the priority. Meanwhile, in the scheme, the terminal directly constructs a priority list according to the priority information sent by the server, the change of the priority is transparent to the upper-layer host, but the upper-layer application does not need to perform operation related to the priority.
It should be noted that, the embodiments of the DMA transfer control apparatus provided by the present invention and the embodiments of the DMA transfer control method provided by the present invention are both based on the same inventive concept, and can achieve the same technical effects. Thus, the other specific contents of the embodiment of the DMA transfer control apparatus can be referred to the description of the embodiment contents of the DMA transfer control method described above.
The invention also provides a specific application scene embodiment, and the message transmission method provided by the invention is applied to the DMA transmission process based on the time-sensitive network standard.
The time sensitive network (TimeSensitiveNetworking, TSN) standard defines a time sensitive mechanism for ethernet data transmission, adding certainty and reliability to the standard ethernet to ensure that the ethernet can provide a consistent and consistent level of service for critical data transmission. The improvement on TSN is concentrated on the exchanger, and in the scheme, the improvement is carried out at the terminal level, the transmission process between the terminal and the upper host is further optimized, and the transmission rate is improved. The following describes a case when the terminal is a chip.
First, a priority identification mechanism is added on the chip. The chip acquires the priority of the message according to the port of the message while receiving the message, and if the priority is high, the chip inserts the message; if the message is a common message, the messages are placed in sequence. The specific operation steps are as follows:
(1.0) waiting for a message, and transferring (1.1) when the message enters;
(1.1) searching for an idle bit, discarding if the idle bit is not available, and turning to (1.0);
(1.2) finding a free bit, storing data into a corresponding free storage block, setting a free bit indication to 1, recording a corresponding buffer block address, and turning to (1.3);
(1.3) in the process of message transmission, acquiring port information of the message, judging the priority of the message, and if the message is not a TCP message, defaulting to be low priority; if the message is a TCP message, judging the priority according to the port rule. If low priority, go to (1.4); if high priority, go to (1.5);
(1.4) directly filling priorities into the tail parts of the priority indication queues, simultaneously filling recorded buffer block index numbers at block indexes at corresponding positions, and turning to (1.6);
(1.5) filling priorities at the tail end of the high priority queue, all subsequent priority registers are sequentially moved back by one position, meanwhile, filling recorded buffer block index numbers at block indexes of corresponding positions, all subsequent block index record registers are sequentially moved back by one position, and turning (1.6).
And (1.6) continuing to store data, after the message is stored, updating the state at the corresponding storage completion register to be 1, and turning to (1.0).
As shown in fig. 7, when the message with priority 0 and length 0x85 is stored, the next transmission is waited, when the DMA is ready for transmission, the operation steps are as follows:
(2.0) if the corresponding first storage completion indication is 1, turning to (2.1);
(2.1) locating the corresponding buffer block address according to the first block index register, and turning to (2.2);
(2.2) starting data transmission until the end, and turning to 2.3;
(2.3) moving all the corresponding storage completion indication register, the length indication register, the priority indication register and the block index register forward by one position, and turning to 2.4;
(2.4) setting the idle indication corresponding to the block completing the transmission to 0, and turning to 2.0.
The idle indication is a bit indication, and one bit is used for indicating whether a storage block is idle, and the idle indication is in one-to-one correspondence with the buffer block. For the hardware to be able to process quickly, the priority indication register, the length indication register, the storage completion register and the block index register are mutually corresponding to each other.
It should be noted that, in this embodiment, the shifting of all registers is a hardware level operation and is mutually exclusive, i.e. the insertion of a received message and the deletion of a message at the end of transmission cannot be performed simultaneously. In this embodiment, although the priorities are set only for the high priority and the low priority, in practice, it is possible to construct a multi-priority, in the operations of (1.4) and (1.5), not simply arranged at the end of the priority instruction queue or the end of the insertion high priority section, but the end of the corresponding priority sequence needs to be inserted from the beginning to the end.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A DMA transfer control method, applied to a terminal layer, comprising:
when receiving message information, acquiring the priority of the message information;
searching an idle buffer block in a buffer block queue, and storing the message information into the searched idle buffer block; recording the buffer block index number corresponding to the message information;
determining a target position of the message information in an indication queue of a priority register based on the priority of the message information, and filling a buffer block index number of the message information in a corresponding indication bit in a block index register so that the priority register, the block index register and a buffer block form a mapping relation;
when the DMA uploads the message information, the DMA is controlled to transmit the message information in the corresponding buffer block to an upper host according to the sequence of the priority indication queue and the mapping relation between the priority indication queue and the index number of each buffer block.
2. The DMA transfer control method according to claim 1, wherein searching for an idle buffer block in the buffer block queue, storing the message information in the searched idle buffer block, comprises:
acquiring the length information of the message information, and writing the length information into a corresponding indicating bit in a length indicating register;
searching a target idle buffer block according to the idle indicating bit information of each buffer block;
acquiring and recording an index number of the target idle buffer block; so that the index number of the target idle buffer block is stored in the corresponding indication bit in the block index register;
storing the message information into the target idle buffer block, and updating a storage state of a corresponding indication bit in a storage completion indication register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
3. The method for controlling DMA transfer according to claim 2, wherein when the DMA uploads the message information, controlling the DMA to transfer the message information in the corresponding buffer block to the host at the upper layer according to the order of the priority indication queue in combination with the mapping relationship between the priority indication queue and the index number of each buffer block, comprises:
Judging whether the storage of the message corresponding to the first indication bit in the priority queue is finished or not according to the priority queue sequence in the priority register and combining the corresponding relation between the priority register and the storage finishing indication register;
when the fact that the message storage corresponding to the first indication bit in the priority queue is completed is judged, the first indication bit in the priority queue is used as a target indication bit;
when judging that the message storage corresponding to the first indicating bit in the priority queue is not completed, continuing to judge whether the message storage of the next indicating bit in the priority queue is completed or not until the indicating bit with completed storage is found out as a target indicating bit;
acquiring a target buffer block address corresponding to a target indication bit in the priority queue according to the corresponding relation between the priority register and the block index register;
controlling the DMA to transmit the message information stored in the target buffer block to an upper host according to the target buffer block address;
after the transmission is completed, the corresponding storage completion indication register, length register, priority register and block index register are all moved forward by one position, and the idle indication bit information of the buffer block for which the transmission is completed is set as idle information.
4. The DMA transfer control method according to claim 1, wherein said obtaining the priority of the message information comprises:
identifying port information in the message information;
inquiring the port information in a pre-constructed priority list, and acquiring the priority of the message information matched with the port information.
5. The DMA transfer control method according to any one of claims 1 to 4, further comprising:
receiving priority information issued by a priority server in a local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information;
and generating a priority list according to the priority information.
6. A DMA transfer control apparatus, applied to a terminal layer, comprising:
the acquisition module is used for acquiring the priority of the message information when the message information is received;
the storage module is used for searching an idle buffer block in the buffer block queue and storing the message information into the searched idle buffer block; recording the index number of the buffer block corresponding to the message information;
the index module is used for determining the target position of the message information in the indication queue of the priority register based on the priority of the message information, and filling the buffer block index number of the message information in the corresponding indication bit in the block index register so that the priority register, the block index register and the buffer block form a mapping relation;
And the transmission module is used for controlling the DMA to transmit the message information in the corresponding buffer block to the host at the upper layer according to the sequence of the priority indication queue and the mapping relation of the priority indication queue and the index number of each buffer block when the DMA uploads the message information.
7. The DMA transfer control apparatus according to claim 6, wherein the memory module comprises:
the first acquisition unit is used for acquiring the length information of the message information and writing the length information into a corresponding indicating bit in a length indicating register;
the first searching unit is used for searching the target idle buffer block according to the idle indicating bit information of each buffer block;
the second acquisition unit is used for acquiring and recording the index number of the target idle buffer block; so that the index number of the target idle buffer block is stored in the corresponding indication bit in the block index register;
the storage unit is used for storing the message information into the target idle buffer block and updating the storage state of the corresponding indication bit in the storage completion indication register after the storage is completed; the priority register, the length indication register, the storage completion indication register and the block index register are in one-to-one mapping relation.
8. The DMA transfer control apparatus according to claim 7, wherein the index module comprises:
the judging unit is used for judging whether the storage of the message corresponding to the first indication bit in the priority queue is finished or not according to the priority queue sequence in the priority register and the corresponding relation between the priority register and the storage finishing indication register;
the judging unit is further configured to, when judging that the storage of the message corresponding to the first indication bit in the priority queue is completed, use the first indication bit in the priority queue as a target indication bit;
the judging unit is further configured to, when judging that the message storage corresponding to the first indication bit in the priority queue is not completed, continue to judge whether the message storage of the next indication bit in the priority queue is completed or not until the indication bit with completed storage is found as the target indication bit;
a third obtaining unit, configured to obtain a target buffer block address corresponding to a target indication bit in the priority queue according to a correspondence between the priority register and the block index register;
the transmission unit is used for controlling the DMA to transmit the message information stored in the target buffer block to an upper host according to the target buffer block address;
And the setting unit is used for shifting the corresponding storage completion indication register, the length register, the priority register and the block index register by one position and setting the idle indication bit information of the buffer block which completes transmission as idle information after the transmission is completed.
9. The DMA transfer control apparatus according to claim 7, wherein the acquisition module comprises:
the identification unit is used for identifying port information in the message information;
and the query unit is used for querying the port information in a pre-constructed priority list and acquiring the priority of the message information matched with the port information.
10. A DMA transfer control apparatus according to any one of claims 6 to 9, further comprising:
the receiving module is used for receiving the priority information issued by the priority server in the local area network in real time, wherein the priority information comprises port information and priorities corresponding to the port information;
and the generating module is used for generating a priority list according to the priority information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310242771.0A CN116233036B (en) | 2023-03-14 | 2023-03-14 | DMA transmission control method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310242771.0A CN116233036B (en) | 2023-03-14 | 2023-03-14 | DMA transmission control method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116233036A CN116233036A (en) | 2023-06-06 |
| CN116233036B true CN116233036B (en) | 2023-08-25 |
Family
ID=86584307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310242771.0A Active CN116233036B (en) | 2023-03-14 | 2023-03-14 | DMA transmission control method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116233036B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116860335B (en) * | 2023-09-01 | 2023-11-17 | 北京大禹智芯科技有限公司 | Method for realizing pipelining operation of direct memory access driving system |
| CN118277289B (en) * | 2024-06-03 | 2024-08-30 | 浙江力积存储科技有限公司 | Data output method, device, equipment and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098215A (en) * | 2010-12-17 | 2011-06-15 | 天津曙光计算机产业有限公司 | Priority management method for multi-application packet reception |
| CN103064808A (en) * | 2011-10-24 | 2013-04-24 | 北京强度环境研究所 | Priority adjustable multiple-channel direct memory access (DMA) controller |
| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
| CN113411270A (en) * | 2021-06-07 | 2021-09-17 | 中国人民解放军国防科技大学 | Message buffer management method for time-sensitive network |
| CN115328850A (en) * | 2022-08-17 | 2022-11-11 | 华中科技大学 | Hardware accelerator for hypergraph processing and operation method thereof |
| CN115361336A (en) * | 2022-10-18 | 2022-11-18 | 中科声龙科技发展（北京）有限公司 | Router with cache, route switching network system, chip and routing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060064508A1 (en) * | 2004-09-17 | 2006-03-23 | Ramesh Panwar | Method and system to store and retrieve message packet data in a communications network |
-
2023
- 2023-03-14 CN CN202310242771.0A patent/CN116233036B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098215A (en) * | 2010-12-17 | 2011-06-15 | 天津曙光计算机产业有限公司 | Priority management method for multi-application packet reception |
| CN103064808A (en) * | 2011-10-24 | 2013-04-24 | 北京强度环境研究所 | Priority adjustable multiple-channel direct memory access (DMA) controller |
| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
| CN113411270A (en) * | 2021-06-07 | 2021-09-17 | 中国人民解放军国防科技大学 | Message buffer management method for time-sensitive network |
| CN115328850A (en) * | 2022-08-17 | 2022-11-11 | 华中科技大学 | Hardware accelerator for hypergraph processing and operation method thereof |
| CN115361336A (en) * | 2022-10-18 | 2022-11-18 | 中科声龙科技发展（北京）有限公司 | Router with cache, route switching network system, chip and routing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116233036A (en) | 2023-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116233036B (en) | DMA transmission control method and device | |
| JP4615030B2 (en) | Method and apparatus for reclaiming a buffer | |
| US5765023A (en) | DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer | |
| US7110400B2 (en) | Random access memory architecture and serial interface with continuous packet handling capability | |
| KR101172103B1 (en) | Method for transmitting data in messages via a communications link of a communications system and communications module, subscriber of a communications system and associated communications system | |
| US5781799A (en) | DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers | |
| US7729258B2 (en) | Switching device | |
| US6760791B1 (en) | Buffer circuit for a peripheral interface circuit in an I/O node of a computer system | |
| JPH0685842A (en) | Communication equipment | |
| US5016221A (en) | First-in, first-out (FIFO) memory with variable commit point | |
| CN115516833A (en) | Packet buffer overflow in a network device | |
| US7984210B2 (en) | Method for transmitting a datum from a time-dependent data storage means | |
| US20070201360A1 (en) | Network switch | |
| KR100560277B1 (en) | Assignment of packet descriptor field positions in a network processor | |
| CN117312201A (en) | Data transmission method and device, accelerator equipment, host and storage medium | |
| US9256548B2 (en) | Rule-based virtual address translation for accessing data | |
| CN106372013B (en) | Long-distance inner access method, device and system | |
| US6904039B1 (en) | Packet queuing for a network switch | |
| US8904032B2 (en) | Prefetch optimization of the communication of data using descriptor lists | |
| US11269797B2 (en) | Method and system for controlling data response with aid of attribute of transaction identifier | |
| US8429240B2 (en) | Data transfer device and data transfer system | |
| CN115955441A (en) | Management scheduling method and device based on TSN queue | |
| CN109145397A (en) | A kind of external memory arbitration structure for supporting parallel pipelining process to access | |
| CN113709061A (en) | Message forwarding method and circuit | |
| US9727512B1 (en) | Identical packet multicast packet ready command |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |