CN116232574A

CN116232574A - Data stream key generation method, encryption device, and storage medium

Info

Publication number: CN116232574A
Application number: CN202211737919.XA
Authority: CN
Inventors: 任培培; 孟鹏涛; 代广周
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2022-12-31
Filing date: 2022-12-31
Publication date: 2023-06-06

Abstract

The application provides a data stream key generation method, an encryption device and a flash memory device, wherein the data stream key generation method comprises the steps of responding to a received data packet, and identifying a data header and a data message in the data packet; acquiring key data from a storage array according to the data header; and carrying out key processing on the data message according to the key data. The data stream key generation method, the encryption device and the flash memory device can dynamically establish vector data in real time according to the data stream, and realize algorithm dynamic switching; the key replacement efficiency is improved through a grouping key replacement mode, the key replacement frequency can be improved, and the cost of software and hardware resources is reduced.

Description

Data stream key generation method, encryption device, and storage medium

Technical Field

The present application relates to the field of data security technologies, and in particular, to a data stream key generating method, an encryption device, and a flash memory device.

Background

AES and SM4 symmetric block encryption algorithms are currently the dominant encryption standard in terms of data security. Symmetric encryption algorithms, as their name implies, encrypt and decrypt data using the same keys. The key is the most fundamental private information, cannot be revealed absolutely, and directly determines the security of the data. For different application scenarios, the symmetric encryption algorithm is expanded into different working modes (such as ECB/CBC/CFB/OFB/CTR/XTS/GCM/CCM, etc.), wherein the storage application is mainly applicable to the XTS working mode, and an initial vector IV is introduced to improve the security strength. IV and KEY belong to the same secret information, collectively referred to herein as KEYs, and protection and management mechanisms for KEYs are required throughout their entire lifecycle. Key management mainly includes: generating, storing, transferring, using and replacing. Key generation, either by the shared secret or by the trusted authority in charge of the generation, or by root key derivation. Transfer and storage may be transferred by ciphertext form or secure channel and stored in a secure nonvolatile memory. The key call is temporarily stored in the cache for call, and is mainly used for data encryption/decryption. The key replacement is to ensure that the key is replaced before exceeding the period or being destroyed, namely the data packet finishes the decryption of the old key and the encryption process of the new key.

In the process of designing and implementing the present application, the inventors found that at least the following problems exist: in storage applications, the data stream encryption is generally implemented by fixing the data unit size according to the disk sector, and the sector corresponds to the key packet, and the key is specified by each data unit mark (lba or index) index, which is a key calling scheme of disk encryption, and generally applies to XTS mode.

The key replacement mainly aims at ciphertext, namely ciphertext generated by an old key is returned to plaintext by the old key, and then the ciphertext is regenerated by a new key. The traditional key replacement is generally a multiplexing data encryption-decryption circuit, but the new key cannot be dynamically allocated along with the data packet, the key replacement can only be statically processed, the independence among the packets is not achieved, and a hardware acceleration system of the data key packet is not adapted; or an independent key replacement circuit, the weight of which is biased by software scheduling, and the resource cost is increased. With the development of security algorithms and diversification of application scenes and the demands of large data volume and high throughput rate, more algorithms and modes need to be supported, and more efficient hardware acceleration is required. The existing key calling and key replacing schemes rely on software scheduling too much, packet management is not fine enough, and key streams and data streams of multiple algorithm modes (such as XTS/ECB/CBC/CFB/OFB/CTR/GCM/CCM and the like) cannot be managed dynamically, so that compatibility and efficiency are required to be improved.

Disclosure of Invention

In order to alleviate the above problems, the present application provides a data stream key generation method, including:

identifying a data header and a data message in a data packet in response to receiving the data packet;

acquiring key data from a storage array according to the data header;

and carrying out key processing on the data message according to the key data.

Optionally, the step of identifying a data header in the data packet includes:

and respectively extracting an index field, an indication field and a count value field of the data packet according to the data header.

Optionally, the step of acquiring key data from the storage array according to the data header includes:

and according to the index field, indexing the key group of the storage array, acquiring algorithm configuration, a pre-stored key and an initial vector value in the corresponding key group, and starting a vector generation circuit to sample the count value field and the initial vector value so as to generate vector data according to the algorithm configuration and the pre-stored key.

Optionally, the step of indexing the key group to the storage array according to the index field, obtaining the algorithm configuration, the pre-stored key and the initial vector value in the corresponding key group, and starting the vector generation circuit to sample the count value field and the initial vector value, so as to generate the vector data on line according to the algorithm configuration and the pre-stored key, and then comprises the following steps:

when the indication field indicates encryption or decryption, acquiring a current key in a corresponding key group;

the vector generation circuit generates current vector data based on the current key;

the algorithm configuration, current key and current vector data are encoded in preparation for encrypting or decrypting the data packet.

when the indication field indicates the replacement of the key, acquiring a current key and a target key in the corresponding key group;

the vector generation circuit generates current vector data based on the current key and generates target vector data based on the target key;

and encoding the algorithm configuration, the current key, the target key, the current vector data and the target vector data for decryption and encryption processing, and replacing the key of the data packet.

Optionally, the step of the start vector generation circuit sampling the count value field and the initial vector value to generate vector data on-line according to the algorithm configuration, a target key, includes:

acquiring a configuration mode of the data packet according to the algorithm configuration;

determining vector standard requirements according to the configuration mode;

and generating the vector data according to the vector standard requirements.

Optionally, the step of generating the vector data according to the vector standard requirement includes:

when the vector standard requirement corresponding to the configuration mode is uniqueness, combining the initial vector value with the count value field of the data packet to generate the vector data; or alternatively, the first and second heat exchangers may be,

and when the vector standard requirement corresponding to the configuration mode is randomness, carrying out forward encryption on the count value field of the data packet, and taking the output ciphertext as the vector data.

Optionally, the step of performing key processing on the data packet according to the key data includes:

and sending the algorithm configuration, the target key, the vector data and the data message to a preset algorithm engine, and performing key processing on the data message.

Optionally, the step of indexing the key group to the storage array according to the index field, and obtaining the algorithm configuration, the target key and the initial vector value in the corresponding key group further includes:

and pre-judging the key of the pre-fetching subsequent data packet according to the data packet.

Optionally, the method for dynamically processing the confidential data stream further comprises at least one of the following steps:

in the data stream, each data packet triggers the execution of a key acquisition action once;

the storage array is divided into a plurality of groups according to a disk sector or an application scene;

each group of the storage array comprises an algorithm configuration table, a data key table, an adjustment key table and an initial vector table;

each packet of the storage array is extended in parallel with a new set of key tables.

The application also provides an encryption device, which comprises a processor and a memory;

the memory stores a computer program which, when executed by the processor, performs the steps of data stream key generation as described above.

The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of data stream key generation as described above.

As described above, the data stream key generation method, the encryption device and the flash memory device provided by the present application identify a data header and a data packet in response to receiving the data packet; acquiring key data from a storage array according to the data header; and carrying out key processing on the data message according to the key data. Vector data can be dynamically established in real time according to the data stream, so that algorithm dynamic switching is realized; the key replacement efficiency is improved through a grouping key replacement mode, the key replacement frequency can be improved, and the cost of software and hardware resources is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a flowchart of a data stream key generating method according to an embodiment of the present application.

Fig. 2 is a schematic diagram of key grouping information of a storage array according to an embodiment of the present application.

FIG. 3 is a schematic diagram of three logical combinations of RAW, SWAP and XOR according to one embodiment of the present application.

Fig. 4 is a schematic structural diagram of an encryption device according to an embodiment of the present application.

Fig. 5 is an exploded view of a packet field according to an embodiment of the present application.

FIG. 6 is a block diagram of an encryption/decryption index storage array according to one embodiment of the present application.

Fig. 7 is a block diagram of a key replacement index storage array according to an embodiment of the present application.

FIG. 8 is a diagram illustrating a unique vector logic combination scheme according to an embodiment of the present application.

Fig. 9 is a schematic diagram of generation logic of an encryption/decryption indication dynamic vector according to an embodiment of the present application.

Fig. 10 is a schematic diagram of generation logic of a key change indication motion vector according to an embodiment of the present application.

FIG. 11 is a logic processing diagram of a re-encryption engine according to an embodiment of the present application.

FIG. 12 is a diagram illustrating a single block of data re-encryption flow according to one embodiment of the present application.

FIG. 13 is a schematic diagram of a continuous batch re-encryption stream according to one embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

First embodiment

Fig. 1 is a flowchart of a data stream key generation method according to an embodiment of the present application.

As shown in fig. 1, in an embodiment, the data stream key generation method includes:

s10: in response to receiving the data packet, a data header and a data packet in the data packet are identified.

A data stream (data stream) is a set of ordered data sequences of bytes having a start point and an end point. Including input and output streams. Data streams are initially a concept used in the field of communications, representing digitally encoded signal sequences of information used in transmission. A data stream is a sequence of data packets, which includes a plurality of data packets, which are transmitted sequentially in a communication channel. The data packets are also referred to as data frames, and each data packet includes at least two parts, a data header and a data message. Wherein the data header is used to identify the valid start of the data packet, and the data body content portion of the data packet is the data message.

S20: key data is retrieved from the storage array based on the data header.

The key data may be a data key, an adjustment key tweak key, an initial vector raw iv, configuration information config, and the like. The key data may be pre-stored in a storage array, linked to specific addresses according to the index of the data header when needed for use. Illustratively, during the encryption phase, a packet request is awaited, and then the hardware automatically indexes the key.

S30: and carrying out key processing on the data message according to the key data.

The key processing may be encryption, decryption, rekeying, etc. The key data is obtained, and the data message can be correspondingly processed through a re-encryption engine.

The embodiment can dynamically establish real-time vector data in real time according to the data stream, and realize the dynamic switching of the key algorithm; the key replacement efficiency is improved, the key replacement frequency can be improved, and the cost of software and hardware resources is reduced.

Optionally, in response to receiving the data packet, the step of identifying the data header and the data packet in the data packet is preceded by:

in the initialization stage, a true random number is obtained from a random number generator through a scheduling unit;

according to the initialization configuration, the true random number is used as a key to be written into the storage array in a grouping mode.

The random number generator RNG (Random Numeral Generator), also called a random number generator, is a program or hardware for generating random numbers. The random number generator generates a pseudo-random number or sequence of values calculated in a complex manner, thus requiring a different seed value for each operation. The seed values are different and the sequence values obtained are also different. Thus, a truly random number. Illustratively, during an initialization phase, the host obtains a true random number from a random number generator (TRNG) as a key source through a dispatch unit, and then the host writes an initialization configuration and key packets into a key buffer array for use by hardware to automatically index key data during an encryption phase.

Referring to fig. 2, the data key table, the adjustment key tweak key table, the initial vector raw iv table and the algorithm configuration config table may be flexibly divided (N groups) according to a disk sector or an application scenario, wherein each group is independent, and the complete key information is composed of 4 information tables, namely, a data key table, an adjustment key tweak key table, an initial vector raw iv table and an algorithm configuration config table. The config table contains the fine management of each group such as encryption and decryption authority, bypass, algorithm mode configuration, host intervention protection and the like, and the other information tables contain the initial key and vector iv information required by encryption. A new set of key table is also extended in parallel in the grouping scheme, and a new set of dkey, tkey and riv data is provided.

Optionally, the step of identifying the data header in the data packet comprises:

Illustratively, each packet is encoded upstream and consists of two parts, a data header and a data message payload. The data header may carry an index field index, an indication field direct and a count value field Nonce, and is mainly used for indexing a packet key and generating vector data. An initial vector (IV, initialization Vector), in the Wired Equivalent Privacy (WEP) protocol, is used to combine with a key into a key seed that is used as an input to the RC4 algorithm to produce an encrypted byte stream to encrypt data. The standard 64-bit WEP uses a 40-bit key to attach a 24-bit initial vector to become the key for RC 4. Typically, the initial vector will be required to be a random number or pseudo-random number (pseudo-random) for general use. The initial vector generated by the random number can achieve semantic security (the hash function and the message verification code have the same requirement), and an attacker can hardly crack the ciphertext of the same key. In block encryption, an encryption mode using an initial vector is called a block encryption mode.

Optionally, the step of retrieving key data from the storage array based on the data header comprises:

and according to the index field, indexing the key group of the storage array, acquiring the algorithm configuration, the pre-stored key and the initial vector value in the corresponding key group, and starting the vector generation circuit to sample the count value field and the initial vector value so as to generate vector data according to the algorithm configuration and the pre-stored key.

In an exemplary embodiment, according to the situation that the indication field carried by the data packet indicates encryption, decryption or key replacement, first, the hardware automatically indexes the corresponding packet in the storage array according to the index field, and obtains the algorithm configuration and the pre-stored key data stored in the packet. Wherein information such as algorithm, mode, key size, etc. can be specified according to the algorithm configuration. Then, according to the algorithm configuration and the key data, the hardware automatically starts the vector generation circuit, and the initial vector and the count value field are sampled to generate vector data in real time. And finally, encoding the obtained configuration, the pre-stored key data and the generated vector data, and transmitting the data packet to a downstream re-encryption engine to complete encryption or decryption of the data packet.

Optionally, according to the index field, indexing the key group to the storage array, obtaining the algorithm configuration, the pre-stored key and the initial vector value in the corresponding key group, and starting the vector generation circuit to sample the count value field and the initial vector value, so as to generate the vector data on line according to the algorithm configuration and the pre-stored key, and then the steps of:

when the indication field indicates encryption or decryption, acquiring a current key in the corresponding key group; the vector generation circuit generates current vector data based on the current key; the algorithm configuration, the current key and the current vector data are encoded in preparation for encrypting or decrypting the data packet.

Illustratively, when the indication field direct carried by the header indicates encryption or decryption, the hardware automatically indexes to a certain packet (e.g., group 1 of fig. 4) of the storage array according to the index field index, and obtains the algorithm configuration and the present key stored in the packet. The information of the algorithm, the mode, the key size and the like can be defined according to the algorithm configuration. Then, according to the algorithm configuration and the current key, the hardware automatically starts an IV vector generation circuit, and samples the initial vector riv and the count value field nonce to generate an IV in real time. And finally, uniformly packaging the configuration, the current key and the generated IV, and transmitting the data packet to a downstream re-encryption engine supporting encryption or decryption to complete encryption or decryption of the data packet.

when the indication field indicates the replacement of the key, acquiring a current key and a target key in the corresponding key group; the vector generation circuit generates current vector data based on the current key and generates target vector data based on the target key; and encoding the algorithm configuration, the current key, the target key, the current vector data and the target vector data for decryption and encryption processing, and replacing the key of the data packet.

For example, when the direct indication field carried by the header indicates a key replacement, first, the hardware automatically indexes a certain packet (e.g., fig. 5, group 1) of the storage array according to the index field index, and obtains the algorithm configuration, the current key and the new key stored in the packet. Then, according to the algorithm configuration and the value of the count value field Nonce, based on the current key, hardware automatically generates a current vector IV (current); the hardware automatically generates a target vector IV (new) based on the target key new key to be used. And finally, uniformly coding the configuration, the current key, the new key, the IV (current) and the IV (new), and transmitting the configuration, the current key, the new key, the IV (current) and the IV (new) to a downstream re-encryption engine supporting a decryption-encryption combined mode along with the data packet to finish the key replacement of the data packet.

Optionally, the step of enabling the vector generation circuit to sample the count value field and the initial vector value to generate the vector data on-line according to the algorithm configuration, the target key, comprises:

acquiring a configuration mode of a data packet according to algorithm configuration; determining vector standard requirements according to the configuration mode; vector data is generated according to vector standard requirements.

Consider the IV standard requirements of different modes: ECB does not require IV; the IV of CBC, CFB requires randomness; OFB, CTR, XTS, GCM and CCM IV require uniqueness. The generation of the scheme IV is determined according to different modes. Optionally, the uniqueness of the IV is satisfied with the nonce of the packet itself, so that the randomness of the IV is satisfied with the encryption result of the nonce.

Optionally, the step of generating vector data according to vector standard requirements includes:

when the vector standard requirement corresponding to the configuration mode is uniqueness, the initial vector value is combined by the count value field of the data packet to generate vector data.

Referring to fig. 3, alternatively, when the unique of the IV is satisfied with the nonce of the packet, three logical combinations of RAW, SWAP and XOR may be used for the unique IV.

and when the vector standard requirement corresponding to the configuration mode is randomness, forward encrypting the count value field of the data packet, and taking the output ciphertext as vector data.

For example, for the randomness IV, a CIPHER encryptor may be used, with the packet configuration and the key (dkey) obtained by the current index as input parameters, forward encrypting the count value field Nonce of the data packet, and the output ciphertext as the finally obtained vector data IV value is returned to the data packet and finally sent to the re-encryption engine together.

Illustratively, when the indication field direct carried by the header indicates encryption or decryption, the configuration, the current key and the generated IV are uniformly packed and encoded, and then the configuration, the current key and the generated IV are sent to a downstream re-encryption engine supporting encryption or decryption in a following manner, so that encryption or decryption of the data packet is completed. Illustratively, when the direct indication field carried by the header indicates the key replacement, the configuration, the current key, the new key, the IV (current) and the IV (new) are uniformly encoded, and then the configuration, the current key, the new key and the IV (new) are issued to a downstream re-encryption engine supporting a decryption-encryption combined mode along with the data packet, so as to complete the key replacement of the data packet. Optionally, in the process of obtaining the vector data, the output ciphertext is used as the finally obtained vector data IV value and returned to the data packet, and the data packet can be sent to a re-encryption engine together for processing.

Optionally, indexing the key packet to the storage array according to the index field, and obtaining the algorithm configuration, the target key and the initial vector value in the corresponding key packet further includes:

and pre-judging the key of the pre-fetch subsequent data packet according to the data packet.

Optionally, according to the current data packet request, the hardware circuit of the scheduling unit can give the key of the current packet, and can also pre-judge the key of the pre-fetch subsequent packet at the same time. For example, when a packet is received, the hardware circuit processes the packet and may also process the next packet in advance, and prefetch the key of the next packet. And judging when the next data packet is received, if the next data packet accords with the prejudgment, directly giving out the key result of the previous pretreatment, and if the next data packet does not accord with the prejudgment, giving up the key result of the previous pretreatment, and carrying out temporary treatment on the new data packet to obtain the correct key result. The preprocessing mode effectively reduces the time delay latency of the continuous data stream for acquiring the secret key, and effectively improves the processing efficiency of the data stream.

Optionally, the method for dynamically processing the confidential data flow may further include:

in the data stream, each data packet triggers the execution of a key acquisition action once.

The data packet payload in the data packet is illustratively the plaintext or ciphertext of the data to be processed. Each data packet may trigger a key acquisition action to be performed so that the data packet may be subjected to the required key processing. The data stream may be a plurality of data packets in succession, whereby the corresponding key acquisitions may also be sequential acquisitions for sequential processing of the data stream.

Referring to fig. 2, optionally, the method for dynamically processing the confidential data flow may further include:

the storage array is divided into a plurality of groups according to the disk sector or the application scene;

With continued reference to fig. 2, the data key table, the adjustment key tweak key table, the initial vector raw iv table and the algorithm configuration config table may be flexibly divided (N groups) according to the disk sector or the application scenario, where each group is independent, and the complete key information is composed of 4 information tables, which are respectively a data key table, an adjustment key tweak key table, an initial vector raw iv table and an algorithm configuration config table. The config table contains the fine management of each group such as encryption and decryption authority, bypass, algorithm mode configuration, host intervention protection and the like, and the other information tables contain the initial key and vector iv information required by encryption. Optionally, a new key table is also extended in parallel in the grouping scheme, so as to provide a new set of dkey, tkey and riv data.

the memory stores a computer program which, when executed by the processor, implements the steps of the data stream key generation method as described above.

Illustratively, the encryption device may include a packet identification module, a key matching module, and a packet processing module.

Optionally, in response to receiving the data packet, the data packet identification module identifies a data header and a data packet in the data packet. The key matching module obtains key data from the storage array based on the data header. And the data packet processing module performs key processing on the data packet according to the key data.

Optionally, in the process that the encryption device realizes the specific function of the secret-related data stream dynamic processing method through the hardware device, the parameters of the related hardware device can be configured through the computer program stored in the memory, or the action of the related hardware device is triggered, so as to realize the steps of the data stream key generation method.

Referring to fig. 4, in an embodiment, the encryption device combines hardware automatic indexing and multi-mode IV real-time generation to improve data encryption throughput and compatibility, and introduces a decryption-encryption combination mode and dual key (new-old key pair) allocation, thereby realizing hardware acceleration of key replacement.

Illustratively, the encryption device supports a host interface, during an initialization phase, the host obtains a true random number from a random number generator (TRNG) as a key source through a dispatch unit, and then the host writes an initialization configuration and a key packet into a key buffer array. In the encryption phase, a packet request is awaited, and then the hardware automatically indexes the key. Each packet is encoded upstream, as shown in fig. 5, and consists of two parts, header and payload. The header carries index, direct and Nonce and is mainly used for indexing a packet key and generating an IV. payload is the plaintext or ciphertext of the data to be processed. Each data packet triggers to execute a key acquisition action, the data stream can be a plurality of continuous data packets, the corresponding key acquisition is continuous, and a scheduling unit in the scheme supports a pretreatment mechanism, namely, according to the current data packet request, a hardware circuit not only gives the key of the current packet, but also pre-judges the key of a pre-fetch subsequent packet, thereby effectively reducing the latency of the key acquisition of the continuous data stream.

Referring to fig. 2, fig. 2 is a block diagram of key information of a storage array, which may be flexibly divided (N groups) according to a disk sector or an application scenario, where each block is independent, and the complete key information is composed of 4 information tables, namely a data key table, a tweek key table, a raw iv table, and a config table. The config table contains the detailed management (encryption and decryption authority, bypass, algorithm mode configuration and host intervention protection) of each group, and the other information tables contain the initial key and iv information required by encryption. A new set of key tables (i.e., a new set of dkey, tkey and riv) is also extended in parallel in the grouping scheme.

As shown in fig. 6, illustratively, when { index, direct, nonce }, which is carried by a data packet, the direct indicates encryption or decryption, first, hardware automatically indexes a certain packet (e.g., fig. 4, group 1) of the storage array according to index, obtains an algorithm configuration and a current key stored in the packet, and according to the algorithm configuration, can determine information such as algorithm, mode, key size, etc. Then, according to the algorithm configuration and the current key, the hardware automatically starts an IV generating circuit, and samples riv and nonce to generate the IV in real time. Finally { configure, present key, generate IV } code, follow the data packet to send down to the downstream re-encryption engine (supporting encryption or decryption), complete encryption or decryption of the data stream.

As shown in fig. 7, illustratively, when { index, direct, nonce }, which is carried by a data packet, the direct indicates a key replacement, first, hardware automatically indexes to a certain packet (e.g., group 1, fig. 5) of the storage array according to the index, and obtains the algorithm configuration, the current key, and the new key stored in the packet. Then, based on the present key, hardware automatically generates IV (current) according to the algorithm configuration and Nonce value; based on the new key, the hardware automatically generates an IV (new). Finally, the { configuration, current key, new key, IV (current), IV (new) } is encoded and sent down to the downstream re-encryption engine (supporting decryption-encryption combination mode) following the packet, completing the key exchange of the data stream.

Illustratively, consider the IV standard requirements of the different modes: ECB does not require IV; the IV of CBC, CFB requires randomness; OFB, CTR, XTS, GCM and CCM IV require uniqueness. According to the scheme IV, the generation is determined according to different modes, the uniqueness of the IV is met by the nonce of the data packet, and the randomness of the IV is met by the encryption result of the nonce. For unique IV, three logical combinations of RAW, SWAP and XOR are supported, as shown in fig. 8.

Fig. 9 is a schematic diagram of generation logic of an encryption/decryption indication dynamic vector according to an embodiment of the present application. Fig. 10 is a schematic diagram of generation logic of a key change indication motion vector according to an embodiment of the present application.

Optionally, for the randomness IV, a CIPHER encryptor is adopted, the Nonce of the data packet is positively encrypted by taking the packet configuration and the key (dkey) obtained by the current index as input parameters, the output ciphertext is taken as the finally obtained IV value, and the finally obtained IV value is returned to the data packet and finally sent to the re-encryption engine together. Dynamic IV generation for encryption/decryption and key change are shown in fig. 9 and 10, respectively.

Third embodiment

In one embodiment, the encryption engine of the encryption device at the downstream combines the key replacement and the data encryption circuit, and besides supporting encryption and decryption of the data packet, a data packet Re-encryption mode MRE (Media Re-encryption) is also expanded, so that dynamic hardware acceleration of key replacement is realized.

As shown in fig. 11, the engine circuit supporting MRE mode, for example, when receiving the input of the data packet (Header and Payload) after the upstream encoding, the hardware automatically buffers the Payload in the buffer and parses the information carried by the Header. The circuit integrates one CIPHER encrypting or decrypting multiplexing, and its interior is designed to be compliant with SM4 (32 rounds) and AES128 (10 rounds), AES192 (12 rounds), AES256 (14 rounds) according to a pipeline structure of 2 rounds/cycle (tentative 2 rounds/cycle, which takes into account timing issues at high frequency clocks, such as above 600 MHZ). The circuit realizes the automatic decryption-encryption combination of hardware through the control of an internal data stream loop. Of course, pure packet encryption and decryption is also supported.

FIG. 12 is a diagram illustrating a single block of data re-encryption flow according to one embodiment of the present application. FIG. 13 is a schematic diagram of a continuous batch re-encryption stream according to one embodiment of the present application.

Optionally, the bottom layer CIPHER engine of the MRE is a 8-level pipeline structure. When the algorithm direction is encryption or decryption, the data stream can be pipeline, and high throughput is realized. When the algorithm direction is KEY replacement, the Loop control logic of the circuit takes 8 data blocks (128 bits/block) as batch units, and sequentially processes the whole data packet according to batches according to the flow of executing step1 (decrypting by the existing KEY) and then executing step2 (encrypting by the new KEY). Each block of data is completely executed step1 and step2 before it is finally output. Fig. 12 is a re-encrypted stream of a single batch of 8 data blocks, the data blocks being pipeline stream inside CIPHER, data block 0 having completed step1 (decryption) being output from CIPHER, direct loop being returned to CIPHER input to perform step2 (encryption). The batch is 8 to match the 8-level pipeline structure so that the data block flows form a closed loop link, and the throughput of the pipeline-CIPHER is fully filled. Fig. 13 is a block re-encryption stream of two consecutive batches, where after the previous batch of blocks 7 is input to CIPHER execution step2, the next batch of blocks 0 can be input to CIPHER execution step1 immediately, which enables seamless engagement between the two batches, as well as guarantees the throughput of filling the pipe-CIPHER.

Based on the resource saving consideration, the scheme of this embodiment integrates only one set of two-way CIPHER, decryption and encryption may not be performed simultaneously, but actually divided into step1 and step2, so that the re-encryption mode throughput is half that of pure encryption or decryption. In another improved embodiment, when dealing with performance-oriented requirements, the system is modified to integrate two CIPHER engines, supporting simultaneous encryption and decryption, and thus the throughput of the key exchange (re-encryption) will be doubled to actually improve the processing performance of the encryption device.

In the embodiment, the hardware automatically indexes the grouping key and automatically generates the associated IV on line, so that a real-time key can be provided for the data stream of the hybrid algorithm, and the efficiency of dynamic encryption and algorithm switching of the data stream is greatly improved. In addition, new-old keys are provided for the data stream in real time through expanding the key table, and the access multiplexing and performance acceleration of data encryption and key replacement are realized by combining a novel re-encryption engine. The key replacement and the data encryption are integrated in the same encryption system, a data path is shared, and the key management and the encryption engine are realized, so that the performance is accelerated, the resources are optimized, and the software efficiency is greatly improved.

The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a data stream key generation method as described above.

Optionally, in the implementation of the specific function of the dynamic processing method of the secret-related data stream through the hardware device, the parameters of the related hardware device can be configured through the computer program stored in the memory, or the action of the related hardware device is triggered, so as to implement the steps of the data stream key generation method.

The embodiments of the encryption device and the storage medium provided in the present application may include all the technical features of any one of the above embodiments, and the expansion and explanation contents of the description are substantially the same as those of each embodiment of the above method, which are not repeated herein.

It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided in the embodiments of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device of the embodiment of the application can be combined, divided and pruned according to actual needs.

In this application, the same or similar term concept, technical solution, and/or application scenario description will generally be described in detail only when first appearing, and when repeated later, for brevity, will not generally be repeated, and when understanding the content of the technical solution of the present application, etc., reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution, and/or application scenario description, etc., which are not described in detail later.

In this application, the descriptions of the embodiments are focused on, and the details or descriptions of one embodiment may be found in the related descriptions of other embodiments.

The technical features of the technical solutions of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims

1. A method for generating a data stream key, comprising:

acquiring key data from a storage array according to the data header;

and carrying out key processing on the data message according to the key data.

2. The data stream key generation method of claim 1, wherein the step of identifying a data header in the data packet comprises:

3. The data stream key generation method of claim 2, wherein the step of retrieving key data from a storage array based on the data header comprises:

4. The data stream key generation method of claim 3, wherein the step of indexing the key packet to the storage array according to the index field, obtaining an algorithm configuration, a pre-stored key, and an initial vector value in the corresponding key packet, and starting a vector generation circuit to sample the count value field and the initial vector value to generate vector data on-line according to the algorithm configuration, the pre-stored key, and then comprises:

5. The data stream key generation method of claim 3, wherein the step of indexing the key packet to the storage array according to the index field, obtaining an algorithm configuration, a pre-stored key, and an initial vector value in the corresponding key packet, and starting a vector generation circuit to sample the count value field and the initial vector value to generate vector data on-line according to the algorithm configuration, the pre-stored key, and then comprises:

6. The data stream key generation method of claim 3, wherein the step of the start vector generation circuit sampling the count value field and the initial vector value to generate vector data on-line according to the algorithm configuration, a target key, comprises:

determining vector standard requirements according to the configuration mode;

and generating the vector data according to the vector standard requirements.

7. The data stream key generation method of claim 6, wherein the step of generating the vector data according to the vector criterion requirement comprises:

8. The data stream key generation method as defined in claim 3, wherein the step of performing key processing on the data packet based on the key data comprises:

9. The data stream key generation method of claim 3, wherein the step of indexing the key groupings to the storage array based on the index field, obtaining the algorithm configuration, target key, and initial vector values in the corresponding key groupings further comprises:

10. The data stream key generation method according to any one of claims 1 to 9, wherein the data stream key generation method further comprises at least one of:

11. An encryption device, wherein the encryption device comprises a processor and a memory;

the memory stores a computer program which, when executed by the processor, implements the steps of the data stream key generation method according to any one of claims 1 to 10.

12. A storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the data stream key generation method according to any of claims 1-10.