CN116232559A - System synchronization method, device, system and computer readable storage medium - Google Patents

Abstract

The application discloses a system synchronization method, a device, a system and a computer readable storage medium, wherein the method comprises the following steps: firstly, obtaining a modulated signal, wherein the modulated signal is obtained by modulating a clock signal by a baseband module by adopting a time division duplex control signal, the time division duplex control signal is used for controlling an uplink and downlink transmission mode of a head end module, and a clock signal is used for realizing clock synchronization of the head end module and the baseband module; then, a time division duplex control signal and a clock signal are obtained from the modulated signal. The method can realize high-precision clock synchronization and time division duplex synchronization, and meets the two synchronous demands in the system.

Description

System synchronization method, device, system and computer readable storage medium

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a system synchronization method, apparatus, system, and computer readable storage medium.

Background

In the conventional clock synchronization scheme based on the digital zoom-out technology, the near end does not transmit a clock signal to the far end separately, and the far end needs to recover the clock signal from the received data (digital signal) by using a Clock Data Recovery (CDR) technology, and then uses the recovered clock signal as a reference signal to perform clock synchronization. The clock recovery circuit is generally implemented by using a phase locked loop structure, and referring to fig. 1, fig. 1 is a simple clock recovery circuit based on a phase locked loop 10, which includes a phase detector 11, a loop filter 12 and a voltage controlled oscillator 13, and inputs data into the phase locked loop 10, so as to recover a clock signal embedded in the data for clock synchronization.

However, the above solution has certain drawbacks: when 0 or 1 which is continuous for a long time appears in data, the output of the voltage-controlled oscillator 13 in the clock recovery circuit is easy to lose lock; the bandwidth selection of the loop filter 12 needs to compromise clock accuracy and clock jitter, which are contradictory, so that it is difficult to select a suitable bandwidth, the phase noise of the recovered clock signal is greatly affected, and the high-accuracy clock synchronization requirement cannot be satisfied.

Therefore, it is necessary to provide a high-precision clock synchronization scheme.

Disclosure of Invention

In order to solve the above-mentioned problems in the prior art, embodiments of the present application provide a system synchronization method, apparatus, system, and computer readable storage medium, which can not only realize high-precision clock synchronization, but also realize Time Division Duplex (TDD) synchronization, and simultaneously meet the two types of synchronization requirements.

In a first aspect, the present application provides a system synchronization method for a headend module, the method including: the method comprises the steps of obtaining a modulated signal, wherein the modulated signal is obtained by modulating a clock signal by a baseband module through a Time Division Duplex (TDD) control signal, the TDD control signal is used for controlling an uplink and downlink transmission mode of a head end module, and a clock signal is used for realizing clock synchronization of the head end module and the baseband module; a TDD control signal and a clock signal are obtained from the modulated signal.

That is, the baseband module modulates the TDD control signal onto the clock signal to obtain a modulated signal; the head end module obtains the modulated signal and then obtains the TDD control signal and the clock signal according to the modulated signal, thereby realizing the TDD synchronization and the clock synchronization of the head end module and the baseband module. It can be understood that the headend module uses the TDD control signal to control its own uplink and downlink transmission modes (or to control the TDD synchronization switch), so as to achieve TDD synchronization with the baseband module; the head-end module can realize clock synchronization with the baseband module by utilizing the clock signal.

According to the method, the clock signal is obtained through the modulated signal, the noise of the obtained clock signal is small, high-precision clock synchronization can be realized, the clock signal does not need to be extracted from data (digital signals), the CDR technology is not relied on, and the problems that a voltage-controlled oscillator is easy to lose lock and the phase noise of the clock signal is large in the CDR technical scheme can be avoided.

Based on the first aspect, in a possible embodiment, the modulated signal is an analog signal.

That is, the modulated signal is an analog signal rather than a digital signal, and the baseband module may transmit the analog signal to the headend module without being digitally encoded; the headend module does not need to recover the clock signal from the digital signal, does not need to realize circuits/devices with CDR functions, is beneficial to miniaturization of the headend module, and can also reduce the power consumption of the headend module.

Based on the first aspect, in a possible embodiment, obtaining the TDD control signal and the clock signal from the modulated signal comprises: and demodulating the modulated signal to obtain a TDD control signal, and phase-locking the modulated signal to obtain a clock signal.

That is, the headend module demodulates and phase locks based on the modulated signal, and may obtain a TDD control signal and a clock signal, respectively, so as to achieve TDD synchronization and clock synchronization of the headend module and the baseband module. Obviously, the mode for realizing the two types of synchronization is simple and easy to implement, and has high reliability.

Based on the first aspect, in a possible embodiment, demodulating based on the modulated signal to obtain the TDD control signal, phase locking based on the modulated signal to obtain the clock signal includes: separating the modulated signal into a first signal and a second signal, wherein the waveforms of the first signal and the second signal are the same as those of the modulated signal; demodulating the first signal to obtain a TDD control signal, and phase-locking the second signal to obtain a clock signal.

It can be seen that the headend module divides the acquired modulated signal into two signals, which are respectively represented by a first signal and a second signal, where the signal separation may be implemented by using a power divider, a coupler, etc., which is not specifically limited in this application. Because the waveforms of the first signal and the second signal are identical (there may be a difference in amplitude and/or phase) to the modulated signal, the first signal and the second signal may be considered to both carry information of the TDD control signal and the clock signal, and the TDD control signal and the clock signal may be extracted using the first signal and the second signal. And then, the head end module demodulates and phase-locks the first signal and the second signal respectively, so that a TDD control signal and a clock signal are obtained, and further the TDD synchronization and the clock synchronization of the head end module and the baseband module are realized.

Based on the first aspect, in a possible embodiment, the modulated signal is obtained by amplitude keying modulating the clock signal by the baseband module using the TDD control signal.

That is, the modulation scheme adopted by the baseband module may be an amplitude keying modulation scheme, and the TDD control signal is used as a modulation signal to control the amplitude of the clock signal (as a carrier signal), thereby obtaining a modulated signal. Accordingly, the head-end module needs to perform processing by adopting a corresponding demodulation scheme, that is, an amplitude demodulation scheme.

Based on the first aspect, in a possible embodiment, acquiring the modulated signal comprises: and receiving the first optical signal sent by the baseband module, and performing photoelectric conversion according to the first optical signal to obtain a modulated signal.

That is, the baseband module may directly send the modulated signal to the headend module, or may first convert the modulated signal into an optical signal, and then send the optical signal to the headend module, which is helpful for improving the extension distance of the headend module (or improving the transmission distance of the signal), so that after the headend module receives the optical signal sent by the baseband module, the headend module needs to obtain the modulated signal through photoelectric conversion, and further obtains the TDD control signal and the clock signal according to the modulated signal.

In a second aspect, the present application provides a further system synchronization method for a baseband module, the method comprising: acquiring a Time Division Duplex (TDD) control signal and a clock signal, wherein the TDD control signal is used for controlling an uplink and downlink transmission mode of a head end module, and the clock signal is used for realizing clock synchronization of the head end module and a baseband module; modulating a clock signal by adopting a TDD control signal to obtain a modulated signal; the modulated signal is sent to the headend module.

That is, the baseband module obtains the modulated signal by obtaining the TDD control signal and the clock signal and modulating the TDD control signal onto the clock signal, and then sends the modulated signal to the headend module, so that the headend module can achieve TDD synchronization and high-precision clock synchronization of the headend module and the baseband module based on the modulated signal. The baseband module does not need to digitally encode the modulated signal, so the headend module does not need to recover the clock signal from the digital signal, and does not need to implement circuits/devices for CDR functions, thereby contributing to miniaturization of the headend module and reducing power consumption of the headend module.

Based on the second aspect, in a possible embodiment, the modulated signal is an analog signal.

Based on the second aspect, in a possible embodiment, modulating the clock signal with the TDD control signal to obtain a modulated signal includes: and performing amplitude keying modulation on the clock signal by adopting the TDD control signal to obtain a modulated signal.

Based on the second aspect, in a possible embodiment, transmitting the modulated signal to the headend module includes: and performing electro-optic conversion on the modulated signal to obtain a first optical signal, and sending the first optical signal to the head-end module.

In a third aspect, embodiments of the present application provide an apparatus, the apparatus comprising: the device comprises an acquisition unit, a control unit and a clock signal generation unit, wherein the acquisition unit is used for acquiring a modulated signal, the modulated signal is obtained by modulating a clock signal by a baseband module through a Time Division Duplex (TDD) control signal, the TDD control signal is used for controlling an uplink transmission mode and a downlink transmission mode of the device, and the clock signal is used for realizing clock synchronization of the device and the baseband module; and the processing unit is used for obtaining the TDD control signal and the clock signal according to the modulated signal.

In a possible embodiment, the modulated signal is an analog signal.

In a possible embodiment, the obtaining the TDD control signal and the clock signal according to the modulated signal includes: and demodulating the modulated signal to obtain a TDD control signal, and phase-locking the modulated signal to obtain a clock signal.

In a possible embodiment, the demodulating based on the modulated signal to obtain the TDD control signal, and phase-locking based on the modulated signal to obtain the clock signal includes: separating the modulated signal into a first signal and a second signal, wherein the waveforms of the first signal and the second signal are the same as those of the modulated signal; demodulating the first signal to obtain a TDD control signal, and phase-locking the second signal to obtain a clock signal.

In a possible embodiment, the modulated signal is obtained by performing amplitude keying modulation on the clock signal by using a TDD control signal by the baseband module.

In a possible embodiment, acquiring the modulated signal comprises: and receiving the first optical signal sent by the baseband module, and performing photoelectric conversion according to the first optical signal to obtain a modulated signal.

In a fourth aspect, embodiments of the present application provide yet another apparatus, the apparatus comprising: the device comprises an acquisition unit, a control unit and a control unit, wherein the acquisition unit is used for acquiring a Time Division Duplex (TDD) control signal and a clock signal, the TDD control signal is used for controlling an uplink and downlink transmission mode of a head end module, and the clock signal is used for realizing clock synchronization of the head end module and the device; the modulating unit is used for modulating the clock signal by adopting the TDD control signal to obtain a modulated signal; and the transmitting unit is used for transmitting the modulated signal to the head-end module.

In a possible embodiment, the modulated signal is an analog signal.

In a possible embodiment, the modulating the clock signal with the TDD control signal to obtain the modulated signal includes: and performing amplitude keying modulation on the clock signal by adopting the TDD control signal to obtain a modulated signal.

In a possible embodiment, the transmitting the modulated signal to the headend module includes: and performing electro-optic conversion on the modulated signal to obtain a first optical signal, and sending the first optical signal to the head-end module.

In a fifth aspect, embodiments of the present application provide a system comprising an apparatus according to any of the above third aspects and an apparatus according to any of the above fourth aspects.

In a sixth aspect, embodiments of the present application provide a computer-readable storage medium; the computer readable storage medium is for storing implementation code of the method of any one of the embodiments of the first or second aspects.

In a seventh aspect, embodiments of the present application provide yet another apparatus that includes a processor, a memory, and a transceiver, where the processor, memory, and transceiver may be interconnected by a bus, or may be integrated. The processor is configured to read the program code stored in the memory and perform the method according to any one of the embodiments of the first or second aspect.

In an eighth aspect, embodiments of the present application provide a chip for implementing the method described in any embodiment of the first or second aspect.

In a ninth aspect, embodiments of the present application provide a computer program (product) comprising program instructions for implementing the method of any of the embodiments of the first or second aspects described above, when the computer program product is executed.

In summary, in the baseband module side of the embodiment of the present application, the number of signals can be reduced, the number of combiners required in the baseband module can be reduced, and the optical module and the optical fiber can be saved by modulating the TDD control signal onto the clock signal, that is, using the clock signal as the carrier of the TDD control signal. The baseband module may specifically adopt an amplitude keying modulation mode, and thus, a corresponding demodulation mode needs to be adopted in the headend module for amplitude demodulation. The baseband module may then send the modulated signal directly to the headend module, or may first modulate the modulated signal (which is an analog signal) further into an optical signal, and then send the optical signal to the headend module via an optical fiber.

At the side of the head end module, the optical signals transmitted by the baseband module are restored to modulated signals through photoelectric conversion, and then the modulated signals are separated into two paths of signals for demodulation and phase locking respectively: one path of signal can complete the recovery of the TDD control signal through demodulation, thereby realizing the TDD synchronization of the head end module and the baseband module; the other path of signal is phase-locked to obtain the clock signal, so that the clock synchronization of the head end module and the baseband module is realized.

It should be noted that, in the embodiment of the present application, the modulated signal is an analog signal instead of a digital signal, and the baseband module may transmit the analog signal to the head-end module without undergoing digital coding; the headend module does not need to recover clock signals from data (digital signals), does not depend on CDR technology, can avoid the problem that a voltage-controlled oscillator in a CDR technical scheme is easy to lose lock and clock signals have large phase noise, and is beneficial to miniaturization of the headend module and can also reduce power consumption of the headend module because circuits/devices for realizing the CDR function are not needed. It should also be appreciated that the headend module obtains the clock signal via the modulated signal, resulting in less noise in the clock signal, enabling high precision clock synchronization between the headend module and the baseband module. It can be seen that the system synchronization method provided by the embodiment of the application is simple and reliable, can realize high-precision time synchronization, can realize TDD synchronization, and can meet the two types of synchronization requirements in the system.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below.

FIG. 1 is a schematic diagram of a clock recovery circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic architecture diagram of a wireless communication system according to an embodiment of the present application;

fig. 3 is a schematic diagram of yet another wireless communication system provided in an embodiment of the present application;

fig. 4 is a schematic flow chart of a system synchronization method according to an embodiment of the present application;

fig. 5 is a schematic process flow diagram of a baseband module according to an embodiment of the present application;

fig. 6 is a schematic process flow diagram of a headend module according to an embodiment of the present application;

FIG. 7 is a flow chart of yet another system synchronization method according to an embodiment of the present application;

FIG. 8 is a flow chart of yet another system synchronization method according to an embodiment of the present application;

FIG. 9 is a schematic structural view of an apparatus according to an embodiment of the present application;

fig. 10 is a schematic structural view of yet another device according to an embodiment of the present application.

Detailed Description

In order to facilitate understanding of the technical solutions in the embodiments of the present application, the following describes some terms and concepts related in the embodiments of the present application.

1. Phase Locked Loop (PLL):

the meaning of phase lock is automatic control of phase synchronization, and an automatic control closed loop system capable of completing phase synchronization of two electric signals is called a phase lock loop. The PLL is characterized by: controlling the frequency and phase of an in-loop oscillation signal (oscillasignal) by using an externally input reference signal so that the oscillation signal output by the PLL is synchronized with the reference signal; the PLL generally includes a Phase Detector (PD), a loop filter (LP), a Voltage Controlled Oscillator (VCO), a Charge Pump (CP), a frequency divider (frequency divider), and the like.

2. Time Division Duplex (TDD) and TDD systems:

TDD is a full duplex communication technology used in communication systems. For a communication system of a TDD mode (called TDD system for short), uplink and downlink transmission signals are in the same frequency band, the time occupied by uplink and downlink in one frequency band can be adjusted as required, signals are scheduled to different time periods, discontinuous transmission is adopted, and a certain time interval is set to avoid interference between the uplink and downlink signals. The TDD system requires strict alignment of uplink and downlink time slots and has higher synchronization requirement.

The following describes a wireless communication system according to an embodiment of the present application.

Referring to fig. 2, fig. 2 is a schematic architecture diagram of a wireless communication system according to an embodiment of the present application, where the wireless communication system includes a baseband module 100 and at least one head-end module 200, and the baseband module 100 and the head-end module 200 are connected through a transmission medium 300.

It should be noted that, the transmission medium 300 may be an optical fiber, a radio frequency feeder line, or other types of transmission media, which are not specifically limited in this application. As shown in fig. 2, each head-end module 200 has a corresponding antenna(s) for transmitting or receiving radio signals. The antenna may be integrated inside the headend module 200, or may be located outside the headend module 200, and connected to the headend module 200 through a feeder line, which is not limited in this application.

The baseband module 100 and the headend module 200 are described in detail below.

(1) The baseband module 100 is configured to process baseband signals and centrally provide baseband resources to one or more headend modules 200. The baseband module 100 may be deployed in a switch, a router, etc., which may be located in an indoor or outdoor machine room, etc., and the present application is not limited in detail.

In one possible embodiment, as shown in fig. 3, the baseband module 100 and the headend module 200 are connected by an optical fiber 400, where the optical fiber 400 may include one or more optical fibers, which may be single mode optical fibers or multimode optical fibers, and is not specifically limited herein; the baseband module 100 includes a modulator 101 and an analog optical module 102.

Wherein the modulator 101 is configured to modulate an input signal thereof to obtain a modulated signal. For example, it is assumed that the modulation mode adopted by the modulator 101 is binary amplitude keying (amplifier shift keying, ASK), i.e., 2ASK, which is also commonly referred to as on-off keying (OOK), and OOK modulation is to control the amplitude of a carrier signal by using a binary digital signal, thereby obtaining an OOK modulated signal.

The analog optical module 102 is used to perform optical-to-electronic (O/E) and electro-optical (E/O) conversion. For example, the analog optical module 102 modulates a light source using an analog electrical signal such that a characteristic (e.g., light intensity) of an output optical signal varies with the analog electrical signal. For another example, the analog optical module 102 converts the optical signal into an analog electrical signal by photoelectric conversion.

(2) The headend module 200 is configured to process Radio Frequency (RF) signals, implement functions of amplifying and filtering the RF signals, and radiate the RF signals through an antenna. The headend module 200 may be distributed indoors/outdoors, on various floors/rooms, etc., without specific limitation.

In one possible embodiment, as shown in fig. 3 (the corresponding antenna of the headend module 200 is not shown), the headend module 200 includes an analog optical module 201, a signal separation unit 202, a phase locked loop 203, and a demodulator 204.

The analog optical module 201 is used for realizing photoelectric conversion and electro-optical conversion. The analog optical module 201 is an analog optical module that modulates an optical signal by an analog signal, as is the analog optical module 102 in the baseband module 100.

The signal separation unit 202 is configured to separate an input signal thereof into two paths of signal outputs. The signal separation unit 202 may be a power divider, a coupler, etc., which is not particularly limited in this application.

The phase-locked loop 203 is used for phase-locking its input signal. The phase-locked loop 203 may have various types and various implementations (based on hardware or software implementation), and the application is not particularly limited.

The demodulator 204 is used for signal demodulation (the inverse of modulation) and detects the original modulated signal from the modulated signal.

It should be noted that the above-mentioned division, connection relation, and the like of the respective functional modules in the baseband module 100 and the headend module 200 are only examples, and they may include more or fewer modules. For example, the same functional module may be divided into a plurality of sub-modules, and a plurality of functional modules may be combined into one module, which is not specifically limited in this application.

Based on the above wireless communication system, embodiments of the system synchronization method provided in the present application are described below.

Referring to fig. 4, fig. 4 is a flowchart of a system synchronization method according to an embodiment of the present application, where the method is used in the above wireless communication system, and includes the following steps:

s401, the baseband module 100 acquires a TDD control signal and a clock signal.

The TDD control signal is used to control the uplink and downlink transmission modes of the headend module 200, so as to achieve TDD synchronization between the headend module 200 and the baseband module 100. In other words, the TDD control signal is used as an uplink and downlink switching signal in the headend module 200 to control the TDD synchronous switch in the headend module 200, thereby implementing switching between the uplink path and the downlink path. For example, when the TDD control signal is high, the control headend module 200 is in a downlink transmission mode; when the TDD control signal is low, the control headend module 200 is in the uplink transmission mode.

The clock signal is used to realize clock synchronization between the baseband module 100 and the headend module 200, and may be used as a synchronous clock source of the headend module 200 or as a system clock.

In a possible embodiment, the clock signal may be generated by a clock source in the baseband module 100. The clock source may be a crystal oscillator, a voltage controlled oscillator, an inductance-capacitance (LC) oscillating circuit, etc., and is not particularly limited in this application.

S402, the baseband module 100 modulates the clock signal by adopting the TDD control signal to obtain a modulated signal, converts the modulated signal into a first optical signal and sends the first optical signal to the headend module 200.

It should be noted that, the modulation mode may be amplitude modulation; the modulated signal (analog electrical signal) is subjected to electro-optical conversion to obtain a first optical signal.

In one possible embodiment, the baseband module 100 modulates the TDD control signal onto the clock signal by ASK modulation, resulting in a modulated signal.

For example, as shown in fig. 5, it is assumed that the TDD control signal is a unipolar rectangular pulse sequence, the clock signal CLK is a high-frequency oscillation signal, and the TDD control signal and the CLK are respectively used as a modulation signal and a carrier signal to be input to the modulator 101 in the baseband module 100. Assuming that a binary ASK (i.e., OOK) modulation scheme is used, the modulator 101 performs OOK modulation on CLK with the TDD control signal to obtain an OOK modulation signal (i.e., modulated signal), and it can be seen that the amplitude of the OOK modulation signal varies with the TDD control signal. The OOK modulated signal is input to the analog optical module 102, and then the analog optical module 102 performs electro-optical conversion, converts the OOK modulated signal (which is an analog electrical signal) into a first optical signal, and then transmits the first optical signal to the headend module 200 through the optical fiber 400.

It should be noted that, the analog optical module 102 may convert the data signal into the second optical signal, and then transmit the first optical signal and the second optical signal in the same optical fiber 400 through processing. The data signal and the modulated signal may be combined into one signal through frequency division multiplexing, and then the analog optical module 102 performs electro-optical conversion to obtain a third optical signal, and then the third optical signal is transmitted to the headend module 200 through the optical fiber 400, which is not specifically limited in this application.

S403, the headend module 200 receives the first optical signal sent by the baseband module 100, and obtains a modulated signal according to the first optical signal.

On the above, as shown in fig. 6, the analog optical module 201 in the headend module 200 receives the first optical signal transmitted by the baseband module 100 through the optical fiber 400, and performs photoelectric conversion on the first optical signal to recover the OOK modulated signal (i.e., the modulated signal).

It should be noted that, in some possible embodiments, in step S402, after the baseband module 100 modulates the clock signal with the TDD control signal to obtain the modulated signal, the modulated signal may be directly sent to the headend module 200 without performing electro-optical conversion; then, in step S403, the headend module 200 may directly receive the modulated signal transmitted by the baseband module 100, without performing photoelectric conversion.

S404, the headend module 200 demodulates the modulated signal to obtain a TDD control signal, and phase locks the modulated signal to obtain a clock signal.

In one possible embodiment, headend module 200 splits the modulated signal into two signals and then performs the following operations on the two signals, respectively: demodulating one path of signal to recover the TDD control signal, so as to control the uplink and downlink transmission modes of the head end module 200 according to the TDD control signal; the other signal is phase-locked to obtain a clock signal.

Continuing with the above example, as shown in fig. 6, the analog optical module 201 inputs the recovered OOK modulated signal (i.e., modulated signal) into the signal separation unit 202, and the signal separation unit 202 separates the OOK modulated signal into two signals, which are represented by a first signal and a second signal. The first signal, the second signal and the OOK modulated signal have the same waveform, but the amplitude and/or the phase may be different (determined by the specific type of the signal separation unit 202), so that the first signal, the second signal and the modulated signal may be considered as the same as each other, and have the information of the TDD control signal and the clock signal, so that the TDD control signal and the clock signal can be obtained according to the first signal and the second signal. It is understood that the energy relationship between the first signal, the second signal and the OOK modulated signal is determined by the type of the signal separation unit 202 and performance index (including distribution loss, insertion loss, isolation, etc.), and the signal separation unit 202 may be a power divider, a coupler, etc., which is not specifically limited in this application.

Then, the first signal is input to the demodulator 204 for demodulation, so that the original modulation signal, i.e., the TDD control signal, can be recovered, and then the state of the TDD synchronization switch in the headend module 200 can be controlled according to the TDD control signal, where the TDD synchronization switch is responsible for controlling the conversion between the uplink path and the downlink path (i.e., the uplink and downlink transmission modes), so as to achieve TDD synchronization between the headend module 200 and the baseband module 100. For example, when the TDD control signal is at a high level, the headend module 200 is controlled to open the uplink path and close the downlink path; when the TDD control signal is low, the headend module 200 is controlled to close the upstream path and open the downstream path. It should be noted that, the demodulator 204 demodulates the first signal, the demodulated signal may not be a TDD control signal, and signal shaping and signal amplification are also required, so a shaping and amplifying module/circuit may be further provided in the headend module 202, for shaping and amplifying the signal demodulated by the demodulator 204, and finally, the TDD control signal may be obtained.

The second signal is input into the phase-locked loop 203 as a reference signal (or as a synchronous clock source of the reference clock/headend module 200), and the frequency and phase of the oscillation signal output by the phase-locked loop 203 are controlled by using the second signal, so that the clock signal can be finally obtained. The parameter setting of the phase-locked loop 203 and the phase-locking process of the phase-locked loop 203 on the second signal to obtain the clock signal will not be described here. It should be noted that, by performing phase locking on the second signal, the phase-locked loop 203 may have a certain phase difference between the output oscillation signal and the clock signal in the baseband module 100, so the headend module 200 may further have a phase adjustment module/circuit for performing phase adjustment on the oscillation signal output by the phase-locked loop 203, thereby obtaining the clock signal.

In summary, in the baseband module 100 side of the embodiment of the present application, the number of signals can be reduced, the number of combiners required in the baseband module 100 can be reduced, and the number of (analog) optical modules and optical fibers can be saved by modulating the TDD control signal onto the clock signal, that is, using the clock signal as the carrier of the TDD control signal. The baseband module 100 may then send the modulated signal directly to the headend module 200, or may further modulate the modulated signal into an optical signal before sending the optical signal to the headend module 200 via the optical fiber 400.

In the embodiment of the present application, at the headend module 200 side, the optical signal transmitted by the baseband module 100 is restored to a modulated signal through photoelectric conversion, and then the modulated signal is separated into two paths of signals for demodulation and phase locking respectively: one path of signal can complete the recovery of the TDD control signal through demodulation, thereby realizing the TDD synchronization of the head-end module 200 and the baseband module 100; the other path of signal can obtain the clock signal through phase locking, so that the clock synchronization of the head end module 200 and the baseband module 100 is realized.

It should be noted that, in the embodiment of the present application, the modulated signal is an analog signal instead of a digital signal, and the baseband module 100 may transmit the analog signal to the head-end module 200 without undergoing digital encoding; the headend module 200 does not need to recover the clock signal from the data (digital signal), does not depend on CDR technology, can avoid the problem that the voltage-controlled oscillator in CDR technology scheme is easy to lose lock and the clock signal has large phase noise, and does not need to implement the circuit/device of CDR function, thus contributing to miniaturization of the headend module 200 and reducing the power consumption of the headend module 200. The headend module 200 obtains the clock signal through the modulated signal, and the obtained clock signal has low noise, so that high-precision clock synchronization between the headend module 200 and the baseband module 100 can be realized. It can be seen that the system synchronization method provided by the embodiment of the application is simple and reliable, not only can realize high-precision time synchronization, but also can realize TDD synchronization, and simultaneously meets the two synchronization requirements in a wireless communication system.

It can be understood that the system synchronization method provided by the application not only can be used for mobile communication systems such as 2G/3G/4G/5G, but also can be used for wireless high-fidelity (Wi-Fi) and other types of wireless communication systems such as bluetooth.

Referring to fig. 7, fig. 7 is a flowchart of another system synchronization method according to an embodiment of the present application, where the method is used in the baseband module 100, and includes the following steps:

s701, a TDD control signal and a clock signal are acquired, where the TDD control signal is used to control an uplink and downlink transmission mode of the headend module 200, and the clock signal is used to implement clock synchronization between the headend module 200 and the baseband module 100.

The step S701 may be specifically referred to as the relevant content in the step S401, and the description is not repeated here.

S702, modulating a clock signal by adopting a TDD control signal to obtain a modulated signal.

In one embodiment, the modulated signal is an analog signal.

In one possible embodiment, the modulated signal is obtained by amplitude keying modulation of the clock signal using a TDD control signal.

Step S702 is specifically described with reference to the relevant content in step S402, which is not described here.

S703, transmitting the modulated signal to the headend module 200.

In one possible embodiment, baseband module 100 may send the modulated signal directly to headend module 200, and in particular may transmit the modulated signal over a radio frequency feeder between baseband module 100 and headend module 200.

In yet another possible embodiment, the baseband module 100 may perform electro-optical conversion on the modulated signal to obtain a first optical signal, and then send the first optical signal to the headend module 200, where the first optical signal may be specifically transmitted through the optical fiber 400 between the baseband module 100 and the headend module 200. This embodiment is specifically described with reference to the relevant content in step S402, which is not described here.

In summary, in the baseband module 100 side, the embodiment of the present application modulates the TDD control signal onto the clock signal, that is, uses the clock signal as the carrier of the TDD control signal, so that the number of signals can be reduced, the number of combiners required in the baseband module 100 can be reduced, and the number of (analog) optical modules and the number of optical fibers in the baseband module 100 can be saved. The modulated signal obtained in the present application is an analog signal, and the baseband module 100 does not need to digitally encode the modulated signal, and can directly send the modulated signal to the headend module 200; the modulated signal may be further modulated into an optical signal, and then sent to the headend module 200 through the optical fiber 400, which helps to increase the remote distance of the headend module 200 (or increase the transmission distance of the signal). The headend module 200 can obtain the TDD control signal and the clock signal by demodulating and phase-locking according to the modulated signal, thereby implementing TDD synchronization and time synchronization between the headend module 200 and the baseband module 100.

Referring to fig. 8, fig. 8 is a flowchart of another system synchronization method according to an embodiment of the present application, where the method is used in the headend module 200, and includes the following steps:

s801, a modulated signal is obtained by modulating a clock signal by the baseband module 100 with a TDD control signal, where the TDD control signal is used to control an uplink and downlink transmission mode of the headend module 200, and the clock signal is used to achieve clock synchronization between the headend module 200 and the baseband module 100.

In one embodiment, the modulated signal is an analog signal.

In one possible embodiment, acquiring the modulated signal may include: the first optical signal sent by the baseband module 100 is received, and the modulated signal is obtained by performing photoelectric conversion according to the first optical signal.

In one possible embodiment, the modulated signal is an amplitude keying modulation of the clock signal by the baseband module 100 using a TDD control signal.

S802, a TDD control signal and a clock signal are obtained according to the modulated signal.

In one possible embodiment, the TDD control signal is demodulated based on the modulated signal and the clock signal is phase locked based on the modulated signal.

In one possible embodiment, the modulated signal is separated into a first signal and a second signal, the first signal is demodulated to obtain a TDD control signal, and the second signal is phase-locked to obtain a clock signal, wherein the waveforms of the first signal, the second signal and the modulated signal are the same.

In summary, in the embodiment of the present application, at the headend module 200 side, the optical signal transmitted by the baseband module 100 may be restored to the modulated signal through photoelectric conversion, and then the modulated signal is separated into two paths of signals for demodulation and phase locking respectively: one path of signal can complete the recovery of the TDD control signal through demodulation, thereby realizing the TDD synchronization of the head-end module 200 and the baseband module 100; the clock signal can be obtained by phase locking the other path of signal, the noise of the clock signal obtained by the modulated signal is small, and the high-precision clock synchronization between the head end module 200 and the baseband module 100 can be realized. In the embodiment of the present application, the modulated signal is an analog signal, rather than a digital signal, and the headend module 200 can easily obtain the TDD control signal and the clock signal according to the modulated signal, without recovering the clock signal from the data (digital signal), without depending on CDR technology, so that the problem that the voltage-controlled oscillator in CDR technical scheme is easy to lose lock and the clock signal has large phase noise can be avoided. Since the headend module 200 does not require a device for implementing CDR functions, it contributes to miniaturization of the headend module 200 and also reduces power consumption of the headend module 200.

Referring to fig. 9, fig. 9 is a schematic structural diagram of an apparatus 900 provided in an embodiment of the present application, where the apparatus 900 includes an acquisition unit 901, a modulation unit 902, and a transmission unit 903.

An obtaining unit 901, configured to obtain a time division duplex TDD control signal and a clock signal, where the TDD control signal is used to control an uplink and downlink transmission mode of the headend module 200, and the clock signal is used to achieve clock synchronization of the headend module 200 and the device.

A modulating unit 902, configured to modulate the clock signal with a TDD control signal to obtain a modulated signal.

A transmitting unit 903, configured to transmit the modulated signal to the headend module 200.

In one possible embodiment, the modulated signal is an analog signal.

In a possible embodiment, the modulation unit 902 is specifically configured to: and performing amplitude keying modulation on the clock signal by adopting the TDD control signal to obtain a modulated signal.

In one possible embodiment, the sending unit 903 is specifically configured to: the modulated signal is electro-optically converted to a first optical signal, which is transmitted to headend module 200.

It should be noted that, in the embodiment of fig. 9, the apparatus 900 is only illustrated by the division of the units, and in practical application, the above-mentioned function allocation may be performed by different units/functional modules according to needs, that is, the internal structure of the apparatus 900 is divided into different units/functional modules to perform all or part of the functions described above.

It should be further noted that, the apparatus 900 may correspond to the baseband module 100 in the wireless communication system of fig. 2 or fig. 3, and specific functional implementation of the apparatus 900 is described with reference to the baseband module 100 side in any embodiment of fig. 4 or fig. 7, which is not repeated here.

Referring to fig. 10, fig. 10 is a schematic structural diagram of an apparatus 1000 according to an embodiment of the present application, where the apparatus 1000 includes an obtaining unit 1001 and a processing unit 1002.

An obtaining unit 1001, configured to obtain a modulated signal, where the modulated signal is obtained by modulating a clock signal by using a TDD control signal by using the baseband module 100, the TDD control signal is used to control an uplink and downlink transmission mode of the apparatus 1000, and the clock signal is used to achieve clock synchronization between the apparatus 1000 and the baseband module 100.

A processing unit 1002 for obtaining a TDD control signal and a clock signal from the modulated signal.

In one possible embodiment, the modulated signal is an analog signal.

In one possible embodiment, the processing unit 1002 is specifically configured to: and demodulating the modulated signal to obtain a TDD control signal, and phase-locking the modulated signal to obtain a clock signal.

In one possible embodiment, the processing unit 1002 is specifically configured to: separating the modulated signal into a first signal and a second signal, wherein the first signal and the second signal have the same waveform as the modulated signal; demodulating the first signal to obtain a TDD control signal, and phase-locking the second signal to obtain a clock signal.

In one possible embodiment, the modulated signal is obtained by amplitude keying modulation of the clock signal by the baseband module 100 using a TDD control signal.

In one possible embodiment, the obtaining unit 1001 is specifically configured to: the first optical signal sent by the baseband module 100 is received, and the modulated signal is obtained by performing photoelectric conversion according to the first optical signal.

It should be noted that, in the device 1000 provided in the embodiment of fig. 10, only the division of the units is illustrated, and in practical application, the above-mentioned function allocation may be performed by different units/functional modules according to needs, that is, the internal structure of the device 1000 is divided into different units/functional modules to perform all or part of the functions described above.

It should be further noted that the above apparatus 1000 may correspond to the headend module 200 in the wireless communication system of fig. 2 or fig. 3, and the apparatus 1000 may be specifically configured to perform the related method on the headend module 200 side in any embodiment of fig. 4 or fig. 8, please refer to the related description above, which is not repeated herein.

The embodiment of the application also provides a device, which comprises a memory, a processor and a transceiver, wherein two or all of the memory, the processor and the transceiver can be connected with each other through a bus or can be integrated together.

Such memory includes, but is not limited to, random access memory (random access memory, RAM), read-only memory (ROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM), or portable read-only memory (compact disc read-only memory, CD-ROM) for storing associated instructions and data.

The transceivers are used to transmit the modulated signals to the headend module 200, or to convert the modulated signals to first optical signals for transmission to the headend module 200, and so on.

The processor may be one or more central processing units (central processing unit, CPU), and in the case where the processor is a CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor in the apparatus is particularly useful for performing the related methods on the baseband module 100 side in the embodiments of fig. 4 or fig. 7 described above.

The above apparatus may be applied to the wireless communication system architecture shown in fig. 2 or 3, and for example, may be the baseband module 100 in fig. 2, for performing operations performed on the baseband module 100 side in the system synchronization method of fig. 4 or 7.

The embodiment of the application also provides another device, which comprises a memory, a processor and a transceiver, wherein two or all of the memory, the processor and the transceiver can be connected with each other through a bus or can be integrated together.

Such memory includes, but is not limited to, random access memory (random access memory, RAM), read-only memory (ROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM), or portable read-only memory (compact disc read-only memory, CD-ROM) for storing associated instructions and data.

The transceiver is configured to obtain a modulated signal, or receive a first optical signal sent by the baseband module 100, perform photoelectric conversion according to the first optical signal to obtain the modulated signal, or the like.

The processor may be one or more central processing units (central processing unit, CPU), and in the case where the processor is a CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor in the apparatus is specifically configured to perform the method associated with the headend module 200 side of the embodiment of fig. 4 or 8.

The above apparatus may be applied to the wireless communication system architecture shown in fig. 2 or 3, and for example, may be the headend module 200 in fig. 2, for performing operations performed by the headend module 200 side in the system synchronization method of fig. 4 or 8.

Embodiments of the present application also provide a system comprising the apparatus 900 of any of the previous embodiments and the apparatus 1000 of any of the previous embodiments.

Embodiments of the present application also provide a computer readable storage medium having instructions stored therein that, when executed on a processor, implement the method of any of the embodiments of fig. 4, 7 or 8. Embodiments of the present application also provide a chip including a processor for implementing the method described in any of the embodiments of fig. 4, 7 or 8. The present embodiments also provide a computer program product which, when run on a processor, implements the method of any of the embodiments of fig. 4, 7 or 8.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.

It should be noted that the foregoing disclosure is only a part of the embodiments, but not all of the embodiments, and it should be understood that the scope of the claims is not limited thereto.

It is also to be understood that the terminology used in the embodiments of the application is for the purpose of describing particular embodiments only, and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and/or" as used herein refers to all possible combinations comprising one or more of the associated listed items.

Claims (22)

1. A system synchronization method for a headend module, the method comprising:

the method comprises the steps of obtaining a modulated signal, wherein the modulated signal is obtained by modulating a clock signal by a baseband module through a Time Division Duplex (TDD) control signal, the TDD control signal is used for controlling an uplink and downlink transmission mode of a head end module, and the clock signal is used for realizing clock synchronization of the head end module and the baseband module;

and obtaining the TDD control signal and the clock signal according to the modulated signal.

2. The method of claim 1, wherein the modulated signal is an analog signal.

3. The method according to claim 1 or 2, wherein said obtaining said TDD control signal and said clock signal from said modulated signal comprises:

Demodulating based on the modulated signal to obtain the TDD control signal, and phase-locking based on the modulated signal to obtain the clock signal.

4. The method of claim 3, wherein demodulating the TDD control signal based on the modulated signal, phase-locking the clock signal based on the modulated signal, comprises:

separating the modulated signal into a first signal and a second signal, wherein the first signal, the second signal and the modulated signal have the same waveform;

demodulating the first signal to obtain the TDD control signal, and phase-locking the second signal to obtain the clock signal.

5. The method of any of claims 1-4, wherein the modulated signal is an amplitude keying modulation of the clock signal by the baseband module using the TDD control signal.

6. The method according to any one of claims 1 to 5, wherein said acquiring the modulated signal comprises:

and receiving a first optical signal sent by the baseband module, and performing photoelectric conversion according to the first optical signal to obtain the modulated signal.

7. A system synchronization method for a baseband module, the method comprising:

acquiring a Time Division Duplex (TDD) control signal and a clock signal, wherein the TDD control signal is used for controlling an uplink and downlink transmission mode of a head end module, and the clock signal is used for realizing clock synchronization of the head end module and a baseband module;

modulating the clock signal by adopting the TDD control signal to obtain a modulated signal;

and transmitting the modulated signal to the head-end module.

8. The method of claim 7, wherein the modulated signal is an analog signal.

9. The method of claim 8, wherein modulating the clock signal with the TDD control signal results in a modulated signal, comprising:

and performing amplitude keying modulation on the clock signal by adopting the TDD control signal to obtain the modulated signal.

10. The method according to any one of claims 7 to 9, wherein said transmitting the modulated signal to the headend module comprises:

and performing electro-optic conversion on the modulated signal to obtain a first optical signal, and sending the first optical signal to the head-end module.

11. An apparatus, the apparatus comprising:

the device comprises an acquisition unit, a control unit and a control unit, wherein the acquisition unit is used for acquiring a modulated signal, the modulated signal is obtained by modulating a clock signal by a baseband module through a Time Division Duplex (TDD) control signal, the TDD control signal is used for controlling an uplink transmission mode and a downlink transmission mode of the device, and the clock signal is used for realizing clock synchronization of the device and the baseband module;

and the processing unit is used for obtaining the TDD control signal and the clock signal according to the modulated signal.

12. The apparatus of claim 11, wherein the modulated signal is an analog signal.

13. The apparatus according to claim 11 or 12, wherein said obtaining said TDD control signal and said clock signal from said modulated signal comprises:

demodulating based on the modulated signal to obtain the TDD control signal, and phase-locking based on the modulated signal to obtain the clock signal.

14. The apparatus of claim 13, wherein the demodulating based on the modulated signal to obtain the TDD control signal and the phase locking based on the modulated signal to obtain the clock signal comprises:

Separating the modulated signal into a first signal and a second signal, wherein the first signal, the second signal and the modulated signal have the same waveform;

demodulating the first signal to obtain the TDD control signal, and phase-locking the second signal to obtain the clock signal.

15. The apparatus according to any of claims 11 to 14, wherein the modulated signal is an amplitude keying modulation of the clock signal by the baseband module using the TDD control signal.

16. The apparatus according to any one of claims 11 to 15, wherein the acquiring the modulated signal comprises:

and receiving a first optical signal sent by the baseband module, and performing photoelectric conversion according to the first optical signal to obtain the modulated signal.

17. An apparatus, the apparatus comprising:

an obtaining unit, configured to obtain a time division duplex TDD control signal and a clock signal, where the TDD control signal is used to control an uplink and downlink transmission mode of a headend module, and the clock signal is used to implement clock synchronization between the headend module and the device;

a modulating unit, configured to modulate the clock signal with the TDD control signal to obtain a modulated signal;

And the transmitting unit is used for transmitting the modulated signal to the head-end module.

18. The apparatus of claim 17, wherein the modulated signal is an analog signal.

19. The apparatus of claim 18, wherein modulating the clock signal with the TDD control signal to obtain a modulated signal comprises:

and performing amplitude keying modulation on the clock signal by adopting the TDD control signal to obtain the modulated signal.

20. The apparatus of any of claims 17 to 19, wherein the transmitting the modulated signal to the headend module comprises:

and performing electro-optic conversion on the modulated signal to obtain a first optical signal, and sending the first optical signal to the head-end module.

21. A system comprising the apparatus of any one of claims 11 to 16 and the apparatus of any one of claims 17 to 20.

22. A computer readable storage medium comprising a program or instructions which, when run on a processor, implement the method of any of claims 1-6 or 7-10.

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