CN116230677A

CN116230677A - Semiconductor structure and preparation method thereof

Info

Publication number: CN116230677A
Application number: CN202210797975.6A
Authority: CN
Inventors: 丘世仰
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2021-12-03
Filing date: 2022-07-06
Publication date: 2023-06-06
Also published as: TW202324550A; TWI817340B

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure comprises a substrate; a redistribution layer disposed on the substrate and having a dielectric layer disposed on the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to and surrounded by the dielectric layer; and a conductive bump disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump. Furthermore, a method for manufacturing the semiconductor structure is also provided.

Description

Semiconductor structure and preparation method thereof

The priority of U.S. patent application Ser. Nos. 17/541,792 and 17/543,194 (i.e., priority dates "2021, 12, 3, and" 2021, 12, 6 "), the contents of which are incorporated herein by reference in their entirety).

Technical Field

The present disclosure relates to a semiconductor structure. And more particularly to a semiconductor structure having a bond pad at least partially exposed through a redistribution layer to accommodate an external interconnect structure.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cell phones, digital cameras, or other electronic devices. The fabrication of semiconductor devices includes sequentially depositing layers of different materials on a semiconductor substrate and patterning the layers of materials using photolithography and etching processes to form microelectronic devices including transistors, diodes, resistors, and/or capacitors on or in the semiconductor substrate.

The semiconductor industry continues to increase the integration density of microelectronic devices by continually shrinking the minimum feature size, which allows more devices to be integrated into a given area. For example, in order to further increase the density of the semiconductor element, stacking of two or more elements has been studied. Accordingly, improvements that address the related manufacturing challenges are desired to be developed.

The above description of "prior art" merely provides background art, and it is not admitted that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate; a redistribution layer disposed on the substrate and including a dielectric layer disposed on the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to and surrounded by the dielectric layer; and a conductive bump disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

In some embodiments, a first surface of the conductive plug and a second surface of the bond pad are exposed through the dielectric layer.

In some embodiments, the first surface of the conductive plug is substantially coplanar with the second surface of the bond pad.

In some embodiments, the first surface of the conductive plug and the second surface of the bond pad contact a seed layer of the conductive bump.

In some embodiments, the first surface of the conductive plug, the second surface of the bond pad, and a third surface of the dielectric layer are substantially coplanar.

In some embodiments, the first surface of the conductive plug is completely covered by the conductive bump.

In some embodiments, a first portion of the second surface of the bond pad is covered by the conductive bump, a second portion of the second surface is exposed through the dielectric layer and through the conductive bump, and the first portion is substantially smaller than the second portion.

In some embodiments, an upper cross section of the bonding pad has a ring shape, a fan shape, or a polygonal shape.

In some embodiments, a height of the conductive plug is substantially greater than a thickness of the bond pad.

In some embodiments, the redistribution layer has a conductive element electrically connecting the conductive plug to the substrate.

In some embodiments, the conductive element is electrically connected to the conductive plug via the conductive plug.

In some embodiments, the conductive element is electrically connected to the bond pad via the conductive plug.

In some embodiments, the conductive bump is electrically connected to a device disposed on the substrate via the conductive element and the conductive plug.

In some embodiments, the conductive element includes a pad portion extending horizontally within the dielectric layer and a via portion coupled to and extending vertically from the pad portion.

In some embodiments, the conductive plug contacts the bonding pad and the bonding pad portion.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure comprises a first substrate; and a redistribution layer disposed on the first substrate and including a dielectric layer disposed on the first substrate, a conductive plug extending within the dielectric layer, and a bonding pad surrounded by the dielectric layer and contacting the conductive plug; wherein the conductive plug is at least partially surrounded by the bond pad.

In some embodiments, the semiconductor structure further includes a conductive bump covering the conductive plug and partially covering the bonding pad.

In some embodiments, a width of the conductive plug is substantially smaller than a width of the conductive bump.

In some embodiments, an interface between the conductive plug and the bond pad is disposed under the conductive bump.

In some embodiments, the conductive bump is disposed on and bonded with an interconnect structure of a second substrate.

In some embodiments, the bonding pad includes a first bonding pad and a second bonding pad spaced apart from the first bonding pad, and the conductive plug is disposed between the first bonding pad and the second bonding pad.

In some embodiments, the conductive plug contacts the first and second junctions.

In some embodiments, the semiconductor structure further includes a bonding wire disposed on and bonded to the bonding pad.

In some embodiments, the first substrate includes a plurality of elements disposed thereon and a plurality of insulators separating the plurality of elements.

Yet another embodiment of the present disclosure provides a method of fabricating a semiconductor structure. The preparation method comprises providing a substrate and a redistribution layer disposed on the substrate, wherein the redistribution layer has a dielectric layer and a conductive plug disposed on the substrate, and the conductive plug extends into the dielectric layer; disposing an etch stop layer on the redistribution layer; disposing a first patterned photoresist on the etch stop layer; removing a portion of the dielectric layer and a portion of the etch stop layer exposed through the first patterned photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and on a portion of the dielectric layer exposed by the first patterned photoresist; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed through the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material protruding from the dielectric layer to form a bond pad adjacent to and surrounded by the conductive plug.

In some embodiments, the first seed layer disposed on the etch stop layer contacts the conductive plug.

In some embodiments, the bond pad includes the first seed layer and the conductive material.

In some embodiments, the portion of the conductive material protrudes from the etch stop layer after the second patterned photoresist is removed.

In some embodiments, the removing of the portion of the dielectric layer exposed by the first patterned photoresist includes forming an opening to extend into the dielectric layer and be disposed adjacent to the conductive plug.

In some embodiments, the conductive plug is at least partially exposed after the opening is formed.

In some embodiments, the opening surrounds the conductive plug.

In some embodiments, the second patterned photoresist fills a portion of the opening.

In some embodiments, the second patterned photoresist is at least partially surrounded by the first seed layer.

In some embodiments, the method of making further comprises: disposing a dielectric material in the opening and on the etch stop layer; and removing a portion of the dielectric material disposed on the etch stop layer.

In some embodiments, the semiconductor structure further comprises: disposing a second seed layer on the bonding pad, the conductive plug and the dielectric layer; disposing a third patterned photoresist on the second seed layer; and forming a portion of a conductive bump exposed through the third patterned photoresist on the second seed layer.

In summary, because the bond pad is disposed adjacent to the conductive plug in the redistribution layer, the bond pad may accommodate an external interconnect structure, such as a wire bond. Furthermore, the bond pad may be formed in a variety of shapes such that the bond pad may receive the external interconnect structure from the same direction around the portion of the conductive plug. Thus, a flexible interconnect and wiring of the semiconductor structure can be realized.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure may be more completely understood in consideration of the following description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure.

Fig. 2 is a schematic top cross-sectional view illustrating the semiconductor device of fig. 1 along a section line A-A' according to an embodiment.

Fig. 3 is a schematic top cross-sectional view illustrating the semiconductor device of fig. 1 along a section line A-A' according to an embodiment.

Fig. 4 is a schematic top cross-sectional view illustrating the semiconductor device of fig. 1 along a section line A-A' according to an embodiment.

Fig. 5 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure.

Fig. 6 is a schematic top cross-sectional view illustrating the semiconductor device of an embodiment along a section line B-B' in fig. 5.

Fig. 7 is a schematic top cross-sectional view illustrating the semiconductor device of fig. 5 along a section line B-B' according to an embodiment.

Fig. 8 is a flow diagram illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 9-36 are schematic cross-sectional views illustrating various intermediate stages in the fabrication of a semiconductor structure in accordance with some embodiments of the present disclosure.

The reference numerals are as follows:

100 semiconductor structure

101 substrate

101a semiconductor layer

101b insulator

101c element

101d rear side

101e front side

102 redistribution layer

102a solder pad portion

102b through hole portion

102c conductive plug

102d bonding pad

102e solder pad

102f seed layer

102g dielectric layer

102h first surface

102i second surface

102j third surface

102k first bonding pad

102m second bonding pad

102n first part

102p second part

102r interface

102s opening

103 conductive bump

103a under bump metallurgy

103b metal layer

103c barrier layer

103d solder assembly

104 etch stop layer

105 first patterned photoresist

106 first seed layer

107 second patterned photoresist

108 conductive material

109 dielectric material

110 second seed layer

111 third patterned Photoresist

112 bonding wire

H1 height of

Height of H2

S200. preparation method

S201 step

S202, step

S203 step

S204, step

S205 step

S206, step

S207 step

S208 step

S209 step

S210 step

S211 step

W1 width

W2 width

Detailed Description

The embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the disclosure is not intended to be limited thereby. Any alterations and modifications in the described embodiments, and any further applications of the principles as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates. Element numbers may be repeated throughout an embodiment, but this does not necessarily mean that features of one embodiment are applicable to another embodiment even though they share the same element numbers.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a schematic cross-sectional view illustrating a semiconductor structure 100 in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor structure 100 is part of a die, a package, or an element. In some embodiments, the semiconductor structure 100 is a flip-chip package (flip-chip package). In some embodiments, the semiconductor structure 100 includes a substrate 101, a redistribution layer 102, and a conductive bump 103, wherein the redistribution layer 102 is disposed on the substrate 101, and the conductive bump 103 is disposed on the redistribution layer 102.

In some embodiments, the substrate 101 is part of a wafer. In some embodiments, the substrate 101 is sawed from a wafer by dicing, cutting, or other suitable operations. In some embodiments, the substrate 101 comprises a semiconductor material, such as silicon. In some embodiments, the substrate 101 is a silicon substrate. In some embodiments, the substrate 101 includes a semiconductor layer 101a, a plurality of insulators 101b, and a plurality of elements 101c, the plurality of elements 101c being disposed on the semiconductor layer 101a and separated by the plurality of insulators 101 b.

In some embodiments, the semiconductor layer 101a includes a rear side 101d and a front side 101e, the front side 101e being disposed opposite the rear side 101 d. During fabrication of the semiconductor structure 100, the backside 101d is disposed on a support substrate. A plurality of elements 101c are formed on the front side 101e and are configured to be electrically connected to an external circuit. In some embodiments, the plurality of elements 101c are Metal Oxide Semiconductor (MOS) elements. In some embodiments, the plurality of insulators 101b are Shallow Trench Isolations (STI).

In some embodiments, the redistribution layer 102 is disposed on the front side 101e of the substrate 101. The redistribution layer 102 rewires a path of a circuit from the plurality of elements 101c on the substrate 101 to the conductive bumps 103. In some embodiments, the redistribution layer 102 includes a conductive element (102 a and 102 b), a conductive plug 102c, a bonding pad 102d, and a dielectric layer 102g, wherein the dielectric layer 102g surrounds the conductive element (102 a and 102 b), the conductive plug 102c, and the bonding pad 102d.

In some embodiments, a dielectric layer 102g is disposed on the front side 101e of the substrate 101 and covers the plurality of elements 101c. Dielectric layer 102g includes a dielectric material such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or the like. In some embodiments, the dielectric layer 102g includes a number of dielectric layers stacked on top of each other. In some embodiments, each dielectric layer comprises a material that is the same as or different from the material of the other dielectric layers.

In some embodiments, the

conductive elements

102a and 102b are an interconnect structure (interconnect) electrically connected to the substrate 101. Conductive elements (102 a and 102 b) are disposed within the dielectric layer 102 g. In some embodiments, the conductive elements (102 a and 102 b) comprise a conductive material, such as gold, silver, copper, nickel, aluminum, or the like. In some embodiments, the conductive elements (102 a and 102 b) include a pad portion 102a and a via portion 102b, the pad portion 102a extending horizontally within the dielectric layer 102g, the via portion 102b being coupled to the pad portion 102a and extending vertically within the dielectric layer 102g and away from the pad portion 102a.

In some embodiments, conductive plugs 102c extend vertically within dielectric layer 102g and toward conductive elements (102 a and 102 b). In some embodiments, conductive plugs 102c are disposed on the pad portions 102 a. The conductive plug 102c is electrically connected to the substrate 101 through the

conductive elements

102a and 102 b. In some embodiments, the conductive plug 102c is surrounded by a dielectric layer 102 g. In some embodiments, a first surface 102h of the conductive plug 102c is exposed through the dielectric layer 102 g. In some embodiments, the conductive plug 102c comprises a conductive material, such as gold, silver, copper, nickel, aluminum, or the like.

In some embodiments, the bond pad 102d is disposed adjacent to the conductive plug 102c and surrounded by the dielectric layer 102 g. In some embodiments, the bond pad 102d at least partially contacts the conductive plug 102c. The bonding pad 102d is electrically connected to the conductive plug 102c. In some embodiments, a sidewall of the bond pad 102d contacts a sidewall of the conductive plug 102c. In some embodiments, the bond pad 102d is electrically connected to the conductive elements (102 a and 102 b) via the conductive plug 102c. In some embodiments, the bond pad 102d comprises a conductive material, such as gold, silver, copper, nickel, aluminum, or the like.

In some embodiments, the bonding pad 102d includes a seed layer 102e and a bonding pad 102f, and the bonding pad 102f is surrounded by the seed layer 102 e. In some embodiments, the seed layer 102e contacts the conductive plug 102c. In some embodiments, the seed layer 102e is surrounded by the dielectric layer 102g and the conductive plug 102c. In some embodiments, the seed layer 102e is a single layer or a composite stack and includes a material such as copper, aluminum, tungsten, or a combination thereof. In some embodiments, the pad 102f contacts the seed layer 102e and is completely surrounded by the seed layer 102 e. In some embodiments, the bond pad 102f comprises a conductive material, such as copper, silver, gold, or the like.

In some embodiments, the conductive plug 102c is at least partially surrounded by the bond pad 102 d. In some embodiments, the bond pad 102d may be of any of a variety of shapes along an upper cross-section of the line A-A' in FIG. 1. In some embodiments, the upper cross section of the bonding pad 102d is a polygonal shape. For example, as shown in fig. 2, the upper section of the bonding pad 102d is a sector shape. For example, as shown in fig. 3 and 4, the upper cross section of the bonding pad 102d is a quarter-annular shape or a half-annular shape.

In some embodiments, the bond pad 102d has an annular shape as shown in FIG. 6 in an upper cross-section along the line B-B' of FIG. 5. In some embodiments, as shown in fig. 5 and 7, the bonding pad 102d includes a first bonding pad 102k and a second bonding pad 102m, and the second bonding pad 102m is spaced apart from the first bonding pad 102 k. The conductive plug 102c is disposed between the first bonding pad 102k and the second bonding pad 102m. In some embodiments, the conductive plug 102c contacts the first bond pad 102k and the second bond pad 102m. In some embodiments, an upper cross section of the first bonding pad 102k and an upper cross section of the second bonding pad 102m are each fan-shaped.

Referring back to fig. 1, in some embodiments, the bond pad 102d includes a second surface 102i exposed through the dielectric layer 102 g. In some embodiments, the second surface 102i of the bond pad 102d is substantially coplanar with the first surface 102h of the conductive plug 102 c. In some embodiments, the second surface 102i includes an upper surface of the seed layer 102e and an upper surface of the pad 102 f.

In some embodiments, the conductive plug 102c has a height H1 that is substantially greater than a height H2 of the bond pad 102 d. The height H1 of the conductive plug 102c extends from the first surface 102H to the pad portion 102a. The height H2 of the bond pad 102d extends from the second surface 102i to the front side 101e of the substrate 101.

In some embodiments, the dielectric layer 102g includes a third surface 102j disposed opposite the front side 101e of the substrate 101. In some embodiments, the first surface 102h of the conductive plug 102c, the second surface 102i of the bond pad 102d, and the third surface 102j of the dielectric layer 102g are substantially coplanar.

In some embodiments, conductive bump 103 is disposed on conductive plug 102 c. In some embodiments, the conductive bump 103 is disposed on a portion of the dielectric layer 102g and the bonding pad 102d of the redistribution layer 102. In some embodiments, the bond pad 102d at least partially contacts the conductive plug 102c and the conductive bump 103. In some embodiments, the conductive elements (102 a and 102 b) are electrically connected to the conductive bump 103 via the conductive plug 102 c. In some embodiments, the conductive bump 103 is electrically connected to the element 101c disposed on the substrate 101. In some embodiments, the first surface 102h of the conductive plug 102c contacts the conductive bump 103 with the second surface 102i of the bond pad 102 d.

In some embodiments, an interface 102r between the conductive plug 102c and the bond pad 102d is disposed under the conductive bump 103. In some embodiments, the conductive bump 103 is disposed on and bonded to an interconnect structure of other substrates (not shown). For example, because the semiconductor structure 100 is a flip-chip package, the semiconductor structure 100 shown in fig. 1 is flipped upside down, and the conductive bump 103 is disposed on and bonded to an interconnect structure, such as a bond pad of another substrate disposed under the semiconductor structure 100.

In some embodiments, the first surface 102h is completely covered by the conductive bump 103 and contacts the conductive bump 103. In some embodiments, a first portion 102n of the second surface 102i covered by the conductive bump 103 is substantially smaller than a second portion 102p of the second surface 102i exposed through the dielectric layer 102g and exposed through the conductive bump 103. In some embodiments, the second portion 102p of the second surface 102i of the bond pad 102d is configured to receive a bond wire, thereby electrically connecting the semiconductor structure 100 to other semiconductor structures or other substrates. Since the bond pad 102d may be formed in a variety of shapes and sizes as desired, the bond pad 102d may accommodate external interconnect structures, such as bond wires having different orientations around conductive plugs. Thus, a flexible interconnect and routing of the semiconductor structure 100 may be achieved.

In some embodiments, the conductive bump 103 comprises a conductive material, such as lead, tin, copper, gold, nickel, or the like. In some embodiments, the conductive bump 103 is a Ball Grid Array (BGA) solder ball, a controlled collapse chip connection (controlled collapse chip connection, C4) bump, a microbump, a pillar, or the like. In some embodiments, the conductive plug 102c has a width W1 that is substantially smaller than a width W2 of the conductive bump 103.

In some embodiments, the conductive bump 103 includes an Under Bump Metal (UBM) layer 103a, a metal layer 103b, a barrier layer 103c, and a solder element 103d. In some embodiments, an under bump metal layer 103a is disposed on the conductive plug 102c and the dielectric layer 102 g. The under bump metal layer 103a contacts the first surface 102h and the third surface 102j. In some embodiments, the under bump metal layer 103a covers the first surface 102h and partially covers the second surface 102i. In some embodiments, the under bump metal layer 103a is a seed layer or an adhesion layer for accommodating the conductive bump 103 of the metal layer 103 b. In some embodiments, the under bump metal layer 103a contacts the first surface of the conductive plug 102c and the second surface 102i of the bond pad 102 d. In some embodiments, the under bump metal layer 103a comprises titanium, copper, gold, or the like. In some embodiments, the under bump metal layer 103a comprises at least two conductive materials.

In some embodiments, a metal layer 103b is disposed on the under bump metal layer 103a and the conductive plug 102 c. In some embodiments, the metal layer 103b comprises a conductive material, such as copper, silver, gold, or the like. In some embodiments, a barrier layer 103c is disposed on the metal layer 103b, the under bump metal layer 103a, and the conductive plug 102 c. In some embodiments, the barrier layer 103c is configured to avoid diffusion of the metal layer 103b into the solder component 103d. In some embodiments, the barrier layer 103c comprises titanium, titanium nitride, tantalum nitride, nickel, or the like.

In some embodiments, solder assembly 103d is disposed on barrier layer 103c, metal layer 103b, and under bump metal layer 103 a. In some embodiments, the solder assembly 103d includes a reflowable material (reflowable material). In some embodiments, the solder assembly 103d includes tin, lead, silver, copper, nickel, or the like. In some embodiments, the solder component 103d is configured to bond an interconnect structure of other substrates to the semiconductor structure 100, such as a bond pad.

Fig. 8 is a flow chart illustrating a method S200 of fabricating a semiconductor structure according to some embodiments of the present disclosure. Fig. 9-36 are schematic cross-sectional views illustrating various intermediate stages in the fabrication of a semiconductor structure 100 in accordance with some embodiments of the present disclosure.

Stages as shown in fig. 9 to 36 are also exemplarily shown in the flowchart in fig. 8. In the following discussion, the various stages of manufacture as shown in fig. 9 through 36 are discussed with reference to the various process steps as shown in fig. 8. The preparation method S200 includes many steps and the description and illustration is not to be construed as limiting the order of the steps. The preparation method S200 includes a number of steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211).

Referring to fig. 9, according to a step S201 in fig. 8, a substrate 101 and a redistribution layer 102 disposed on the substrate 101 are provided. In some embodiments, the redistribution layer 102 includes a dielectric layer 102g and a conductive plug 102c, the dielectric layer 102g is disposed on the substrate 101, and the conductive plug 102c extends within the dielectric layer 102 g. In some embodiments, the fabrication technique of the redistribution layer 102 includes disposing a dielectric material on the substrate 101; portions of the dielectric material are removed and conductive material is provided to form conductive plug 102c and a conductive element (102 a and 102 b).

Referring to fig. 10, according to a step S202 in fig. 10, an etch stop layer 104 is disposed on the redistribution layer 102. An etch stop layer 104 is disposed over the dielectric layer 102g and the conductive plug 102 c. In some embodiments, the etch stop layer 104 comprises a dielectric material having an etch selectivity that is different from the etch selectivity of adjacent materials. In some embodiments, the etch stop layer 104 comprises nitride, silicon nitride, or the like. In some embodiments, the etch stop layer 104 is deposited by Chemical Vapor Deposition (CVD) or any other suitable process.

Referring to fig. 11, according to a step S203 in fig. 8, a first patterned photoresist 105 is disposed on the etching stop layer 104. In some embodiments, the fabrication technique of the first patterned photoresist 105 includes disposing a photoresist material on the etch stop layer 104; covering portions of the photoresist material; the exposed portions of the photoresist material are then removed to pattern the photoresist material, thereby forming a first patterned photoresist 105. In some embodiments, a portion of the etch stop layer 104 is exposed through the first patterned photoresist 105. In some embodiments, portions of the etch stop layer 104 are exposed through the first patterned photoresist 105 as shown in fig. 12. In some embodiments, the plurality of exposed portions of photoresist material are configured to present a ring of fields having a ring shape. In some embodiments, the photoresist material is provided by spin coating or any other suitable process.

Referring to fig. 13, according to a step S204 in fig. 8, portions of the dielectric layer 102g and the etch stop layer 104 exposed through the first patterned photoresist 105 are removed. In some embodiments, portions of the dielectric layer 102g and the etch stop layer 104 exposed through the first patterned photoresist 105 are removed simultaneously or sequentially. Portions of the dielectric layer 102g and the etch stop layer 104 exposed through the first patterned photoresist 105 are removed by an etching process, such as a dry etch or other suitable etching process. In some embodiments, an opening 102s is formed. In some embodiments, the removal of portions of the dielectric layer 102g exposed through the first patterned photoresist 105 includes forming openings 102s, with the openings 102s extending into the dielectric layer 102g and disposed adjacent to the conductive plugs 102c. In some embodiments, the conductive plug 102c is at least partially exposed after the opening 102s is formed. In some embodiments, a number of openings 102s are formed as shown in fig. 14. In some embodiments, the opening 102s surrounds the conductive plug 102c. In some embodiments, at least a portion of the conductive plug 102c is exposed via the opening 102s.

Referring to fig. 15 or 16, according to a step S205 in fig. 8, the first patterned photoresist 105 is removed. In some embodiments, the first patterned photoresist 105 is removed by etching, stripping, or any suitable process.

Referring to fig. 17, according to a step S206 in fig. 8, a first seed layer 106 is disposed on the etch stop layer 1404 and on a portion of the dielectric layer 102g exposed through the etch stop layer 104. In some embodiments, the first seed layer 106 is disposed conformally with the etch stop layer 104 and the opening 102s. In some embodiments, the first seed layer 106 is disposed conformally with a number of openings 102s as in fig. 18. In some embodiments, at least a portion of the first seed layer 106 contacts the portion of the conductive plug 102c exposed through the opening 102s. In some embodiments, the first seed layer 106 is a single layer or a composite stack and includes a material such as copper, titanium, tungsten, or a combination thereof. In some embodiments, the first seed layer 106 is provided by deposition, physical Vapor Deposition (PVD), or any other suitable process.

Referring to fig. 19, according to a step S207 in fig. 8, a second patterned photoresist 107 is disposed on the first seed layer 106. In some embodiments, the fabrication technique of the second patterned photoresist 107 includes disposing a photoresist material on the first seed layer 106; covering portions of the photoresist material; the exposed portions of the photoresist material are then removed to pattern the photoresist material, thereby forming a second patterned photoresist 107. In some embodiments, a portion of the first seed layer 106 is exposed through the second patterned photoresist 107. In some embodiments, the photoresist material is provided by spin coating or other suitable process. In some embodiments, a portion of the first seed layer 106 is covered by a second patterned photoresist 107 as shown in fig. 20. The second patterned photoresist 107 fills the opening 102s. In some embodiments, the second patterned photoresist 107 is at least partially surrounded by the first seed layer 106.

Referring to fig. 21 or 22, according to a step S208 in fig. 8, a conductive material is disposed on the portion of the first seed layer 106 exposed through the second patterned photoresist 107. In some embodiments, the conductive material 108 contacts the first seed layer 106 and fills the opening 102s. In some embodiments, the conductive material 108 includes copper, silver, gold, or the like. In some embodiments, the conductive material 108 is provided by electroplating or any other suitable process.

Referring to fig. 23, according to a step S209 in fig. 8, the second patterned photoresist 107 is removed. In some embodiments, the second patterned photoresist 107 is removed by etching, stripping, or any other suitable process. In some embodiments, the openings 102s are exposed after the second patterned photoresist is removed as shown in fig. 24.

In some embodiments, after the second patterned photoresist 107 is removed as shown in fig. 23, a portion of the conductive material 108 protruding from the etch stop layer 104 is removed as shown in fig. 25. In some embodiments, the portion of the conductive material 108 protruding from the etch stop layer 104 is removed by etching, planarization, chemical Mechanical Polishing (CMP), or any other suitable process.

In some embodiments, after the removal of the second patterned photoresist 107 as shown in fig. 24, an additional dielectric material 109 is disposed on the etch stop layer 104 as shown in fig. 26. In some embodiments, additional dielectric material 109 fills the openings 102s. In some embodiments, additional dielectric material 109 surrounds a portion of conductive material 108. In some embodiments, as shown in fig. 27, the portion of the additional dielectric material 109 and conductive material 108 protruding from the etch stop layer 104 is removed. In some embodiments, the portions of the additional dielectric material 109 and conductive material 108 protruding from the etch stop layer 104 are removed by etching, chemical Mechanical Polishing (CMP), or any other suitable process.

Referring to fig. 28 or 29, according to a step S210 in fig. 8, the etching stop layer 104 is removed. In some embodiments, the etch stop layer 104 is removed by etching or any other suitable process.

In some embodiments, as shown in fig. 28, after the etch stop layer 104 is removed, a portion of the first seed layer 106 and a portion of the conductive material 108 protrude from the dielectric layer 102 g. In some embodiments, as shown in fig. 29, after the etch stop layer 104 is removed, a portion of the first seed layer 106, a portion of the conductive material 108, and a portion of the additional dielectric material 109 are removed.

Referring to fig. 30 or 31, according to a step S211 in fig. 8, the portion of the conductive material 108 protruding from the dielectric layer 102g is removed to form a bonding pad 102d adjacent to the conductive plug 102c and surrounded by the dielectric layer 102 g. In some embodiments, the portions of the conductive material 108 and the first seed layer 106 protruding from the dielectric layer 102g are removed by etching, planarization, CMP, or any other suitable process. In some embodiments, a bond pad 102d is formed that includes a seed layer 102e and a bond pad 102 f. The bonding pad 102d contacts the conductive plug 102c. In some embodiments, as shown in fig. 31, the portion of the additional dielectric material 109 protruding from the dielectric layer 102g is removed; as a result, a remaining portion of the additional dielectric material 109 is bonded to the dielectric layer 102 g.

In some embodiments, after the formation of the bonding pad 102d, as shown in fig. 32, a second seed layer 110 is disposed on the bonding pad 102d, the conductive plug 102c and the dielectric layer 102 g. In some embodiments, the second seed layer 110 is a single layer or a composite stack comprising a material such as copper, titanium, tungsten, or a combination thereof. In some embodiments, the second seed layer 110 is provided by deposition, PVD, or any other suitable process.

In some embodiments, after the deposition of the second seed layer 110, a third patterned photoresist 111 is disposed on the second seed layer 110, as shown in FIG. 33. In some embodiments, the fabrication technique of the third patterned photoresist 111 includes disposing a photoresist material on the second seed layer 110; covering portions of the photoresist material; the exposed portions of the photoresist material are then removed to pattern the photoresist material, thereby forming a third patterned photoresist 111. In some embodiments, a portion of the second seed layer 110 is exposed through the third patterned photoresist 111. In some embodiments, the photoresist material is provided by spin coating or any other suitable process.

In some embodiments, as shown in fig. 34 and 35, a conductive bump 103 is formed on the portion of the second seed layer 110 exposed through the third patterned photoresist 111. In some embodiments, as shown in fig. 34, a metal layer 103b, a barrier layer 103c, and a solder element 103d are sequentially disposed on the portion of the second seed layer 110 exposed through the third patterned photoresist 111. In some embodiments, the metal layer 103b and the barrier layer 103c are provided by electroplating, sputtering, deposition, or any other suitable process.

In some embodiments, the metal layer 103b comprises a conductive material, such as copper, silver, gold, or the like. In some embodiments, the barrier layer 103c comprises titanium, titanium nitride, tantalum nitride, nickel, or the like. In some embodiments, the fabrication technique of the solder assembly 103d includes lamination, deposition, or any suitable process. In some embodiments, the solder assembly 103d includes tin, lead, silver, copper, nickel, or the like. In some embodiments, the solder assembly 103d performs a reflow process to become hemispherical (dome-shaped).

In some embodiments, after the metal layer 103b, the barrier layer 103c, and the solder assembly 103d are disposed, the third patterned photoresist 111 is removed, as shown in fig. 35. In some embodiments, the third patterned photoresist 111 is removed by etching, stripping, or any suitable process.

In some embodiments, a portion of the second seed layer 110 exposed through the metal layer 103b, the barrier layer 103c, and the solder assembly 103d is removed to form an under bump metal layer 103a. In some embodiments, the portion of the second seed layer 110 exposed by the metal layer 103b, the barrier layer 103c, and the solder assembly 103d is removed by etching or any suitable process. In some embodiments, conductive bumps 103 are formed that include an under bump metal layer 103a, a metal layer 103b, a barrier layer 103c, and a solder assembly 103 d. In some embodiments, as shown in fig. 36, a bond wire 112 is disposed and bonded on bond pad 102 d. Bond wire 112 electrically connects semiconductor structure 100 to an external circuit via bond pad 102 d.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or future developed that perform the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate;

a redistribution layer disposed on the substrate and including a dielectric layer disposed on the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to and surrounded by the dielectric layer; and

a conductive bump disposed on the conductive plug;

wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

2. The semiconductor structure of claim 1, wherein a first surface of said conductive plug and a second surface of said bond pad are exposed through said dielectric layer.

3. The semiconductor structure of claim 2, wherein said first surface of said conductive plug is coplanar with said second surface of said bond pad.

4. The semiconductor structure of claim 2, wherein the first surface of the conductive plug and the second surface of the bond pad contact a seed layer of the conductive bump.

5. The semiconductor structure of claim 2, wherein the first surface of the conductive plug, the second surface of the bond pad, and a third surface of the dielectric layer are coplanar.

6. The semiconductor structure of claim 2, wherein said first surface of said conductive plug is completely covered by said conductive bump.

7. The semiconductor structure of claim 2, wherein a first portion of said second surface of said bond pad is covered by said conductive bump, a second portion of said second surface is exposed through said dielectric layer and through said conductive bump, and said first portion is smaller than said second portion.

8. The semiconductor structure of claim 1, wherein an upper cross-section of the bond pad has a ring shape, a fan shape, or a polygonal shape.

9. The semiconductor structure of claim 1, wherein a height of said conductive plug is greater than a thickness of said bond pad.

10. The semiconductor structure of claim 1, wherein said redistribution layer has a conductive element electrically connecting said conductive plug to said substrate.

11. The semiconductor structure of claim 10, wherein said conductive element is electrically connected to said conductive plug via said conductive plug.

12. The semiconductor structure of claim 10, wherein said conductive element is electrically connected to said bond pad via said conductive plug.

13. A semiconductor structure, comprising:

a first substrate; and

a redistribution layer disposed on the first substrate and including a dielectric layer disposed on the first substrate, a conductive plug extending in the dielectric layer, and a bonding pad surrounded by the dielectric layer and contacting the conductive plug;

Wherein the conductive plug is at least partially surrounded by the bond pad.

14. The semiconductor structure of claim 13, further comprising a conductive bump overlying said conductive plug and partially overlying said bond pad.

15. The semiconductor structure of claim 14, wherein a width of said conductive plug is smaller than a width of said conductive bump.

16. The semiconductor structure of claim 14, wherein an interface between said conductive plug and said bond pad is disposed under said conductive bump.

17. The semiconductor structure of claim 14, wherein said conductive bump is disposed on and bonded with an interconnect structure of a second substrate.

18. The semiconductor structure of claim 14, wherein said bond pad comprises a first bond pad and a second bond pad spaced apart from said first bond pad, and said conductive plug is disposed between said first bond pad and said second bond pad.

19. The semiconductor structure of claim 14, further comprising a bond wire disposed on and bonded to the bond pad.

20. The semiconductor structure of claim 14, wherein the first substrate comprises a plurality of elements disposed thereon and a plurality of insulators separating the plurality of elements.

21. A method of fabricating a semiconductor structure, comprising:

providing a substrate and a redistribution layer, wherein the redistribution layer is arranged on the substrate, the redistribution layer is provided with a dielectric layer and a conductive plug, the electric connection layer is arranged on the substrate, and the conductive plug extends into the dielectric layer;

disposing an etch stop layer on the redistribution layer;

disposing a first patterned photoresist on the etch stop layer;

removing a portion of the dielectric layer and a portion of the etch stop layer exposed through the first patterned photoresist;

removing the first patterned photoresist;

disposing a first seed layer on the etch stop layer and on a portion of the dielectric layer exposed by the first patterned photoresist;

disposing a second patterned photoresist on the first seed layer;

disposing a conductive material on a portion of the first seed layer exposed through the second patterned photoresist;

removing the second patterned photoresist;

removing the etch stop layer; and

a portion of the conductive material protruding from the dielectric layer is removed to form a bond pad adjacent to and surrounded by the conductive plug.

22. The method of claim 21, wherein said first seed layer disposed on said etch stop layer contacts said conductive plug.

23. The method of claim 21, wherein said bond pad comprises said first seed layer and said conductive material.

24. The method of claim 21, wherein said portion of said conductive material protrudes from said etch stop layer after said second patterned photoresist is removed.

25. The method of claim 21, wherein removing said portion of said dielectric layer exposed by said first patterned photoresist comprises forming an opening to extend into said dielectric layer and to be disposed adjacent to said conductive plug.

26. The method of claim 25, wherein said conductive plug is at least partially exposed after said opening is formed.

27. The method of claim 25, wherein said opening surrounds said conductive plug.

28. The method of claim 27, wherein said second patterned photoresist fills a portion of said opening.

29. The method of claim 27, wherein said second patterned photoresist is at least partially surrounded by said first seed layer.

30. The method of fabricating a semiconductor structure as recited in claim 27, further comprising:

disposing a dielectric material in the opening and on the etch stop layer; and

a portion of the dielectric material disposed on the etch stop layer is removed.

31. The method of fabricating a semiconductor structure as recited in claim 21, further comprising:

disposing a second seed layer on the bonding pad, the conductive plug and the dielectric layer;

disposing a third patterned photoresist on the second seed layer; and

a conductive bump is formed on a portion of the second seed layer exposed through the third patterned photoresist.