CN116229823A

CN116229823A - Display panel

Info

Publication number: CN116229823A
Application number: CN202111459480.4A
Authority: CN
Inventors: 康沐楷; 陈谚宗; 黄思凯; 陈靖轩
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2023-06-06

Abstract

The invention discloses a display panel which comprises a substrate, a first integrated circuit chip, a second integrated circuit chip and a circuit board. The substrate includes a display region and a non-display region. The first integrated circuit chip and the second integrated circuit chip are disposed within the non-display area and on one side of the display area in the first direction. The first integrated circuit chip or the second integrated circuit chip includes a first edge and a second edge. The circuit board is disposed within the non-display area and between the first integrated circuit chip and the second integrated circuit chip in the second direction, and the circuit board includes a third edge. The first edge is disposed between the second edge and the display area, and the third edge is disposed between the first edge and the second edge.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel with a narrow bezel design.

Background

The display panel is composed of two substrates, a plurality of film layers arranged between the two substrates and various electronic components, so as to achieve the function of displaying pictures. Because the display panel has the characteristics of light and thin profile, low power consumption, no radiation pollution, etc., it has been widely used in various portable or wearable electronic products such as notebook computers (notebook), smart phones (smart phones), watches, and vehicle displays, etc., to provide more convenient information transmission and display.

In the non-display area of the existing display panel, the width of the lower bezel of the display panel is limited to be reduced due to the limit of the bonding technology of the back-end process. Therefore, how to effectively continue to reduce the width of the lower frame of the display panel so as to meet the design of the narrow frame of the display panel is a technical problem to be solved at present.

Disclosure of Invention

The invention aims to solve the technical problem that in the prior art, the lower frame of the display panel cannot be further reduced due to the limit of the bonding technology of the back-end process.

In order to solve the above technical problems, the present invention provides a display panel, which includes a substrate, a first integrated circuit chip, a second integrated circuit chip and a circuit board. The substrate comprises a display area and a non-display area, wherein the non-display area is arranged on at least one side of the display area. The first integrated circuit chip and the second integrated circuit chip are disposed in the non-display area and on one side of the display area in a first direction, and the first integrated circuit chip or the second integrated circuit chip includes a first edge and a second edge. The circuit board is arranged in the non-display area and arranged between the first integrated circuit chip and the second integrated circuit chip in a second direction, the second direction and the first direction are not parallel, and the circuit board comprises a third edge. The first edge is disposed between the second edge and the display area, and the third edge is disposed between the first edge and the second edge.

In the non-display area of the display panel, the circuit board is arranged between the first integrated circuit chip and the second integrated circuit chip in the second direction, so that the width of the lower frame can be reduced. Meanwhile, the arrangement mode is less complex, so that the method can also show better qualification rate and reliability.

Drawings

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the invention.

Fig. 2 is an enlarged schematic view of a first integrated circuit chip, a second integrated circuit chip and a circuit board according to the present invention.

Reference numerals illustrate: 10-display panel; 100-base plate; 102 to a first signal line; 104 to a second signal line; 106 to a first integrated circuit chip; 108-second integrated circuit chips; 110-circuit board; 112. 114, 116, 118, 120, 138, 140, 150, 152-edges; 122 to extension lines; 124. 126, 128, 130, 142, 154-side; 132 to a first bonding pad; 134 to a second bonding pad; 136 to third bonding pads; 144 to fourth bonding pads; 146 to fifth bonding pads; 148 to sixth bonding pads; A1-A5, B1-B3, C1-C2, E1-E2, F1-F2; d1 to the first direction; d2 to the second direction; DR-display area; PR to non-display region.

Detailed Description

The following description sets forth the preferred embodiments of the invention and, together with the drawings, provides further details of the invention and its intended advantages, as will be apparent to those skilled in the art. It should be noted that the drawings are simplified schematic diagrams, and thus only show components and combinations related to the present invention, so as to provide a clearer description of the basic architecture or implementation of the present invention, and actual components and arrangements may be more complex. In addition, for convenience of explanation, the components shown in the drawings of the present invention are not drawn in the same scale as the number, shape, size, etc. of actual implementations, and the detailed proportion thereof may be adjusted according to the design requirements.

A first direction D1 and a second direction D2 are indicated in the following figures. The first direction D1 and the second direction D2 may be parallel to the upper surface of the substrate 100. The second direction D2 and the first direction D1 may not be parallel, for example, the second direction D2 and the first direction D1 may be perpendicular to each other. The following figures may describe the spatial relationship of structures according to a first direction D1 and a second direction D2.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the invention. The display panel 10 of the present invention may be any suitable display panel, such as a liquid crystal display panel, but is not limited thereto. As shown in fig. 1, the display panel 10 includes a substrate 100. The substrate 100 includes a display region DR and a non-display region PR disposed on at least one side of the display region DR. In the present embodiment, the non-display region PR surrounds the display region DR, but is not limited thereto. The substrate 100 may be a hard substrate such as a glass substrate, a plastic substrate, a quartz substrate or a sapphire substrate, or may be a flexible substrate including a Polyimide (PI) material or a polyethylene terephthalate (polyethylene terephthalate, PET) material, but is not limited thereto.

The display panel 10 includes a plurality of first signal lines 102 and a plurality of second signal lines 104 disposed on a substrate 100. The first signal line 102 and the second signal line 104 may be disposed at least in the display region DR, and the first signal line 102 and the second signal line 104 may extend in the first direction D1 in the display region DR. In addition, the first signal line 102 and the second signal line 104 may extend from the display region DR to the non-display region PR. For example, the first signal line 102 and the second signal line 104 may be data lines and may be electrically connected to a plurality of sub-pixels in the display region DR, but not limited thereto.

The display panel 10 includes a first integrated circuit chip 106, a second integrated circuit chip 108, and a circuit board 110 disposed on the substrate 100. The first integrated circuit chip 106, the second integrated circuit chip 108, and the circuit board 110 are disposed within the non-display region PR and on one side of the display region DR in the first direction D1. In addition, the circuit board 110 is disposed between the first integrated circuit chip 106 and the second integrated circuit chip 108 in the second direction D2, and by this arrangement, the width of the lower frame can be reduced.

The first integrated circuit chip 106 includes an edge 112 (or may be referred to as a first edge) and an edge 114 (or may be referred to as a second edge), the second integrated circuit chip 108 includes an edge 116 (or may be referred to as a first edge) and an edge 118 (or may be referred to as a second edge), and the circuit board 110 includes an edge 120 (or may be referred to as a third edge).

Edges

112, 114, 116, 118, and 120 may extend in the second direction D2, but are not limited thereto.

An edge 112 of the first integrated circuit chip 106 is disposed between an edge 114 of the first integrated circuit chip 106 and the display region DR, and an edge 116 of the second integrated circuit chip 108 is disposed between an edge 118 of the second integrated circuit chip 108 and the display region DR. Edge 120 of circuit board 110 is disposed between edge 112 and edge 114 of first integrated circuit chip 106 or between edge 116 and edge 118 of second integrated circuit chip 108. For example, the edge 120 of the circuit board 110 may have an extension line 122 extending along the second direction D2, and the extension line 122 may be located between the edge 112 and the edge 114 of the first integrated circuit chip 106 or between the edge 116 and the edge 118 of the second integrated circuit chip 108 in the first direction D1.

In the first direction D1, a distance A1 is between the edge 120 of the circuit board 110 and the display region DR, a distance A2 is between the edge 112 of the first integrated circuit chip 106 and the display region DR, a distance A3 is between the edge 116 of the second integrated circuit chip 108 and the display region DR, and the distance A1 may be greater than the distance A2 and the distance A3. The distance A2 and the distance A3 may be substantially the same, but are not limited thereto.

In the first direction D1, a distance B1 (or may be referred to as a first distance) is between the edge 120 of the circuit board 110 and the edge 114 of the first integrated circuit chip 106, a distance B2 (or may be referred to as a second distance) is between the edge 112 of the first integrated circuit chip 106 and the edge 114, and a ratio (e.g., B1/B2) of the distance B1 to the distance B2 is greater than or equal to 0.3 and less than or equal to 1.

Similarly, in the first direction D1, a distance C1 (may also be referred to as a first distance) is between the edge 120 of the circuit board 110 and the edge 118 of the second integrated circuit chip 108, a distance C2 (may also be referred to as a second distance) is between the edge 116 and the edge 118 of the second integrated circuit chip 108, and a ratio (e.g., C1/C2) of the distance C1 to the distance C2 is greater than or equal to 0.3 and less than or equal to 1.

The first integrated circuit chip 106 includes a side 124 (or may be referred to as a first side), the circuit board 110 includes a side 126 (or may be referred to as a second side), the side 124 of the first integrated circuit chip 106 and the side 126 of the circuit board 110 are disposed adjacent to each other in the second direction D2, and the side 124 and the side 126 have a distance E1 (or may be referred to as a third distance) in the second direction D2. For example, the distance E1 may be greater than or equal to 0.1 millimeters and less than or equal to 1 millimeter.

Similarly, the second integrated circuit chip 108 includes a side 128 (also referred to as a first side), the circuit board 110 includes a side 130 (also referred to as a second side), the

sides

130 and 126 may be opposite sides of the circuit board 110, the side 128 of the second integrated circuit chip 108 and the side 130 of the circuit board 110 are disposed adjacent to each other in the second direction D2, and the

sides

128 and 130 have a distance E2 (also referred to as a third distance) in the second direction D2. For example, the distance E2 may be greater than or equal to 0.1 millimeters and less than or equal to 1 millimeter. In addition, the

side edges

124, 126, 128 and 130 may extend along the first direction D1, but not limited thereto.

The display panel 10 includes a plurality of first pads 132, a plurality of second pads 134, and a plurality of third pads 136 disposed on the substrate 100 and within the non-display region PR, wherein the first integrated circuit chip 106 covers the first pads 132 and the second pads 134. In the first direction D1, the first pads 132 may be disposed closer to the edge 112 of the first integrated circuit chip 106. The first pads 132 may be arranged in one or more pad rows along the second direction D2, but not limited thereto. The first pad 132 electrically connects the first integrated circuit chip 106 and the first signal line 102 in the display region DR. For example, each first signal line 102 may be electrically connected to a corresponding one of the first pads 132. The first signal line 102 may be, for example, a data line, the first pad 132 may be, for example, an IC output pad and may be, for example, a plurality of display signal pads, and the first integrated circuit chip 106 may output a display signal (e.g., a data signal) to the first signal line 102 and the subpixels within the display region DR through the first pad 132.

In some embodiments, the first pad 132 may be used as a touch signal pad, the first signal line 102 may be used as a sensing signal line, and the touch signal pad is also electrically connected to the sensing signal line in the display region DR. In addition, one end of a sensing signal line can be electrically connected with a touch electrode, so that the touch signal pad can transmit a touch signal to the touch electrode in the display area DR through the sensing signal line.

The second pads 134 may be disposed along the second direction D2 (or side-by-side), and the second pads 134 may be disposed closer to the edge 114 and/or the side 124 of the first integrated circuit chip 106, but not limited thereto. In addition, the second pads 134 are electrically connected to the first integrated circuit chip 106.

The third pads 136 may be disposed along the second direction D2 (or side by side), and may be disposed between the first integrated circuit chip 106 and the second integrated circuit chip 108 in the second direction D2, but is not limited thereto. The third pad 136 may be disposed at one side of the second pad 134 in the second direction D2. The circuit board 110 covers the third pad 136, and the third pad 136 is electrically connected to the circuit board 110. In addition, the third pad 136 is electrically connected to the second pad 134. For example, one third pad 136 may be electrically connected with a corresponding one second pad 134.

The second pad 134 may be, for example, an IC input pad, and the circuit board 110 may provide a signal from an interface or a power line (power line) to the first integrated circuit chip 106 through the third pad 136, the routing between the third pad 136 and the second pad 134, but is not limited thereto.

The third pad 136 includes an edge 138 (or may be called a fourth edge) and an edge 140 (or may be called a fifth edge), and the edge 138 is disposed between the edge 140 and the display region DR. In the first direction D1, a distance A4 is provided between the edge 138 and the display region DR, and the distance A4 may be greater than the distance A1 between the edge 120 of the circuit board 110 and the display region DR.

In the first direction D1, a distance B3 (or may be referred to as a fourth distance) is between the edge 138 of the third pad 136 and the edge 114 of the first integrated circuit chip 106, a distance B2 is between the edge 112 and the edge 114 of the first integrated circuit chip 106, and a ratio of the distance B3 to the distance B2 (e.g., B3/B2) is greater than or equal to 0.3 and less than or equal to 1.

Fig. 2 is an enlarged schematic diagram of the first integrated circuit chip, the second integrated circuit chip and the circuit board according to the present invention. One of the third pads 136 (e.g., a third pad 136 closest to the second pad 134) includes a side 142 (or referred to as a third side), and the side 142 is disposed adjacent to the side 124 of the first integrated circuit chip 106 and has a distance F1 (or referred to as a sixth distance) in the second direction D2. For example, the distance F1 may be greater than or equal to 0.1 millimeters and less than or equal to 1 millimeter.

On the other hand, as shown in fig. 1, the display panel 10 includes a plurality of fourth pads 144, a plurality of fifth pads 146, and a plurality of sixth pads 148 disposed on the substrate 100 and within the non-display region PR, wherein the second integrated circuit chip 108 covers the fourth pads 144 and the fifth pads 146. In the first direction D1, the fourth pads 144 may be disposed closer to the edge 116 of the second integrated circuit chip 108. The fourth pads 144 may be arranged in one or more pad rows along the second direction D2, but not limited to this. The fourth pad 144 electrically connects the second integrated circuit chip 108 and the second signal line 104 in the display region DR. For example, each of the second signal lines 104 may be electrically connected to a corresponding one of the fourth pads 144. The second signal line 104 may be, for example, a data line, the fourth pad 144 may be, for example, an IC output pad and may be, for example, a plurality of display signal pads, and the second integrated circuit chip 108 may output display signals (e.g., data signals) to the second signal line 104 and the subpixels within the display region DR through the fourth pad 144.

In some embodiments, the fourth pad 144 may be used as a touch signal pad, the second signal line 104 may be used as a sensing signal line, and the touch signal pad is also electrically connected to the sensing signal line in the display region DR. In addition, one end of a sensing signal line can be electrically connected with a touch electrode, so that the touch signal pad can transmit a touch signal to the touch electrode in the display area DR through the sensing signal line.

The fifth pads 146 may be disposed along the second direction D2 (or side-by-side), and the fifth pads 146 may be disposed closer to the edge 118 and/or the side 128 of the second integrated circuit chip 108, but are not limited thereto. In addition, the fifth pad 146 is electrically connected to the second integrated circuit chip 108.

The sixth pads 148 may be disposed along the second direction D2 (or side-by-side), and may be disposed between the first integrated circuit chip 106 and the second integrated circuit chip 108 in the second direction D2, but is not limited thereto. The sixth pad 148 may be disposed at one side of the fifth pad 146 in the second direction D2. The circuit board 110 covers the sixth pad 148, and the sixth pad 148 is electrically connected to the circuit board 110. Further, the sixth pad 148 is electrically connected to the fifth pad 146. For example, one sixth pad 148 may be electrically connected with a corresponding one fifth pad 146.

The fifth pad 146 may be, for example, an IC input pad, and the circuit board 110 may provide signals from an interface or a power line (power line) to the second integrated circuit chip 108 through the sixth pad 148, the routing between the sixth pad 148 and the fifth pad 146, but is not limited thereto.

The sixth pad 148 includes an edge 150 (or may be referred to as a sixth edge) and an edge 152 (or may be referred to as a seventh edge), and the edge 150 is disposed between the edge 152 and the display region DR. In the first direction D1, a distance A5 is provided between the edge 150 and the display region DR, and the distance A5 may be greater than the distance A1 between the edge 120 of the circuit board 110 and the display region DR.

In the first direction D1, a distance C3 (or may be referred to as a fifth distance) is provided between the edge 150 of the sixth pad 148 and the edge 118 of the second integrated circuit chip 108, a distance C2 is provided between the edge 116 and the edge 118 of the second integrated circuit chip 108, and a ratio (e.g., C3/C2) of the distance C3 to the distance C2 is greater than or equal to 0.3 and less than or equal to 1.

As shown in fig. 2, one of the sixth pads 148 (e.g., a sixth pad 148 closest to the fifth pad 146) includes a side 154, the side 154 being disposed adjacent to the side 128 of the second integrated circuit chip 108 and having a distance F2 in the second direction D2. For example, the distance F2 may be greater than or equal to 0.1 millimeters and less than or equal to 1 millimeter.

In addition, for example, the first integrated circuit chip 106 may include a plurality of pads disposed on a surface of the first integrated circuit chip 106, at least some of the pads being located to correspond to and electrically connect the first pads 132 and the second pads 134, respectively. The second integrated circuit chip 108 may include a plurality of pads disposed on a surface of the second integrated circuit chip 108, at least some of the pads being located in correspondence with and electrically connected to the fourth pad 144 and the fifth pad 146, respectively. The circuit board 110 may include a plurality of pads disposed on a surface of the circuit board 110, at least some of which are located to correspond to and electrically connect the third pad 136 and the sixth pad 148, respectively.

The first integrated circuit chip 106 and/or the second integrated circuit chip 108 may be disposed on the substrate 100 in the form of a chip (e.g., system on a glass (SOC)) or a system on a glass (SOG)), but is not limited thereto. The circuit board 110 may include, but is not limited to, a flexible circuit board. The number of pads and signal lines in the present invention is not limited to that shown in fig. 1 and 2. In addition, the materials of the pad and the signal line may include conductive materials, such as metal, but not limited thereto.

In summary, in the non-display area of the display panel of the present invention, the circuit board is disposed between the first integrated circuit chip and the second integrated circuit chip in the second direction, or the third pad and the sixth pad of the corresponding circuit board are disposed between the first pad and the second pad of the corresponding first integrated circuit chip and the fourth pad and the fifth pad of the corresponding second integrated circuit chip in the second direction, and by these arrangements, the width of the lower frame can be reduced, for example, to about 2.5 mm. Meanwhile, as the setting modes are less complex, the method can also show better qualification rate and reliability.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, comprising:

the substrate comprises a display area and a non-display area, and the non-display area is arranged on at least one side of the display area;

a first integrated circuit chip and a second integrated circuit chip disposed within the non-display area and disposed on one side of the display area in a first direction, and the first integrated circuit chip or the second integrated circuit chip includes a first edge and a second edge; and

a circuit board disposed in the non-display area and disposed between the first integrated circuit chip and the second integrated circuit chip in a second direction, the second direction being non-parallel to the first direction, and the circuit board including a third edge,

wherein the first edge is disposed between the second edge and the display area, and the third edge is disposed between the first edge and the second edge.

2. The display panel of claim 1, wherein a first distance is provided between the third edge and the second edge in the first direction, a second distance is provided between the first edge and the second edge, and a ratio of the first distance to the second distance is greater than or equal to 0.3 and less than or equal to 1.

3. The display panel of claim 1, wherein the first integrated circuit chip or the second integrated circuit chip includes a first side and the circuit board includes a second side, the first side and the second side are disposed adjacent to each other and have a third distance in the second direction, and the third distance is greater than or equal to 0.1 millimeter and less than or equal to 1 millimeter.

4. The display panel of claim 1, further comprising:

a plurality of first pads disposed in the non-display region, the first pads electrically connecting the first integrated circuit chip and a plurality of first signal lines in the display region;

a plurality of second bonding pads arranged in the non-display area, wherein the second bonding pads are electrically connected with the first integrated circuit chip; and

a plurality of third pads disposed in the non-display area, the third pads electrically connecting the circuit board and the second pads,

wherein the third pad is disposed between the first integrated circuit chip and the second integrated circuit chip in the second direction.

5. The display panel of claim 4, wherein the first integrated circuit chip covers the first pad and the second pad.

6. The display panel of claim 4, wherein one of the third pads includes a fourth edge and a fifth edge, the fourth edge is disposed between the fifth edge and the display area, there is a fourth distance between the fourth edge and the second edge in the first direction, there is a second distance between the first edge and the second edge, and a ratio of the fourth distance to the second distance is greater than or equal to 0.3 and less than or equal to 1.

7. The display panel of claim 4, wherein the first integrated circuit chip includes a first side and one of the third pads includes a third side, the first side and the third side are disposed adjacent to each other and have a sixth distance in the second direction, and the sixth distance is greater than or equal to 0.1 millimeters and less than or equal to 1 millimeter.

8. The display panel of claim 1, further comprising:

a plurality of fourth pads disposed in the non-display region, the fourth pads electrically connecting the second integrated circuit chip and a plurality of second signal lines in the display region;

a plurality of fifth bonding pads disposed in the non-display region, the fifth bonding pads being electrically connected to the second integrated circuit chip; and

a plurality of sixth pads disposed in the non-display area, the sixth pads electrically connecting the circuit board and the fifth pads,

wherein the sixth pad is disposed between the first integrated circuit chip and the second integrated circuit chip in the second direction.

9. The display panel of claim 8, wherein the second integrated circuit chip covers the fourth pad and the fifth pad.

10. The display panel of claim 8, wherein one of the sixth pads includes a sixth edge and a seventh edge, the sixth edge is disposed between the seventh edge and the display area, there is a fifth distance between the sixth edge and the second edge in the first direction, there is a second distance between the first edge and the second edge, and a ratio of the fifth distance to the second distance is greater than or equal to 0.3 and less than or equal to 1.