CN116225673A - Task processing method and device based on many-core chip, processing core and electronic equipment - Google Patents

Task processing method and device based on many-core chip, processing core and electronic equipment Download PDF

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CN116225673A
CN116225673A CN202111474828.7A CN202111474828A CN116225673A CN 116225673 A CN116225673 A CN 116225673A CN 202111474828 A CN202111474828 A CN 202111474828A CN 116225673 A CN116225673 A CN 116225673A
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task
type
processing
target
core
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吴臻志
祝夭龙
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Beijing Lynxi Technology Co Ltd
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Beijing Lynxi Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The disclosure provides a task processing method based on a many-core chip, wherein the many-core chip comprises a first type of processing core and a second type of processing core; the first type processing core is configured with a first task processing program corresponding to a first task type; the task processing method comprises the following steps: under the condition that the task type of the target task is a first task type, inputting task data of the target task of the first task type into a first type processing core so as to enable the first type processing core to execute the target task; and under the condition that the task type of the target task is the second task type, configuring a target task processing program corresponding to the second task type in the second type processing core, and inputting task data of the target task of the second task type into the second type processing core so as to enable the second type processing core to execute the target task based on the configured target task processing program. The disclosure also provides a task processing device, a processing core, a many-core system, an electronic device and a computer readable medium.

Description

Task processing method and device based on many-core chip, processing core and electronic equipment
Technical Field
The disclosure relates to the technical field of computers, and in particular relates to a task processing method based on a many-core chip, a task processing device, a processing core, a many-core system, electronic equipment and a computer readable medium.
Background
The current process of processing task data by the many-core system often processes the task data according to the time sequence of receiving the task data, the task processing method is single, and the task processing method is difficult to adapt to different task processing scene requirements, so that the task processing efficiency is low.
Disclosure of Invention
The disclosure provides a task processing method and device based on a many-core chip, a processing core, a many-core system, electronic equipment and a computer readable medium.
In a first aspect, the present disclosure provides a task processing method based on a many-core chip, where the many-core chip includes a first type of processing core and a second type of processing core; the first type processing core is configured with a first task processing program corresponding to a first task type; the task processing method comprises the following steps:
when the task type of the target task is a first task type, inputting task data of the target task of the first task type into the first type processing core so that the first type processing core can execute the target task based on the configured first task processing program;
Under the condition that the task type of the target task is a second task type, configuring a target task processing program corresponding to the second task type in the second type processing core;
and inputting task data of the target task of a second task type into the second class of processing cores so that the second class of processing cores execute the target task based on the configured target task processing program corresponding to the second task type.
In some embodiments, the first task type comprises an immediate response type; the step of inputting task data of the target task of the first task type to the first type processing core in the case that the task type of the target task is the first task type includes:
and in the case that the task type of the target task is an immediate response type, inputting the task data of the target task of the immediate response type into the first type processing core.
In some embodiments, the second task type includes a delay sensitive and batch-on-demand type; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
Under the condition that the task type of the target task is delay sensitive and needs batch processing, task data of the target task are stored in a first memory;
acquiring real-time waiting time duration and estimated processing time duration corresponding to each target task based on task data of each target task stored in a first memory;
and under the condition that the difference value between the real-time waiting time length corresponding to any one target task and the estimated processing time length corresponding to the target task is smaller than or equal to a preset difference value, configuring a target task processing program which is sensitive to delay and needs to be batched in the second type of processing cores.
In some embodiments, the task data for the target task includes an expected task completion time; the step of acquiring the real-time waiting time length and the estimated processing time length corresponding to each target task based on the task data of each target task stored in the first memory comprises the following steps:
aiming at each target task with a delay sensitive type and a batch processing type, determining the estimated processing time length corresponding to each target task according to the sum of configuration calling and initialization time length, preset scheduling polling time granularity and the estimated calculation time length corresponding to the target task;
And determining the real-time waiting time length corresponding to the target task according to the difference between the expected task completion time and the real-time.
In some embodiments, after the task data of the target task of the second task type is input to the second class of processing cores, the method includes:
and (3) clearing the memory of the first memory, or setting the task data of all the target tasks stored in the first memory as invalid data.
In some embodiments, the second task type includes throughput-sensitive; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
storing task data of the target task into a second memory under the condition that the task type of the target task is throughput sensitive;
and under the condition that the number of the target tasks corresponding to the task data stored in the second memory is equal to or greater than the preset task number, configuring a target task processing program corresponding to the throughput sensitive type in the second type processing core.
In some embodiments, the second task type includes throughput-sensitive; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
storing task data of the target task into a second memory under the condition that the task type of the target task is throughput sensitive;
acquiring the residual memory capacity of the second memory;
and under the condition that the residual storage capacity of the second memory is smaller than or equal to a preset storage capacity, configuring a target task processing program corresponding to the throughput sensitive type in the second type of processing cores.
In some embodiments, after the task data of the target task of the second task type is input to the second class of processing cores, the method further includes:
and clearing the memory of the second memory.
In some embodiments, in a case where the second type of processing core is currently configured with a target task handler corresponding to a throughput-sensitive type, before configuring in the second type of processing core the target task handler corresponding to the delay-sensitive and batch-required type, further comprising: performing configuration initialization operation on the second type of processing cores to remove target task processing programs which are currently configured by the second type of processing cores and correspond to throughput sensitivity;
The configuring, in the second type of processing core, a target task processing program corresponding to the delay sensitive and batch-needed processing type, including: and in response to the completion of the configuration initialization operation, configuring a target task handler corresponding to the delay-sensitive and batch-required type in the second type of processing core.
In some embodiments, after the inputting the task data of the target task of the second task type to the second class of processing cores, the method further includes:
and in response to the second type of processing core executing the target task completion of the delay sensitive and batch processing type, reconfiguring a target task handler corresponding to the throughput sensitive type in the second type of processing core.
In some embodiments, before the step of performing a configuration initialization operation on the second class of processing cores, further comprising: storing task data of the throughput-sensitive target task which has been input to the second class of processing cores to a second memory;
after the step of reconfiguring the target task handler corresponding to the throughput-sensitive type in the second class of processing cores, further includes: and re-inputting the task data of the target task which is stored in the second memory and is sensitive to the throughput to the second type of processing core.
In some embodiments, inputting task data of the target task of a second task type to the second class of processing cores, for the second class of processing cores to execute the target task based on a configured target task handler corresponding to the second task type, includes:
and responding to the completion of the target task of the second task type executed by the second type processing core, and executing configuration initialization operation on the second type processing core so as to clear a target task processing program which is currently configured by the second type processing core and corresponds to the second task type.
In some embodiments, the task processing method further comprises:
responding to the fact that the target task of the second task type is not received within a preset time period, and carrying out dormancy operation on the second type of processing cores in the working state;
and in response to receiving the target task of the second task type, waking up the second type of processing cores in the dormant state.
In a second aspect, the present disclosure provides a task processing device based on a many-core chip, where the many-core chip includes a first type of processing core and a second type of processing core; the first type processing core is configured with a first task processing program corresponding to a first task type; the task processing device includes:
The control module is used for inputting task data of a target task of a first task type to the first type processing core under the condition that the task type of the target task is the first task type, so that the first type processing core can execute the target task based on the configured first task processing program;
the configuration module is used for configuring a target task processing program corresponding to a second task type in the second type processing core under the condition that the task type of the target task is the second task type;
the control module is further configured to input task data of the target task of a second task type to the second class processing core, so that the second class processing core executes the target task based on a configured target task processing program corresponding to the second task type.
In a third aspect, the present disclosure provides a processing core comprising the task processing device provided in the second aspect of the present disclosure.
In a fourth aspect, the present disclosure provides a many-core system, including at least one many-core chip and a task processing device provided in the second aspect of the present disclosure;
the many-core chip comprises a plurality of processing cores, wherein the plurality of processing cores comprise a first type of processing core and a second type of processing core; the first type of processing core is configured with a first task handler corresponding to a first task type.
In some embodiments, at least one processing core of at least one many-core chip includes the task processing device.
In a fifth aspect, the present disclosure provides an electronic device comprising:
a plurality of processing cores; and
a network on chip configured to interact data between the plurality of processing cores and external data;
one or more of the processing cores have one or more instructions stored therein that are executed by one or more of the processing cores to enable one or more of the processing cores to perform the task processing method provided in the first aspect of the present disclosure.
In a sixth aspect, the present disclosure provides a computer readable medium having stored thereon a computer program, wherein the computer program, when executed by a processing core, implements the task processing method as provided in the first aspect of the present disclosure.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
Fig. 1 is a flowchart of a task processing method based on a many-core chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a many-core chip according to an embodiment of the disclosure;
FIG. 3 is a flowchart of a specific implementation of step S101 provided in an embodiment of the present disclosure;
FIG. 4 is a flowchart of a specific implementation of step S102 provided in an embodiment of the present disclosure;
FIG. 5 is a flowchart of a specific implementation of step S402 provided in an embodiment of the present disclosure;
FIG. 6 is a flowchart of another embodiment of step S102 provided in an embodiment of the present disclosure;
FIG. 7 is a flowchart of a specific implementation of a further step S102 provided by an embodiment of the present disclosure;
FIG. 8 is a block diagram of a many-core chip based task processing device according to an embodiment of the present disclosure;
FIG. 9 is a block diagram of a many-core system provided by an embodiment of the present disclosure;
fig. 10 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flowchart of a task processing method based on a many-core chip according to an embodiment of the disclosure. The many-core chip comprises a first type of processing core and a second type of processing core; the first type of processing core is configured with a first task handler corresponding to a first task type. The processing cores of the many-core chip may include an in-core memory, where configuration information corresponding to the processing cores executing the corresponding tasks is stored in the in-core memory of the first type of processing core, for example, may include program data, parameters, and the like.
Referring to fig. 1, an embodiment of the present disclosure provides a task processing method based on a many-core chip, the task processing method including the steps of:
step S101, inputting task data of a target task of a first task type to a first type processing core when the task type of the target task is the first task type, so that the first type processing core executes the target task based on the configured first task processing program.
The target task refers to a task received by the many-core chip. The task types of the target task include a first task type and a second task type. The target tasks of the first task type do not need to be batched, and the target tasks of the second task type need to be batched.
The number of tasks corresponding to each task type configured and executed on the many-core chip is not limited.
In this embodiment, the task types of different tasks are marked by different task type identifiers, for example, a first task type is marked by a first task type identifier, and a second task type is marked by a second task type identifier. If the first task type further comprises a plurality of different subtask types, marking each subtask type by comprising a first task type identifier and a corresponding unique subtask type identifier; if the second task type also includes a plurality of different subtask types, then the task type for each subtask type identifies a same setting.
Fig. 2 is a schematic structural diagram of a many-core chip according to an embodiment of the disclosure. As shown in fig. 2, many-core chip 20 includes a first type of processing core 201 and a second type of processing core 202. Wherein the first type of processing core 201 is configured with a first task handler corresponding to a first task type. The second class of processing cores 202 are not configured with task handlers without executing tasks.
Wherein the first type of processing core 201 may include one or more processing cores and the second type of processing core 202 may include one or more processing cores.
In one embodiment, the first type processing core receives task data of a target task with a task type of a first task type, executes the target task based on a configured first task processing program corresponding to the first task type, calculates the task data of the target task, and outputs an obtained result to an output buffer zone.
Wherein the output buffer may be located on the many-core chip and/or external to the many-core chip. For example, the output buffer may be a double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM, also referred to as DDR) located external to the many-core chip. The output buffer may also be on-chip storage of processing cores on a many-core chip, or on-chip storage of in-core storage of non-processing cores that the processing cores are capable of writing to, without limitation by the present disclosure.
Step S102, if the task type of the target task is the second task type, configuring a target task processing program corresponding to the second task type in the second type processing core.
In one embodiment, in a case that the task type of the target task is the second task type, before configuring the target task handler corresponding to the second task type in the second class of processing cores, the method includes: and acquiring a target task processing program corresponding to the second task type. The target task processing program corresponding to the second task type is stored in the off-chip memory.
Step S103, task data of a target task of a second task type is input to the second class processing core, so that the second class processing core executes the target task based on the configured target task processing program corresponding to the second task type.
In one embodiment, the second type processing core receives task data of a target task of a second task type, executes the target task based on a configured task processing program corresponding to the second task type, calculates task data of the target task, and outputs an obtained result to the output buffer.
According to the task processing method based on the many-core system, when the task type of the target task is the first task type, task data of the target task of the first task type are input to a first type of processing core, so that the first type of processing core can execute the target task based on the configured first task processing program; under the condition that the task type of the target task is the second task type, configuring a target task processing program corresponding to the second task type in the second type processing core, and inputting task data of the target task of the second task type to the second type processing core so that the second type processing core can execute the target task based on the configured target task processing program corresponding to the second task type, classification processing of different types of target tasks can be achieved, task processing efficiency is effectively improved, and therefore performance of the many-core chip facing diversified task processing scenes is improved.
In one embodiment, before the task data of the target task of the first task type is input to the first type processing core (step S101), or before the target task processing program corresponding to the second task type is configured in the second type processing core (step S102), if the task type of the target task is the second task type, the method further includes: and receiving the target task, and determining the task type corresponding to the target task according to the task type identifier corresponding to the target task.
Fig. 3 is a flowchart of a specific implementation of step S101 provided in an embodiment of the disclosure. In one embodiment, the first task type includes an immediate response type. Referring to fig. 3, in a case where a task type of a target task is a first task type, a step of inputting task data of the target task of the first task type to the first type processing core includes:
in step S301, when the task type of the target task is the immediate response type, task data of the immediate response type target task is input to the first type processing core.
The task type of the target task is an immediate response type, which means that the target task is sensitive to delay and requires immediate processing, that is, the many-core chip needs to process the target task immediately whenever receiving a target task of the immediate response type. Therefore, as long as the task type of the target task is the immediate response type, the task processing device directly inputs the task data of the target task to the first type processing core so that the first type processing core can immediately execute the target task based on the configured first task processing program, thereby effectively reducing the task processing delay of the immediate response type target task and improving the task processing efficiency.
In one embodiment, the many-core chip includes a first type of processing core that is a processing core corresponding to an immediate-response type of task type, the processing core configured with a task handler corresponding to the immediate-response type of task type. The processing cores corresponding to the immediate response type of task may include one or more processing cores.
Fig. 4 is a flowchart of a specific implementation of step S102 provided in an embodiment of the disclosure. In one embodiment, the second task type includes a delay sensitive and batch-on-demand type. Referring to fig. 4, in the case where the task type of the target task is the second task type, a step of configuring a target task handler corresponding to the second task type in the second type processing core (the above step S102) includes the following steps S401 to S403:
in step S401, task data of the target task is stored in the first memory when the task type of the target task is delay sensitive and needs batch processing.
The task type of the target task is delay sensitive and needs batch processing, which means that the target task is delay sensitive but can be executed in a suspending way, and waits for batch processing with other target tasks of the same type. The first memory is a memory for storing task data of a target task that is delay sensitive and requires batch processing. In some embodiments, the first memory is an off-chip memory, e.g., DDR.
Step S402, based on task data of each target task stored in the first memory, acquiring real-time waiting time duration and estimated processing time duration corresponding to each target task.
The task data of the target task includes an expected task completion time, and the expected task completion time is used for indicating that the target task needs to be processed and completed before the expected task completion time. The real-time waiting time length corresponding to the target task is the real-time length of the real-time from the expected task completion time, namely the difference between the expected task completion time and the real-time. The estimated processing time length corresponding to the target task is the time length required for estimating the execution completion of the target task from the start of the target task processing program corresponding to the second task type.
Step S403, if the difference between the real-time waiting duration corresponding to any one target task and the estimated processing duration corresponding to the target task is less than or equal to the preset difference, configuring a target task processing program corresponding to delay-sensitive and batch-processing-required processing in the second type of processing core.
The preset difference value is a value greater than or equal to 0, and a specific value of the preset difference value may be set according to an actual scene, which is not specifically limited in this embodiment.
In some embodiments, the preset difference is preferably set to 0. When the difference value between the real-time waiting time length corresponding to any one target task and the estimated processing time length corresponding to the target task is equal to 0, the real-time waiting time length corresponding to the target task is equal to the estimated processing time length corresponding to the target task.
In this embodiment, the difference between the real-time waiting duration corresponding to any one of the target tasks and the estimated processing duration corresponding to the target task is smaller than or equal to a preset difference, which indicates that, among all the target tasks stored in the first memory, there is a target task that needs to be executed immediately. Under the situation, task data of all target tasks stored in the first memory are input to the second type of processing core for batch processing, so that the second type of processing core can batch process all target tasks based on configured target task processing programs corresponding to delay sensitivity and batch processing requirements, and the time of each target task stored in the first memory after being executed is smaller than or equal to the expected task completion time carried by the task data of each target task.
In an embodiment, when the difference between the real-time waiting duration corresponding to any one of the target tasks and the estimated processing duration corresponding to the target task is less than or equal to the preset difference, after the target task processing program corresponding to the delay-sensitive and batch-required type is configured in the second type processing core (step S403), task data of the target task corresponding to the delay-sensitive and batch-required type is input to the second type processing core configured with the target task processing program corresponding to the delay-sensitive and batch-required type, so that the second type processing core configured with the target task processing program corresponding to the delay-sensitive and batch-required type executes the target task corresponding to the delay-sensitive and batch-required type based on the configured target task processing program.
In one embodiment, after inputting task data of a target task of a delay-sensitive and batch-required type to a second type of processing core configured with a target task handler corresponding to the delay-sensitive and batch-required type, the method includes: the memory of the first memory is emptied, so that occupation of storage resources is avoided; or, setting the task data of all the target tasks stored in the current first memory as invalid data so as to avoid that the processed task data influence the subsequent task processing process.
Fig. 5 is a flowchart of a specific implementation of step S402 provided in an embodiment of the disclosure. Referring to fig. 5, the step of acquiring a real-time waiting duration and an estimated processing duration corresponding to each target task based on task data of each target task stored in the first memory includes:
step S501, for each target task with a delay sensitive type and a batch processing type, determining a predicted processing time length corresponding to the target task according to a sum of a configuration calling and initializing time length, a preset scheduling polling time granularity and a predicted computing time length corresponding to the target task.
The configuration calling and initializing time is the time for initializing the task processing program configured by the second type of processing core and configuring the task processing program corresponding to the target task to the second type of processing core. The scheduled polling time granularity is a time interval during which the task processing device polls the first memory any two adjacent times to schedule task data for a target task.
The estimated calculation time length corresponding to the target task is the estimated time length for the second type of processing core configured with the target task processing program corresponding to the delay sensitive and batch processing type to execute the target task.
In one embodiment, the estimated computing time length corresponding to the target task is obtained based on historical task execution data statistics of a second type of processing cores of the many-core chip. The historical task execution data comprises calculation time lengths of a plurality of historical tasks, wherein the calculation time lengths are configured with target task processing programs which are sensitive to delay and need batch processing, and the task similarity between the second type of processing cores and the target tasks is greater than a preset threshold value. The task similarity may be evaluated according to the task content of the actual task, which is not specifically limited in this embodiment. In this embodiment, the method for obtaining the estimated computation time length corresponding to the target task based on statistics of historical task execution data, for example, average the computation time lengths corresponding to a plurality of historical tasks to be used as the estimated computation time length corresponding to the target task, or take the mode from the computation time lengths of a plurality of historical tasks to be used as the estimated computation time length corresponding to the target task, etc. In this embodiment, the estimated calculation time length is determined by the historical task execution data, and the target task does not need to be compiled in advance, so that the speed of determining the estimated calculation time length is high in this embodiment.
In another embodiment, under the condition that the many-core chip compiles the task execution process of the target task in advance, determining the execution time length of the second type of processing core configured with the target task processing program which is sensitive to delay and needs to be batched and corresponds to the target task as the estimated calculation time length corresponding to the target task in the pre-compiling process. Because the estimated calculation time length is determined by compiling the task execution process of the target task, the accuracy of the estimated calculation time length determined by the implementation is high.
In the embodiment of the disclosure, the determination method of the estimated processing time length may not be limited to the two manners of determining the estimated processing time length, but may also be determined by other manners.
Step S502, determining the real-time waiting time length corresponding to the target task according to the difference between the expected task completion time and the real-time.
For example, the real-time is 13:00, the expected task completion time is 13:10, and the real-time waiting time corresponding to the target task is 10 minutes. Because the real-time is continuously changed, the real-time waiting time length corresponding to the target task is also continuously reduced along with the change of the real-time.
The above description sequence of step S501 and step S502 does not limit the execution sequence of step S501 and step S502, and step S501 may be executed before step S502 or after step S502, or both may be executed simultaneously.
Fig. 6 is a flowchart of another specific implementation of step S102 provided in an embodiment of the disclosure. In one embodiment, the second task type includes throughput-sensitive. Referring to fig. 6, in the case where the task type of the target task is the second task type, a step of configuring a target task handler corresponding to the second task type in the second type processing core includes:
in step S601, when the task type of the target task is throughput sensitive, task data of the target task is stored in the second memory.
The task type of the target task is throughput sensitive, and the target task representing the task type can be processed only when reaching the preset task number. The second memory is a memory for storing task data of the throughput-sensitive target task. In some embodiments, the second memory may be a DDR.
In one embodiment, in a case that the task type of the target task is throughput sensitive, before storing the task data of the target task in the second memory, the method includes: a target task is received.
In one embodiment, after task data of the target task is stored in the second memory, it is determined whether the number of target tasks corresponding to the task data stored in the second memory is equal to or greater than a preset task number. And returning to the step of receiving the target tasks under the condition that the number of the target tasks corresponding to the task data stored in the second memory is smaller than the preset task number.
In step S602, when the number of target tasks corresponding to the task data stored in the second memory is equal to or greater than the preset number of tasks, a target task processing program corresponding to the second task type is configured in the second type processing core.
Under the condition that the number of target tasks corresponding to the task data stored in the second memory is equal to or greater than the preset number of tasks, the number of target tasks indicating the task type is accumulated to reach the throughput requirement, and batch processing can be performed on the target tasks.
According to the embodiment, the automatic control of batch processing of the target tasks can be realized by configuring the number of the target tasks to be processed, and the performance of the many-core chip facing diversified task processing scenes is improved.
Fig. 7 is a flowchart of a specific implementation of still another step S102 provided in an embodiment of the disclosure. In one embodiment, the second task type includes throughput-sensitive. Referring to fig. 7, in the case where the task type of the target task is the second task type, a step of configuring a target task handler corresponding to the second task type in the second type processing core includes:
In step S701, in case that the task type of the target task is throughput sensitive, task data of the target task is stored in the second memory.
Step S702, obtaining the remaining storage amount of the second memory.
In one embodiment, after the remaining storage amount of the second memory is acquired, it is determined whether the remaining storage amount of the second memory is less than or equal to a preset storage amount. The preset storage amount may be set according to an actual application scenario, which is not specifically limited in this embodiment. In this embodiment, when the remaining storage amount of the second memory is greater than the preset storage amount, it is indicated that the second memory can also continue to store the target task, and therefore, when the remaining storage amount of the second memory is greater than the preset storage amount, the step of receiving the target task may be returned.
In step S703, in the case where the remaining storage amount of the second memory is less than or equal to the preset storage amount, a target task processing program corresponding to the throughput sensitive type is configured in the second type processing core.
In the case where the remaining storage amount of the second memory is smaller than or equal to the preset storage amount, the second memory may not be able to continue to store the target task, so that batch processing may be performed on the target task at this time.
According to the embodiment, the automatic control of batch processing of the target task can be realized by configuring the preset storage amount, and the performance of the many-core chip facing the diversified task processing scene is improved.
In some embodiments, the above-described embodiment of step S102 shown in fig. 7 may be performed based on the embodiment of step S102 shown in fig. 6. For example, after task data of the target task is stored in the second memory, it is determined whether the number of target tasks corresponding to the task data stored in the second memory is equal to or greater than a preset task number. The step of acquiring the remaining storage amount of the second memory may be performed (step S702) in the case where the number of target tasks corresponding to the task data stored in the second memory is smaller than the number of preset tasks, and the target task processing program corresponding to the throughput sensitive type may be configured in the second type processing core in the case where the remaining storage amount of the second memory is smaller than or equal to the preset storage amount.
In the case where the remaining storage amount of the second memory is smaller than or equal to the preset storage amount, the second memory may not be able to continue storing the target task, so that the target task may be batched even if the number of target tasks of the task type does not accumulate to reach the throughput requirement at this time.
In one embodiment, after configuring a target task handler corresponding to the throughput sensitive type in the second type of processing core, task data of a target task of the second task type is input to the second type of processing core, including: task data of a target task of a throughput-sensitive type is input to a second type of processing core configured with a target task handler corresponding to the throughput-sensitive type.
In one embodiment, after inputting task data of a target task of a second task type to a second class of processing cores configured with target task handlers corresponding to throughput-sensitive types, the method further includes: and (3) clearing the memory of the second memory so that the second memory can be used in the subsequent task processing process.
In one implementation scenario, the many-core chip can only provide enough second type processing cores for the target tasks of the delay-sensitive and batch-required type to configure the target task processing programs corresponding to the delay-sensitive and batch-required type within the same time period, or provide enough second type processing cores for the target tasks of the throughput-sensitive type to configure the task processing programs corresponding to the throughput-sensitive type, so that it is difficult to simultaneously provide enough second type processing cores for the target tasks of the delay-sensitive and batch-required type and the target tasks of the throughput-sensitive type respectively to configure the corresponding task processing programs.
In some embodiments, the second task type comprises throughput-sensitive in some embodiments. In the case where the second type processing core is processing a target task of a delay-sensitive and batch-required type, that is, the second type processing core is currently configured with a target task handler corresponding to the delay-sensitive and batch-required type, the step of configuring the target task handler corresponding to the throughput-sensitive type in the second type processing core (step S602 or step S703) includes: and in response to the second type of processing core executing the delay-sensitive and batch-processing-required target task completion, configuring a target task handler corresponding to the throughput-sensitive type in the second type of processing core.
The target tasks which are delay sensitive and require batch processing are delay sensitive, and have requirements on the processing time limit of the tasks, while the target tasks which are throughput sensitive have no requirements on the processing time limit of the tasks. Therefore, in the case that the second type processing core is currently executing the target task of the delay sensitive and batch processing type, the second type processing core can wait for the completion of executing the target task of the delay sensitive and batch processing type, and then configure the step of the target task processing program corresponding to the throughput sensitive on the second type processing core so as to process the target task of the throughput sensitive. By the embodiment, the interruption of the task processing process of the target task sensitive to delay can be effectively avoided, and the task processing efficiency can be effectively improved.
In other embodiments, the second task type includes delay sensitive and batch-needed processing. In the case that the second type of processing core is processing a throughput-sensitive target task, that is, the second type of processing core is currently configured with a target task handler corresponding to the throughput-sensitive target task handler, before the step of configuring the second type of processing core with a target task handler corresponding to the delay-sensitive target task handler and the batch-required target task handler (step 403 above), the method further includes: and storing task data of the throughput sensitive target task input to the second type of processing core into a second memory, and executing configuration initialization operation on the second type of processing core to clear the target task processing program corresponding to the throughput sensitive currently configured by the second type of processing core. Before the configuration initialization operation is performed on the second type of processing core, task data of the throughput-sensitive target task input to the second type of processing core is stored in the second memory, so that task data of the throughput-sensitive target task being processed by the second type of processing core can be prevented from being lost, and subsequent automatic recovery of processing of the throughput-sensitive target task is facilitated.
In this embodiment, configuring a target task handler corresponding to a delay-sensitive and batch-needed type in the second type of processing core (step 403 above) includes: in response to completion of the configuration initialization operation, a target task handler corresponding to the delay-sensitive and batch-needed processing is configured in the second class of processing cores.
The target tasks of the delay-sensitive and batch-processing-requiring type are sensitive to delay and have a requirement on processing time limit, while the target tasks of the throughput-sensitive type have a requirement on task processing time limit. Therefore, even when the second type processing core is currently executing the throughput-sensitive target task, it is required to control the second type processing core to suspend executing the throughput-sensitive target task and store task data of the throughput-sensitive target task back to the second memory, so as to preferentially execute the delay-sensitive and batch-type target task, so as to avoid that the actual processing completion time of the delay-sensitive and batch-type target task exceeds the corresponding expected task completion time.
In this embodiment, after a target task processing program corresponding to the delay-sensitive and batch-required type is configured in the second type processing core, task data of the target task corresponding to the delay-sensitive and batch-required type is input to the second type processing core configured with the target task processing program corresponding to the delay-sensitive and batch-required type, so that the second type processing core can execute the target task based on the configured target task processing program corresponding to the delay-sensitive and batch-required type. According to the method and the device for processing the target tasks, the order of the target tasks processed by the second type of processing cores can be reasonably arranged, the target tasks which are sensitive to delay and need to be batched are preferentially processed, the time for actually processing the target tasks which are sensitive to delay and need to be batched is prevented from exceeding the corresponding expected task completion time, and the task processing efficiency can be effectively improved.
In this embodiment, after the delay-sensitive and batch-type target task is preferentially executed, the suspended throughput-sensitive target task may be continuously executed. Thus, after inputting task data of a target task that is delay-sensitive and batch-wise to a second type of processing core configured with a target task handler that corresponds to the delay-sensitive and batch-wise, the method includes: and in response to the second type of processing core executing the target task which is sensitive to delay and needs batch processing, reconfiguring a target task processing program corresponding to the throughput sensitive type in the second type of processing core, and re-inputting task data of the throughput sensitive target task stored in the second memory into the second type of processing core. By the embodiment, the priority processing of the target tasks which are sensitive to delay and need to be batched can be realized, the processing of the target tasks which are sensitive to throughput can be automatically recovered after the priority processing of the target tasks which are sensitive to delay and need to be batched is finished, the task processing efficiency can be effectively improved, and the performance of the many-core chip facing diversified task processing scenes is further improved.
In one embodiment, in order to avoid affecting the efficiency of the second type processing core to execute the target tasks of different task types, task data of the target tasks of the second task type are input to the second type processing core, so that the second type processing core executes the target tasks based on the configured target task handler corresponding to the second task type (step S102 above), and then includes:
And responding to the completion of the target task of the second task type executed by the second type processing core, and executing configuration initialization operation on the second type processing core so as to clear the target task processing program corresponding to the second task type currently configured by the second type processing core.
Wherein the second task type comprises a delay sensitive and batch-on-demand type and/or a throughput sensitive type.
In one embodiment, in order to reduce energy consumption and prolong the service life of the chip, the task processing method in the present disclosure further includes:
and step one, responding to the fact that the target task of the second task type is not received within a preset time period, and carrying out dormancy operation on the second type of processing cores in the working state, wherein the second type of processing cores are in a non-working state after dormancy.
The duration corresponding to the predetermined time period of the second task type may be set according to an actual application scenario, which is not specifically limited in this embodiment. For example, the predetermined period may be a period of time from the last time the target task of the second task type was received, or may be a fixed period of time set in advance. The duration corresponding to the predetermined time period may also be set according to an actual application scenario.
And step two, in response to receiving the target task of the second task type, waking up the second type of processing core in the dormant state, wherein the second type of processing core is in a working state after waking up.
According to the embodiment of the disclosure, the second type processing core can automatically enter the dormant state under the condition that the task to be processed is not needed in a period of time, the condition that the second type processing core is still in the working state for a long time under the condition that the task to be processed is not needed is avoided, and the effect of saving energy consumption can be achieved. Meanwhile, the service life of the many-core chip where the processing core is located is effectively prolonged.
Fig. 8 is a block diagram of a task processing device based on a many-core chip according to an embodiment of the disclosure.
Referring to fig. 8, a task processing device 800 provided in an embodiment of the present disclosure includes: a control module 801 and a configuration module 802.
The control module 801 is configured to input task data of a target task of a first task type to a first type processing core when the task type of the target task is the first task type, so that the first type processing core executes the target task based on a configured first task handler.
And a configuration module 802, configured to configure, in the second type of processing core, a target task handler corresponding to the second task type, if the task type of the target task is the second task type.
The control module 801 is further configured to input task data of a target task of a second task type to the second processing core, so that the second processing core executes the target task based on the configured target task handler corresponding to the second task type.
In one embodiment, the first task type includes a delay sensitive and batch-on-demand type. The configuration module 802 includes a storage unit, an acquisition unit, and a processing unit.
The storage unit is used for storing task data of the target task into the first memory under the condition that the task type of the target task is delay sensitive and needs batch processing.
The acquisition unit is used for acquiring real-time waiting time duration and estimated processing time duration corresponding to each target task based on the task data of each target task stored in the first memory.
And the processing unit is used for configuring a target task processing program which corresponds to the delay-sensitive and batch-processing-required type in the second type of processing core under the condition that the difference value between the real-time waiting time length corresponding to any one target task and the estimated processing time length corresponding to the target task is smaller than or equal to a preset difference value.
In one embodiment, the second task type includes throughput-sensitive. The configuration module 802 includes a storage unit, an acquisition unit, and a processing unit.
And the storage unit is used for storing task data of the target task into the second memory under the condition that the task type of the target task is throughput sensitive.
And the processing unit is used for configuring a target task processing program corresponding to the second task type in the second type processing core under the condition that the number of target tasks corresponding to the task data stored in the second memory is equal to or greater than the preset task number.
The acquisition unit is used for acquiring the residual memory of the second memory under the condition that the number of target tasks corresponding to the task data stored in the second memory is smaller than the preset task number.
And the processing unit is used for configuring a target task processing program corresponding to the throughput sensitive type in the second type of processing cores under the condition that the residual storage capacity of the second memory is smaller than or equal to the preset storage capacity.
In one embodiment, task processing device 800 further includes: and a state adjustment module.
The state adjustment module is used for responding to the fact that the target task is not received in a preset time period, and performing dormancy operation on the processing core corresponding to the second task type in the working state. The second task type includes a delay sensitive and batch-on-demand type and a throughput sensitive type.
The state adjustment module is further configured to wake up a processing core corresponding to the second task type in the sleep state in response to receiving the target task.
The task processing device based on the many-core system provided by the embodiment of the disclosure, a control module, a first type processing core and a second type processing core, wherein the control module is used for inputting task data of a target task of a first task type to the first type processing core under the condition that the task type of the target task is the first task type, so that the first type processing core can execute the target task based on a configured first task processing program; the configuration module is used for configuring a target task processing program corresponding to the second task type in the second type processing core under the condition that the task type of the target task is the second task type, and the control module is also used for inputting task data of the target task of the second task type into the second type processing core so that the second type processing core can execute the target task based on the configured target task processing program corresponding to the second task type, so that classification processing of different types of target tasks can be realized, the task processing efficiency is effectively improved, and the performance of the many-core chip facing diversified task processing scenes is further improved.
The embodiment of the disclosure also provides a processing core, which comprises the task processing device.
Fig. 9 is a block diagram of a many-core system according to an embodiment of the present disclosure.
Referring to fig. 9, the disclosed embodiment also provides a many-core system 900, including at least one many-core chip 901 and a task processing device 902.
The many-core chip 901 includes a plurality of processing cores, where the plurality of processing cores includes a first type of processing core and a second type of processing core. The specific structure of the many-core chip 901 may be referred to the structure of the many-core chip shown in fig. 2 in the foregoing embodiments of the disclosure, and will not be described herein.
The specific structure of the task processing device 902 may be referred to as the structure of the task processing device shown in fig. 7 in the foregoing embodiments of the present disclosure, and will not be described herein.
In one embodiment, the many-core system 900 further includes a memory, wherein the memory includes a first memory and/or a second memory.
In one embodiment, at least one processing core of at least one many-core chip 901 includes task processing device 902 described above. That is, the task processing device 902 may be disposed on the many-core chip 901, or may be disposed outside the many-core chip 901. Only the case where the task processing device 902 is provided outside the many-core chip 901 is shown in fig. 9.
Fig. 10 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Referring to fig. 10, an embodiment of the present disclosure provides an electronic device including a plurality of processing cores 1001 and a network-on-chip 1002, wherein the plurality of processing cores 1001 are connected to the network-on-chip 1002, and the network-on-chip 1002 is configured to interact data between the plurality of processing cores and external data.
Wherein one or more processing cores 1001 have one or more instructions stored therein that are executed by the one or more processing cores 1001 to enable the one or more processing cores 1001 to perform the task processing method described above.
Furthermore, the embodiment of the present disclosure also provides a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements the task processing method described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (19)

1. A task processing method based on many-core chip, the said many-core chip includes first kind of processing core and second kind of processing core; the first type processing core is configured with a first task processing program corresponding to a first task type; the task processing method comprises the following steps:
when the task type of the target task is a first task type, inputting task data of the target task of the first task type into the first type processing core so that the first type processing core can execute the target task based on the configured first task processing program;
Under the condition that the task type of the target task is a second task type, configuring a target task processing program corresponding to the second task type in the second type processing core;
and inputting task data of the target task of a second task type into the second class of processing cores so that the second class of processing cores execute the target task based on the configured target task processing program corresponding to the second task type.
2. The task processing method according to claim 1, wherein the first task type includes an immediate response type; the step of inputting task data of the target task of the first task type to the first type processing core in the case that the task type of the target task is the first task type includes:
and in the case that the task type of the target task is an immediate response type, inputting the task data of the target task of the immediate response type into the first type processing core.
3. A task processing method as claimed in claim 1, wherein the second task type comprises a delay sensitive and batch-on-demand type; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
Under the condition that the task type of the target task is delay sensitive and needs batch processing, task data of the target task are stored in a first memory;
acquiring real-time waiting time duration and estimated processing time duration corresponding to each target task based on task data of each target task stored in a first memory;
and under the condition that the difference value between the real-time waiting time length corresponding to any one target task and the estimated processing time length corresponding to the target task is smaller than or equal to a preset difference value, configuring a target task processing program which is sensitive to delay and needs to be batched in the second type of processing cores.
4. A task processing method according to claim 3, wherein the task data of the target task includes an expected task completion time; the step of acquiring the real-time waiting time length and the estimated processing time length corresponding to each target task based on the task data of each target task stored in the first memory comprises the following steps:
aiming at each target task with a delay sensitive type and a batch processing type, determining the estimated processing time length corresponding to each target task according to the sum of configuration calling and initialization time length, preset scheduling polling time granularity and the estimated calculation time length corresponding to the target task;
And determining the real-time waiting time length corresponding to the target task according to the difference between the expected task completion time and the real-time.
5. A task processing method according to claim 3, wherein after the task data of the target task of the second task type is input to the second type of processing core, comprising:
and (3) clearing the memory of the first memory, or setting the task data of all the target tasks stored in the first memory as invalid data.
6. The task processing method according to claim 1, wherein the second task type includes a throughput-sensitive type; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
storing task data of the target task into a second memory under the condition that the task type of the target task is throughput sensitive;
and under the condition that the number of the target tasks corresponding to the task data stored in the second memory is equal to or greater than the preset task number, configuring a target task processing program corresponding to the throughput sensitive type in the second type processing core.
7. The task processing method according to claim 1, wherein the second task type includes a throughput-sensitive type; the step of configuring, in the second type processing core, a target task processing program corresponding to the second task type, where the task type of the target task is the second task type, includes:
storing task data of the target task into a second memory under the condition that the task type of the target task is throughput sensitive;
acquiring the residual memory capacity of the second memory;
and under the condition that the residual storage capacity of the second memory is smaller than or equal to a preset storage capacity, configuring a target task processing program corresponding to the throughput sensitive type in the second type of processing cores.
8. The task processing method according to claim 6, wherein after the task data of the target task of the second task type is input to the second class processing core, further comprising:
and clearing the memory of the second memory.
9. A task processing method according to claim 3, wherein, in a case where the second type of processing core is currently configured with a target task handler corresponding to a throughput-sensitive type, before configuring the target task handler corresponding to the delay-sensitive and batch-required type in the second type of processing core, further comprising: performing configuration initialization operation on the second type of processing cores to remove target task processing programs which are currently configured by the second type of processing cores and correspond to throughput sensitivity;
The configuring, in the second type of processing core, a target task processing program corresponding to the delay sensitive and batch-needed processing type, including: and in response to the completion of the configuration initialization operation, configuring a target task handler corresponding to the delay-sensitive and batch-required type in the second type of processing core.
10. The task processing method according to claim 9, wherein after the task data of the target task of the second task type is input to the second-class processing core, further comprising:
and in response to the second type of processing core executing the target task completion of the delay sensitive and batch processing type, reconfiguring a target task handler corresponding to the throughput sensitive type in the second type of processing core.
11. The task processing method according to claim 10, wherein, before the step of performing a configuration initialization operation on the second type of processing core, further comprising: storing task data of the throughput-sensitive target task which has been input to the second class of processing cores to a second memory;
after the step of reconfiguring the target task handler corresponding to the throughput-sensitive type in the second class of processing cores, further includes: and re-inputting the task data of the target task which is stored in the second memory and is sensitive to the throughput to the second type of processing core.
12. The task processing method according to claim 1, wherein, after inputting task data of the target task of a second task type to the second class processing core for the second class processing core to execute the target task based on a configured target task handler corresponding to the second task type, comprising:
and responding to the completion of the target task of the second task type executed by the second type processing core, and executing configuration initialization operation on the second type processing core so as to clear a target task processing program which is currently configured by the second type processing core and corresponds to the second task type.
13. The task processing method according to claim 1, wherein the task processing method further comprises:
responding to the fact that the target task of the second task type is not received within a preset time period, and carrying out dormancy operation on the second type of processing cores in the working state;
and in response to receiving the target task of the second task type, waking up the second type of processing cores in the dormant state.
14. A task processing device based on a many-core chip, wherein the many-core chip comprises a first type of processing core and a second type of processing core; the first type processing core is configured with a first task processing program corresponding to a first task type; the task processing device includes:
The control module is used for inputting task data of a target task of a first task type to the first type processing core under the condition that the task type of the target task is the first task type, so that the first type processing core can execute the target task based on the configured first task processing program;
the configuration module is used for configuring a target task processing program corresponding to a second task type in the second type processing core under the condition that the task type of the target task is the second task type;
the control module is further configured to input task data of the target task of a second task type to the second class processing core, so that the second class processing core executes the target task based on a configured target task processing program corresponding to the second task type.
15. A processing core comprising the task processing device of claim 13.
16. A many-core system comprising at least one many-core chip and the task processing device of claim 14;
the many-core chip comprises a plurality of processing cores, wherein the plurality of processing cores comprise a first type of processing core and a second type of processing core; the first type of processing core is configured with a first task handler corresponding to a first task type.
17. The many-core system of claim 16, wherein at least one processing core of at least one many-core chip comprises the task processing device.
18. An electronic device, comprising:
a plurality of processing cores; and
a network on chip configured to interact data between the plurality of processing cores and external data;
one or more of the processing cores having one or more instructions stored therein, the one or more instructions being executable by the one or more processing cores to enable the one or more processing cores to perform the task processing method of any one of claims 1-13.
19. A computer readable medium having stored thereon a computer program, wherein the computer program when executed by a processing core implements the task processing method according to any of claims 1-13.
CN202111474828.7A 2021-12-03 2021-12-03 Task processing method and device based on many-core chip, processing core and electronic equipment Pending CN116225673A (en)

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