CN116225626A

CN116225626A - ZNS SSD-oriented multi-chip cooperative scheduling method

Info

Publication number: CN116225626A
Application number: CN202211462891.3A
Authority: CN
Inventors: 刘人萍; 龙林波; 谭振华
Original assignee: Chongqing University of Post and Telecommunications
Current assignee: Chongqing University of Post and Telecommunications
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-06-06

Abstract

The invention relates to the technical field of computer storage, in particular to a ZNS SSD-oriented multi-chip collaborative scheduling method; the method aims at minimizing the total response time of all requests, and designs a first multi-chip cooperation method and a second multi-chip cooperation method; after the ZNS SSD device receives the request, converting the request through a partition conversion layer, and splitting the converted request into a plurality of transactions according to a partition mapping module by an SSD controller, wherein each transaction corresponds to one chip; if the request is selected by a scheduling algorithm, the transaction scheduling module performs position scheduling on all transactions in the request according to the scheduling algorithm and a first multi-chip cooperation method; if the request is not selected by the scheduling algorithm, the transaction scheduling module performs position scheduling on all transactions in the request according to a second multi-chip cooperation method; the invention further reduces the total response time of all requests on the basis of ensuring the scheduling effect of the existing scheduling algorithm.

Description

ZNS SSD-oriented multi-chip cooperative scheduling method

Technical Field

The invention relates to the technical field of computer storage, in particular to a ZNS SSD-oriented multi-chip collaborative scheduling method.

Background

Solid State Disk (SSD) based on flash memory media is widely used in modern computer systems, such as memory centers, personal computers, embedded devices, etc., due to its high performance, low power consumption, etc. Due to the advent of the big data and cloud computing age, the performance requirements of users on SSDs are further improved, however, mismatch of the characteristics of the conventional block interfaces and flash memory media gradually becomes one of the reasons that prevent further improvement of the performance of SSDs. Therefore, a ZNS (Zoned Namespace) interface is proposed as a substitute for a conventional block interface to make up for the shortfall of the conventional block interface, thereby further improving the performance of the SSD.

In one aspect, the ZNS interface divides the logical address space into fixed-size partitions (zones) so that the host can more reasonably partition data placement according to its own application information to reduce garbage collection overhead. On the other hand, the ZNS interface specifies that each partition must be written sequentially and rewritten after reset (reset) so that the writing of data more closely conforms to the characteristics of the flash media to avoid unnecessary conversion. In addition, based on the above mode, only the mapping relation from the partition to the physical Block (Block) needs to be maintained inside the ZNS SSD device, so that the space overhead of the mapping table is reduced. Although the NVMe ZNS specification does not specify a specific partition mapping method, in order to be able to exploit the chip parallelism of the SSD, each partition typically needs to be mapped onto multiple chips so that the requests of that partition can be responded to in parallel by the chips. However, scheduling within SSD devices often only considers scheduling of transactions within a single chip (e.g., fairness scheduling), while ignoring other chips whose cooperation responds to the same request, resulting in increased response time for some other requests.

Disclosure of Invention

In view of the above problems, the present invention aims to provide a multi-chip collaborative scheduling method for a ZNS SSD device, which is used in combination with an existing scheduling algorithm, so as to minimize the total response time of all requests while ensuring the scheduling effect.

The invention provides a ZNS SSD-oriented multi-chip cooperative scheduling method, which comprises the following steps:

s1, initializing ZNS SSD equipment, wherein the ZNS SSD equipment comprises a partition conversion layer, a partition mapping module, an SSD controller, a transaction scheduling module and a flash memory module; the flash memory module comprises a plurality of chips, and each chip is correspondingly provided with a chip queue;

s2, designing a first multi-chip cooperation method and a second multi-chip cooperation method with the aim of minimizing the total response time of all requests;

s3, after the ZNS SSD device receives the request, converting the request through a partition conversion layer, and splitting the converted request into a plurality of transactions according to a partition mapping module by an SSD controller, wherein each transaction corresponds to one chip;

s4, if the request is selected by a scheduling algorithm, the transaction scheduling module performs position scheduling on all transactions in the request according to the scheduling algorithm and a first multi-chip cooperation method;

s5, if the request is not selected by the scheduling algorithm, the transaction scheduling module performs position scheduling on all transactions in the request according to a second multi-chip cooperation method;

s6, the chip in the flash memory module continuously takes out the transaction from the head of the own chip queue to respond, and after all the transactions split by one request are responded, the request response is completed.

Further, in step S4, when the first multi-chip cooperation method is used to perform the position scheduling on the request selected by the scheduling algorithm, the specific process includes:

s11, when all the transactions of the request selected by the scheduling algorithm are stored in the corresponding chip queues, calculating the nearest head position of each transaction in the chip queue according to the scheduling algorithm;

s12, selecting the maximum value from all the most recent head positions as the maximum scheduling position of all the transactions in the request;

s13, the tail of each chip queue is an initial position, and all transactions start from the initial positions in the corresponding chip queues and move towards the head direction of the chip queues;

s14, calculating the total response time benefit of the movement every time a position is moved until the maximum scheduling position is moved;

s15, screening out the maximum value of the total response time gain, taking the position corresponding to the maximum value as a final dispatching position, and inserting all the transactions in the request into the final dispatching position.

Further, assuming that the response time of each chip to respond to each transaction is t, the transaction of the last response in a request is called the last transaction, and the transaction moving to the tail of the chip queue due to the insertion of the scheduled transaction is called the enqueued transaction; the calculation process of the total response time benefit of each movement in step S14 includes:

before moving a position from the position A to the position B, acquiring the total number M of the transactions currently at the position A in the request selected by the scheduling algorithm;

after the M transactions are moved to the position B, the response time of the request selected by the scheduling algorithm is reduced by t; simultaneously resulting in the generation of a plurality of enqueued transactions in which the number n of transactions belonging to the last transaction is deduplicated _m The response time gain of the movement from the position A to the position B is obtained to be T _m ＝(1-n _m )×t；

Assuming that the initial position is 1 and the final scheduling position is k, the total response time gain of the position B is:

further, the request not selected by the scheduling algorithm adopts a second multi-chip cooperation method to perform position scheduling, and specifically includes:

s21, traversing the depth of each corresponding chip queue of all the transactions in the request when storing all the transactions in the request which are not selected by the scheduling algorithm into each corresponding chip queue;

s22, selecting a position corresponding to the minimum depth as a target position of all transactions in the request;

s23, inserting the transaction in the chip queue corresponding to the minimum depth directly to the tail of the chip queue;

s24, calculating the maximum profit position of the rest transactions in the request in the chip queue, and carrying out position scheduling.

Further, in step S24, the process of calculating the maximum profit position of the rest of the transactions includes:

s241, determining the tail of a chip queue where each rest transaction is located, and moving from the tail to the direction of the target position;

s242, calculating the total response time benefit of the movement every time the position is moved; ending the movement when the total response time gain is less than or equal to 0;

s243, screening out the maximum value of the total response time gain, and inserting all other transactions into the positions corresponding to the maximum value of the total response time gain.

Further, assuming that the response time of each chip to respond to each transaction is t, the last responding transaction in one request is called the last transaction, and the transaction moving to the tail of the chip queue due to the insertion of the scheduled transaction is called the enqueued transaction; in step S242, the calculation process of the total response time gain for each movement includes:

before moving a position from a position A to a position B, acquiring the total number N of the rest transactions currently at the position A;

after the N rest transactions are moved to the position B, the response time of the request to which the rest transactions belong is reduced by t; simultaneously resulting in the generation of a plurality of enqueued transactions in which the number n of transactions belonging to the last transaction is deduplicated _i The response time gain of the movement from the position A to the position B is obtained to be T _i ＝(1-n _i )×t；

the invention has the beneficial effects that:

the invention provides a multi-chip collaborative scheduling method for ZNS SSD, which can be used together with the existing scheduling algorithm, and for the transactions which need to be scheduled by the existing scheduling algorithm, the total response time of the request is prevented from being increased due to the fact that only the transactions in a single chip queue are scheduled by comprehensively scheduling other transactions which belong to the same request with the transactions; for those transactions that do not need to be scheduled, the transaction condition of the chip queue is mapped to all transactions of the same request to be inserted into the most appropriate position in the chip queue to minimize the total response time of the request. The method of the invention further reduces the total response time of all requests on the basis of ensuring the scheduling effect of the existing scheduling algorithm.

Drawings

FIG. 1 is a schematic diagram of the internal structure of a ZNS SSD device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a multi-chip co-scheduling request to be scheduled according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a multi-chip co-scheduling request that does not need to be scheduled according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention provides a ZNS SSD-oriented multi-chip cooperative scheduling method, which is shown in figure 1 and comprises the following steps:

In general, the transaction scheduling module acts on transactions, and the present invention is used for multi-chip co-scheduling all transactions of the same request, so that whenever one transaction in the request is selected, it is equivalent to all transactions of the request, i.e. the request.

In one embodiment, the internal structure of the ZNS SSD device of the present invention is shown in fig. 2, where the ZNS SSD device includes an SSD controller, a partition conversion layer, a partition mapping module, a transaction scheduling module, and a flash memory module (flash memory medium), the flash memory module includes a plurality of chips, and each chip corresponds to a chip queue; the partition mapping module comprises all partitions split by the ZNS interface and the mapping relation between the partitions and the physical media. When the ZNS SSD device receives a host request from the SQ, it first converts the host request to a specific operation (read, write or erase operation) for a partition through the partition conversion layer; the SSD controller splits the converted request into a plurality of transactions according to the mapping relation of the partition in the partition mapping module, and each transaction is stored in a chip queue of a corresponding chip and is processed through the corresponding chip, as shown in FIG. 5; the plurality of transactions can be processed in parallel by different chips; the chip in the flash memory module always takes out the transaction from the head of the own chip queue to respond, when all the transactions of one request are responded, the request is completed after being responded, and finally the request of completion of the response is submitted to the CQ.

Specifically, the chip needs a certain time to respond to the transaction, and the transaction which is not responded to is temporarily stored in the chip queue of the corresponding chip, and then waits to be responded to. For transactions waiting for response in the chip queue, the transaction scheduling module may schedule certain transactions forward or backward according to rules agreed in advance, so as to achieve the corresponding purposes, such as increasing fairness, prioritizing read requests, and the like.

The transaction conditions in each chip queue are not exactly the same, and the scheduling algorithm of the transaction in a single chip is considered, so that the scheduling conditions of other transactions belonging to the same request can not be perceived, which may cause the total response time of the request and other requests to be increased. As shown in fig. 3 (a), the transaction TR4 in the chip queue 1 and the transaction TR4 in the chip queue 2 belong to the request 4, but only the scheduling situation in the chip queue 2 is considered in scheduling, and the transaction situation in the chip queue 1 is ignored, so that the total response time of all the requests is increased by 600us after scheduling. A request is completed when the last transaction response in all transactions it split is completed; the response time of a request is calculated until its last transaction is completed by the response. In fig. 3 (a), even though TR4 in chip queue 2 is scheduled to the front position, TR4 in chip queue 1 is not moved, and is positioned further back than TR4 in chip queue 2, closer to the tail of the chip queue, so the response time of request 4 after scheduling is the same as before scheduling; also in chip queue 2, since TR4 is scheduled to the front, TR1, TR2, TR3 are shifted back by one position, so the response times of requests 1, 2, 3 are all increased by 200, thus increasing the total response time of all requests by 600us.

In one embodiment, a first multi-chip cooperation method is provided, which comprehensively considers all transactions in a plurality of chip queues in a request during scheduling, and specifically includes:

s11, splitting a request selected by a scheduling algorithm into a plurality of transactions, wherein each transaction corresponds to a chip; preparing to store all the transactions in the corresponding chip queues for scheduling;

s12, after all transactions of one request are responded, the request is responded and completed, so the response time of one request is dependent on the response time of the transaction (the last transaction) at the deepest queue position (the position closest to the tail of the chip queue) in all transactions; therefore, when the method is used for scheduling, firstly, the chip queues corresponding to all the transactions of the request selected by the scheduling algorithm are traversed, and the nearest head position of each transaction in the chip queue is calculated according to the scheduling algorithm; the most recent head position refers to the position closest to the head of the queue that a transaction can insert in its corresponding chip queue;

s13, selecting the maximum value from all the most recent head positions as the maximum scheduling position (pos-max) of all the transactions in the request; thus avoiding causing unnecessary increases in response time for other requests, which would not decrease, but may also cause increases in response time for other requests, even if transactions in other chip queues are scheduled closer to the head of the queue than pos-max;

specifically, the depth of all chip queues is the same, and the number of transactions that can be stored is the same, i.e. the number of positions is the same; the closer to the head of the chip queue, the smaller the depth value; conversely, the closer to the tail of the chip queue, the greater its depth value. The maximum value is selected from all the most recent head positions, and one position closest to the tail of the chip queue is selected, namely the position with the largest depth value is selected.

S14, taking the tail of the chip queue as an initial position, and moving all the transactions from the initial positions in the corresponding chip queues to the head direction of the chip queue;

specifically, the tail of the chip queue refers to the position after the last transaction in the chip queue before the latest transaction is stored in the chip queue, as shown in fig. 5, the request 4 is split into 4 transactions, which correspond to the chip 1, the chip 2, the chip 3 and the chip 4 respectively; when all the transactions of the request 4 are ready to be stored in the corresponding chip queues, the tail of the chip queue 1 refers to the later position of the stored transaction TR3, and the first TR4 takes the position as the initial position; the tail of chip queue 2 refers to the latter position of transaction TR1 in which it is deposited, and the tail of chip queue 3 refers to the latter position of transaction TR2 in which it is deposited. It follows that the initial positions of all transactions of the same request in the respective corresponding chip queues are not necessarily the same.

specifically, starting from the initial position closest to the tail of the queue in all the transactions of the request, moving one position by one position, not necessarily moving all the transactions of one request forward by one position at the same time, but when one or more transactions of the request need to be moved from the position A to the position B, finding that one or more transactions of the request are in the position A, and moving the transactions in the position A to the position B together; finally, all the transactions of the request almost reach the same position in the queue, so that the purpose of movement is to make the positions of all the transactions of the same request in the respective queue the same as much as possible; when all transactions of the request reach the maximum dispatch location, the move is ended.

Specifically, as shown in fig. 3 (b), pos-max indicated by an arrow is a maximum scheduling position of all transactions in the request 4, a tail of the chip queue is taken as an initial position, and the transaction TR4 of the chip queue 1 and the transaction TR4 of the chip queue 2 start from the initial positions in the corresponding chip queues and move towards the head direction of the chip queue; calculating the total response time benefit of the movement every time a position is moved until the maximum scheduling position is moved; the maximum value of the total response time benefit is screened out, the position (pos-max in fig. 3 (b)) corresponding to the maximum value of the total response time benefit is taken as the final scheduling position, and all the transactions in the request 4 are inserted into the final scheduling position.

For requests that do not require scheduling, all of their transactions are often inserted directly into the tail of the chip queue according to first-in-first-out (FIFO) principles. However, such transaction placement does not result in optimal overall request response time for chip queues that are not busy. As shown in fig. 4 (a), two transactions TR6 of a request 6 are placed directly to the tail of the queue in a default manner, however TR6 in the chip queue 2 may also be moved forward at this time to reduce the response time of the request 6 without affecting the response time of other requests.

In one embodiment, a second multi-chip collaboration method is provided that, for requests that do not require scheduling, still inserts all of their transactions from the multi-chip collaboration perspective into the most appropriate locations in the corresponding chip queues to minimize the total response time of all requests, in the following manner:

s21, splitting a request which is not selected by a scheduling algorithm into a plurality of transactions, wherein each transaction corresponds to a chip; when all the transactions are stored in the corresponding chip queues, traversing the depth of the chip queue corresponding to each transaction in the request, namely, the depth value of the tail position of the chip queue;

s24, calculating the maximum profit positions of all other transactions in the request in the corresponding chip queues, and performing position scheduling.

Specifically, in step S24, the process of calculating the maximum profit position of all the remaining transactions includes:

s241, determining the tail of a chip queue where each other transaction is located, and moving all the other transactions from the tail to the direction of the target position;

s242, calculating the total response time benefit of the movement every time the position is moved; when the total response time gain is less than or equal to 0, all other transactions end to move;

Specifically, as shown in fig. 4, traversing the depth of the chip queue corresponding to each of the two transactions of the request 6, namely obtaining the depth value of the tail position of the chip queue corresponding to each of the two transactions, wherein the depth value of the tail position of the chip queue 3 is the smallest, so that the tail position of the chip queue 3 is selected as the target position of the two transactions in the request 6, the transaction corresponding to the chip queue 3 is directly inserted into the tail of the chip queue 3, and the transaction in the chip queue 2 starts from the tail of the chip queue 2 and moves to the target position; each time a transaction in the chip queue 2 moves by one position, calculating the total response time benefit of the movement; when the total response time gain is less than or equal to 0, the rest transactions end to move; the maximum value of the total response time gain is screened out, and the transaction in the chip queue 2 is inserted into the position corresponding to the maximum value of the total response time gain, and the position corresponding to the maximum value of the total response time gain is the target position as can be seen from fig. 4 (b).

All transactions split for a request are response completed based on the response completion condition of the request, so the response time of a request is equal to the response time of the transaction it last responded to (the last transaction). If the last transaction of a request is preceded by a transaction of another request, this will result in an increase in the response time of the last transaction (because of the increase in latency), i.e. in the response time of the request to which the last transaction belongs. In one embodiment, the scheduled transaction (the scheduled transaction is the transaction that uses the first multi-chip cooperation method or the second multi-chip cooperation method to perform position scheduling) is called a target transaction, and the transaction that is forced to move to the tail of the queue due to the insertion of the target transaction is called a dequeued transaction; it is apparent that this scheduling will result in an increase in the response time of the request to which the enqueued transaction belongs when it is the last transaction to which the enqueued transaction belongs. Thus, the specific way to calculate the total response time benefit per move is:

s101, assuming t is the response time of one chip to respond to one transaction, and the response time of each chip to respond to each transaction is the same;

s102, reducing response time of a scheduled request by t when a target transaction moves to the head direction of a chip queue by one transaction;

specifically, there may be only one target transaction to move, or there may be multiple target transactions to move, each of which moves only when the position to be moved is the next position to the position in which it is located; regardless of how many target transactions move per move, the response time of the request to which the target transaction belongs is reduced by only t, and these target transactions that participate in the move process belong to one request.

S103, for the enqueued transaction, if the enqueued transaction is not the last transaction of the affiliated request, the response time of the affiliated request is not affected; if it is the last transaction of the request, the response time of the request to which it belongs is increased by t; further, when n non-duplicate enqueued transactions are the last transaction of the request to which they belong, then the total response time for all requests is increased by n×t;

s4, the response time benefit of the target transaction moving once is (1-n) x t; and for a certain location its total response time benefit time is the sum of the response time benefits of all the previous moved locations.

In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A ZNS SSD-oriented multi-chip cooperative scheduling method is characterized by comprising the following steps:

2. The method for collaborative scheduling of multiple chips for a ZNS SSD of claim 1, wherein in step S4, when the first multi-chip collaborative method is used to perform the position scheduling on the request selected by the scheduling algorithm, the specific process includes:

3. The ZNS SSD-oriented multi-chip co-scheduling method of claim 2, wherein assuming that the response time of each chip to each transaction is t, the last responding transaction in a request is called a last transaction, and the transaction moved to the tail of the chip queue due to the insertion of the scheduled transaction is called a dequeued transaction; the calculation process of the total response time benefit of each movement in step S14 includes:

4. the ZNS SSD-oriented multi-chip cooperative scheduling method of claim 1, wherein the request not selected by the scheduling algorithm is subjected to the position scheduling by using a second multi-chip cooperative method, and the method specifically includes:

5. The method for collaborative scheduling of multiple chips for a ZNS SSD according to claim 4, wherein the step of calculating the maximum profit position of the remaining transactions in step S24 comprises:

6. The ZNS SSD-oriented multi-chip cooperative scheduling method of claim 5, wherein assuming that a response time of each chip to each transaction is t, a last-responded transaction in one request is called a last transaction, and a transaction moved to a tail of a chip queue due to insertion of the scheduled transaction is called a dequeued transaction; in step S242, the calculation process of the total response time gain for each movement includes:

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