CN116210229A

CN116210229A - Exposure control circuit, related image sensor and electronic device

Info

Publication number: CN116210229A
Application number: CN202180005048.XA
Authority: CN
Inventors: 梁佑安; 黄猷淳
Original assignee: Dick Innovation Technology Co ltd
Current assignee: Huiding Technology Private Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2023-06-02
Also published as: WO2023050029A1

Abstract

The application discloses an exposure control circuit, a related image sensor and an electronic device. The exposure control circuit is used for controlling the exposure of the pixel array, and comprises: the first sub-exposure control circuit, the second sub-exposure control circuit, the third sub-exposure control circuit and the fourth sub-exposure control circuit which are arranged in 2 rows and 2 columns are correspondingly coupled with the first pixel group, the second pixel group, the third pixel group and the fourth pixel group of the pixel array. In the first exposure mode, the exposure control circuit controls the first part of pixels, the second part of pixels, the third part of pixels and the fourth part of pixels of the first pixel group to have a first exposure time length; in the second exposure mode, the exposure control circuit controls the fourth part of pixels of the first pixel group, the third part of pixels of the second pixel group, the second part of pixels of the third pixel group and the first part of pixels of the fourth pixel group to have a ninth exposure time length.

Description

Exposure control circuit, related image sensor and electronic device

Technical Field

The present disclosure relates to electronic circuits, and particularly to an exposure control circuit, an image sensor and an electronic device.

Background

With the progress of technology, CMOS image sensors are required to have a high dynamic range in addition to a large-scale pixel array. In general, when an image is captured, the exposure time of each pixel in the pixel array is the same, so that in order to achieve a high dynamic range, it is necessary to process the captured images to achieve the high dynamic range effect that some portions of the same image have short exposure time and some portions have long exposure time. Such a procedure consumes much time, and thus how to solve the above-mentioned problems has become one of the problems to be solved in the art.

Disclosure of Invention

An objective of the present application is to disclose an exposure control circuit, a related image sensor and an electronic device, so as to solve the above-mentioned problems.

An embodiment of the present application discloses an exposure control circuit for controlling exposure of a pixel array, the pixel array at least includes a first pixel group, a second pixel group, a third pixel group and a fourth pixel group arranged in 2 rows and 2 columns, wherein the first pixel group, the second pixel group, the third pixel group and the fourth pixel group each include a first portion pixel, a second portion pixel, a third portion pixel and a fourth portion pixel, the exposure control circuit includes: a first sub-exposure control circuit, a second sub-exposure control circuit, a third sub-exposure control circuit and a fourth sub-exposure control circuit arranged in 2 rows and 2 columns are correspondingly coupled to the first pixel group, the second pixel group, the third pixel group and the fourth pixel group; wherein: in the first exposure mode, the exposure control circuit controls: the first part of pixels, the second part of pixels, the third part of pixels and the fourth part of pixels of the first pixel group all have a first exposure time length; the first, second, third and fourth partial pixels of the second pixel group each have a second exposure time length; the first, second, third and fourth partial pixels of the third pixel group each have a third length of exposure time; and the first, second, third, and fourth partial pixels of the fourth pixel group each have a fourth exposure time length; wherein the first exposure time length, the second exposure time length, the third exposure time length, and the fourth exposure time length are not all the same as each other; and in a second exposure mode, the exposure control circuit controls: the first part of pixels of the first pixel group have a fifth exposure time length; the second portion of pixels of the first pixel group and the first portion of pixels of the second pixel group all have a sixth exposure time length; the second partial pixels of the second pixel group all have a seventh exposure time length; the third partial pixels of the first pixel group and the first partial pixels of the third pixel group all have an eighth exposure time length; the fourth partial pixels of the first pixel group, the third partial pixels of the second pixel group, the second partial pixels of the third pixel group, and the first partial pixels of the fourth pixel group all have a ninth exposure time length; the fourth partial pixels of the second pixel group and the second partial pixels of the fourth pixel group all have a tenth exposure time length; the third partial pixels of the third pixel group all have an eleventh exposure time length; the fourth partial pixels of the third pixel group, the third partial pixels of the fourth pixel group, and the fourth partial pixels of the third pixel group all have a twelfth exposure time length; and the third portion of pixels of the fourth pixel group all have a thirteenth exposure time length; wherein the fifth exposure time length, the sixth exposure time length, the seventh exposure time length, the eighth exposure time length, the ninth exposure time length, the tenth exposure time length, the eleventh exposure time length, the twelfth exposure time length, and the thirteenth exposure time length are not all the same as each other.

An embodiment of the present application discloses an exposure control circuit for controlling exposure of a pixel array, the pixel array at least includes a first pixel group, a second pixel group, a third pixel group and a fourth pixel group arranged in 2 rows and 2 columns, wherein the first pixel group, the second pixel group, the third pixel group and the fourth pixel group each include a first portion pixel, a second portion pixel, a third portion pixel and a fourth portion pixel, the exposure control circuit includes: a first sub-exposure control circuit, a second sub-exposure control circuit, a third sub-exposure control circuit and a fourth sub-exposure control circuit arranged in 2 rows and 2 columns are correspondingly coupled to the first pixel group, the second pixel group, the third pixel group and the fourth pixel group; wherein the first sub-exposure control circuit, the second sub-exposure control circuit, the third sub-exposure control circuit, and the fourth sub-exposure control circuit each include: a control unit for generating an exposure control signal; and a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer, each having a first input, a second input, and an output; wherein: the output terminal of the first multiplexer of the first sub-exposure control circuit is coupled to the first partial pixel of the first pixel group to control an exposure time length, the output terminal of the second multiplexer of the first sub-exposure control circuit is coupled to the second partial pixel of the first pixel group to control an exposure time length, the output terminal of the third multiplexer of the first sub-exposure control circuit is coupled to the third partial pixel of the first pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the first sub-exposure control circuit is coupled to the fourth partial pixel of the first pixel group to control an exposure time length; the output terminal of the first multiplexer of the second sub-exposure control circuit is coupled to the first partial pixel of the second pixel group to control an exposure time length, the output terminal of the second multiplexer of the second sub-exposure control circuit is coupled to the second partial pixel of the second pixel group to control an exposure time length, the output terminal of the third multiplexer of the second sub-exposure control circuit is coupled to the third partial pixel of the second pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the second sub-exposure control circuit is coupled to the fourth partial pixel of the second pixel group to control an exposure time length; the output terminal of the first multiplexer of the third sub-exposure control circuit is coupled to the first partial pixel of the third pixel group to control an exposure time length, the output terminal of the second multiplexer of the third sub-exposure control circuit is coupled to the second partial pixel of the third pixel group to control an exposure time length, the output terminal of the third multiplexer of the third sub-exposure control circuit is coupled to the third partial pixel of the third pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the third sub-exposure control circuit is coupled to the fourth partial pixel of the third pixel group to control an exposure time length; the output terminal of the first multiplexer of the fourth sub-exposure control circuit is coupled to the first partial pixel of the fourth pixel group to control an exposure time length, the output terminal of the second multiplexer of the fourth sub-exposure control circuit is coupled to the second partial pixel of the fourth pixel group to control an exposure time length, the output terminal of the third multiplexer of the fourth sub-exposure control circuit is coupled to the third partial pixel of the fourth pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the fourth sub-exposure control circuit is coupled to the fourth partial pixel of the fourth pixel group to control an exposure time length; the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the first sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the first sub-exposure control circuit; the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the second sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the second sub-exposure control circuit; the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the third sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the third sub-exposure control circuit; the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the fourth sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the fourth sub-exposure control circuit; the second input terminal of the fourth multiplexer of the first sub-exposure control circuit, the second input terminal of the third multiplexer of the second sub-exposure control circuit, the second input terminal of the second multiplexer of the third sub-exposure control circuit, and the second input terminal of the first multiplexer of the fourth sub-exposure control circuit are all configured to receive the exposure control signal generated by the control unit of the first sub-exposure control circuit.

An embodiment of the present application discloses an image sensor, including the above-mentioned exposure control circuit; and the pixel array.

An embodiment of the application discloses an electronic device, which comprises the image sensor.

Compared with the prior art, the exposure control circuit, the related image sensor and the electronic device can improve the performance of a high dynamic range.

Drawings

Fig. 1 is a schematic diagram of an embodiment of an exposure control circuit controlling a pixel array in a first exposure mode.

Fig. 2 is an example of an exposure control circuit of the present application controlling exposure time of each pixel group of the pixel array in the first exposure mode.

Fig. 3 is a schematic diagram of a first embodiment of an exposure control circuit for controlling a pixel array in a second exposure mode.

Fig. 4 is an example of the exposure control circuit of the present application controlling the exposure time of each pixel group of the first embodiment of the pixel array in the second exposure mode.

Fig. 5 is a schematic diagram of the exposure time after integrating fig. 2 and fig. 4.

Fig. 6 is a schematic diagram of a second embodiment of the exposure control circuit controlling the pixel array in the second exposure mode.

Fig. 7 is an example of the exposure control circuit of the present application controlling the exposure time of each pixel group of the second embodiment of the pixel array in the second exposure mode.

Fig. 8 is a schematic diagram of the exposure time after integrating fig. 2 and fig. 7.

Fig. 9 is a schematic diagram of an embodiment of an operation of the exposure control circuit of the present application in a first exposure mode.

Fig. 10 is a schematic diagram of an embodiment of the operation of the exposure control circuit of the present application in the second exposure mode.

Detailed Description

The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of those ordinarily skilled in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the word "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.

Fig. 1 is a schematic diagram of an embodiment of an exposure control circuit controlling a pixel array in a first exposure mode. The pixel array 100 of fig. 1 includes a plurality of pixels arranged in m rows and n columns, where m and n are positive integers. The pixel array 100 of fig. 1 is divided into a plurality of groups of pixel groups by thick lines, and for convenience of illustration, fig. 1 only shows the pixel groups G11, G12, G21 and G22 arranged in 2 rows by 2 columns. In the present embodiment, the pixel group G11, the pixel group G12, the pixel group G21 and the pixel group G22 have the same size, and each includes a plurality of pixels arranged in p×q, where p and q are positive integers. In the present embodiment, the pixel group G11, the pixel group G12, the pixel group G21, and the pixel group G22 each include pixels P11, P12, P13, P14, P21, P22, P23, P24, P31, P32, P33, P34, P41, P42, P43, and P44 arranged in 4*4.

In the first exposure mode, the exposure control circuit of the present application individually controls each pixel group in the grouping manner shown in fig. 1, for example, when sensing the image I1, the exposure control circuit of the present application controls the pixel group G11, the pixel group G12, the pixel group G21 and the pixel group G22 to have the exposure time length T1, the exposure time length T2, the exposure time length T3 and the exposure time length T4, respectively. That is, in sensing the image I1, all pixels in the pixel group G11 are exposed for the exposure time length T1 to complete sensing; all pixels in the pixel group G12 are exposed for an exposure time length T2 to complete sensing; all pixels in the pixel group G21 are exposed for an exposure time length T3 to complete sensing; all pixels in the group of pixels G22 are exposed for an exposure time period T4 to complete the sensing. And the exposure time length T1, the exposure time length T2, the exposure time length T3, and the exposure time length T4 may be different from each other. For example, as shown in fig. 2, the exposure time length T1 is 1 time length unit; the exposure time length T2 is 3 time length units; the exposure time length T3 is a time length unit of 3 times; the exposure time length T4 is 6 time length units.

The advantage of using the first exposure mode of fig. 1 is that the exposure time of each pixel group in the pixel array can be different in the same image I1, so that only one image I1 needs to be taken, and the high dynamic range effect that some parts of the same image have short exposure time and some parts have long exposure time can be achieved, as shown in fig. 2. Thus, if each pixel group includes only one pixel, i.e., p and q are 1, and each pixel group includes only a plurality of pixels arranged in 1*1, the exposure time of each pixel can be controlled independently, i.e., the exposure control with the highest resolution can be achieved. However, in order to save the hardware cost, a compromise scheme may be adopted to make p and q larger than 1, for example, each pixel group in fig. 1 is 4*4, or may be 8×8, 8×16 or 16×16. However, the resolution of the exposure control is reduced, and there is a serious discontinuity between the different exposure areas, which results in poor linearity. In view of this, the present application proposes a way that can further improve the resolution of exposure control without excessively increasing the complexity.

Fig. 3 is a schematic diagram of a first embodiment of an exposure control circuit for controlling a pixel array in a second exposure mode. It should be noted that G11, G12, G21, and G22 indicated in fig. 3 still refer to the pixel group G11, the pixel group G12, the pixel group G21, and the pixel group G22 divided in fig. 1. The difference between fig. 3 and fig. 1 is that the pixel groups of fig. 1 are equally divided into four parts, specifically, according to fig. 3, the pixel groups in the first exposure mode are divided into first partial pixels (pixels P11, P12, P21, and P22), second partial pixels (pixels P13, P14, P23, and P24), third partial pixels (pixels P31, P32, P41, and P42), and fourth partial pixels (pixels P33, P34, P43, and P44) having the same size in the second exposure mode.

The pixel array 100 is divided into a plurality of pixel groups by the thick lines indicated in fig. 3 in the second exposure mode, wherein each pixel group still includes a plurality of pixels arranged in p×q. For example, as can be seen from fig. 3, the fourth partial pixels of the pixel group G11, the third partial pixels of the pixel group G12, the second partial pixels of the pixel group G21, and the first partial pixels of the pixel group G22 are combined into the same pixel group in the second exposure mode. For another example, the second partial pixels of the pixel group G11, the first partial pixels of the pixel group G12, the fourth partial pixels of the pixel group above the pixel group G11 (not shown in the figure), and the third partial pixels of the pixel group above the pixel group G12 (not shown in the figure) are combined into the same pixel group in the second exposure mode. The remaining pixel groups can be analogized and are not described in detail herein.

Therefore, in fig. 3, in the second exposure mode, the first portion of pixels of the pixel group G11 have an exposure time length T5; the second partial pixels of the pixel group G11 and the first partial pixels of the second pixel group G12 all have an exposure time length T6; the second partial pixels of the pixel group G12 have an exposure time length T7; the third partial pixel of the G11 pixel group and the first partial pixel of the pixel group G21 all have an exposure time length T8; the fourth partial pixel of the pixel group G11, the third partial pixel of the pixel group G12, the second partial pixel of the pixel group G21, and the first partial pixel of the pixel group G22 all have an exposure time length T9; the fourth partial pixel of the pixel group G12 and the second partial pixel of the pixel group G22 have an exposure time length T10; the third partial pixels of the pixel group G21 all have an exposure time length T11; the fourth portion of pixels of the pixel group G21 and the third portion of pixels of the pixel group G22 all have an exposure time length T12; and the third portion of pixels of the pixel group G22 have an exposure time length T13. And the exposure time length T5, the exposure time length T6, the exposure time length T7, the exposure time length T8, the exposure time length T9, the exposure time length T10, the exposure time length T11, the exposure time length T12, and the exposure time length T13 may be different from each other.

For example, as shown in fig. 4, the exposure time length T5 is 1 time length unit; the exposure time length T6 is a time length unit of 2 times; the exposure time length T7 is 3 time length units; the exposure time length T8 is a time length unit of 2 times; the exposure time length T9 is 4 time length units; the exposure time length T10 is a time length unit of 5 times; the exposure time length T11 is a time length unit of 3 times; the exposure time length T12 is 4 time length units; the exposure time length T13 is 6 time length units.

Compared with the image I1 obtained in the first exposure mode in fig. 1, the image I2 obtained in the second exposure mode in fig. 3 does not have higher resolution of exposure control, but the grouping manner of the pixel groups in the images I1 and I2 is different, so that when the results obtained in the images I1 and I2 are integrated together, higher resolution can be obtained. For example, as can be seen in fig. 5, which is a direct combination of fig. 2 and 4, the resolution of the exposure control is four times higher than that of either of fig. 2 and 4.

Fig. 6 is a schematic diagram of a second embodiment of the exposure control circuit controlling the pixel array in the second exposure mode. The difference from fig. 3 is that the pixel groups of fig. 1 are unevenly broken up into four parts in fig. 6, specifically, according to fig. 6, the pixel groups in the first exposure mode are broken up into first partial pixels (pixels P11, P12, P13, P21, P22, P23, P31, P32, and P33), second partial pixels (pixels P14, P24, and P34), third partial pixels (pixels P41, P42, and P43), and fourth partial pixels (pixel P44) having different sizes in the second exposure mode.

The pixel array 100 is divided into a plurality of pixel groups by the thick lines indicated in fig. 6 in the second exposure mode, wherein each pixel group still includes a plurality of pixels arranged in p×q. For example, as can be seen from fig. 6, the fourth partial pixels of the pixel group G11, the third partial pixels of the pixel group G12, the second partial pixels of the pixel group G21, and the first partial pixels of the pixel group G22 are combined into the same pixel group in the second exposure mode. For another example, the second partial pixels of the pixel group G11, the first partial pixels of the pixel group G12, the fourth partial pixels of the pixel group above the pixel group G11 (not shown in the figure), and the third partial pixels of the pixel group above the pixel group G12 (not shown in the figure) are combined into the same pixel group in the second exposure mode. The remaining pixel groups can be analogized and are not described in detail herein.

Thus, in the second exposure mode, as shown in fig. 6, the first partial pixels of the pixel group G11 have an exposure time length T14; the second partial pixels of the pixel group G11 and the first partial pixels of the second pixel group G12 all have an exposure time length T15; the second partial pixels of the pixel group G12 have an exposure time length T16; the third partial pixel of the G11 pixel group and the first partial pixel of the pixel group G21 all have an exposure time length T17; the fourth partial pixel of the pixel group G11, the third partial pixel of the pixel group G12, the second partial pixel of the pixel group G21, and the first partial pixel of the pixel group G22 all have an exposure time length T18; the fourth partial pixel of the pixel group G12 and the second partial pixel of the pixel group G22 have an exposure time length T19; the third portion of pixels of the pixel group G21 have an exposure time length T20; the fourth portion of pixels of the pixel group G21 and the third portion of pixels of the pixel group G22 all have an exposure time length T21; and the third portion of pixels of the pixel group G22 have an exposure time length T22. And the exposure time length T14, the exposure time length T15, the exposure time length T16, the exposure time length T17, the exposure time length T18, the exposure time length T19, the exposure time length T20, the exposure time length T21, and the exposure time length T22 may be different from each other.

For example, as shown in fig. 7, the exposure time length T14 is 1 time length unit; the exposure time length T15 is 3 time length units; the exposure time length T16 is 4 time length units; the exposure time length T17 is 3 time length units; the exposure time length T18 is 4 time length units; the exposure time length T19 is 6 time length units; the exposure time length T20 is 4 time length units; the exposure time length T21 is a time length unit of 5 times; the exposure time length T22 is 6 time length units.

Compared with the image I1 obtained in the first exposure mode in fig. 1, the image I3 obtained in the second exposure mode in fig. 6 does not have higher resolution of exposure control, but the grouping manner of the pixel groups in the image I1 and the image I3 is different, so that when the results obtained in the image I1 and the image I3 are integrated together, higher resolution can be obtained. For example, as can be seen in fig. 8, which is a direct combination of fig. 2 and 7, the resolution of the exposure control is on average four times higher than that of either of fig. 2 and 7, and the effect is not much the same as that of fig. 5. The designer may choose the desired configuration according to different needs.

In summary, by alternately switching between the first exposure mode and the second exposure mode and combining the results obtained in the first exposure mode and the second exposure mode, the resolution of exposure control can be substantially improved. And the setting of the dynamic range used in the first exposure mode and the second exposure mode may be different. For example, using a high dynamic range setting to perform exposure in the first exposure mode and a low dynamic range setting to perform exposure in the second exposure mode.

Fig. 9 is a schematic diagram of an embodiment of the operation of the exposure control circuit of the present application in the first exposure mode. The exposure control circuit 400 includes a plurality of sub-exposure control circuits correspondingly coupled to a plurality of pixel groups of the pixel array 100 of fig. 1. For convenience of description, fig. 9 shows only the sub-exposure control circuit C11, the sub-exposure control circuit C12, the sub-exposure control circuit C21, and the sub-exposure control circuit C22 arranged in 2 rows by 2 columns. In the present embodiment, the sub-exposure control circuit C11, the sub-exposure control circuit C12, the sub-exposure control circuit C21, and the sub-exposure control circuit C22 have the same size, and each includes a control unit and a plurality of multiplexers. In this embodiment, the first input (input labeled 0) of each multiplexer is selectively connected to the output by the control signal S to enter the first exposure mode.

Specifically, the sub-exposure control circuit C11 includes a control unit 10 for generating an exposure control signal SC10 to first inputs (input labeled 0) of the

multiplexers

15, 16, 17 and 18. The outputs of the

multiplexers

15, 16, 17 and 18 are coupled to the first, second, third and fourth partial pixels of the pixel group G11 through the

drivers

11, 12, 13 and 14, respectively, to control the exposure time length. The bold line of fig. 9 represents the manner in which the exposure control signal SC10 is output, and it is clear from fig. 9 that in the first exposure mode, the first partial pixel, the second partial pixel, the third partial pixel, and the fourth partial pixel of the pixel group G11 are controlled by the same exposure control signal SC 10.

The sub-exposure control circuit C12 includes a control unit 20 for generating an exposure control signal SC20 to a first input (input labeled 0) of a multiplexer 25, a multiplexer 26, a multiplexer 27, and a multiplexer 28. The outputs of the

multiplexers

25, 26, 27 and 28 are coupled to the first, second, third and fourth partial pixels of the pixel group G12 through the

drivers

21, 22, 23 and 24, respectively, to control the exposure time length. As is clear from fig. 9, in the first exposure mode, the first, second, third and fourth partial pixels of the pixel group G12 are controlled by the same exposure control signal SC20, as is apparent from the bold line of fig. 9 representing the manner in which the exposure control signal SC20 is output.

The sub-exposure control circuit C21 includes a control unit 30 for generating an exposure control signal SC10 to a first input (input labeled 0) of the multiplexer 35, the multiplexer 36, the multiplexer 37, and the multiplexer 38. The outputs of the

multiplexers

35, 36, 37 and 38 are coupled to the first, second, third and fourth partial pixels of the pixel group G21 through the

drivers

31, 32, 33 and 34, respectively, to control the exposure time length. As is clear from fig. 9, in the first exposure mode, the first, second, third and fourth partial pixels of the pixel group G21 are controlled by the same exposure control signal SC30, as is apparent from the bold line of fig. 9 representing the manner in which the exposure control signal SC30 is output.

The sub-exposure control circuit C22 includes a control unit 40 for generating an exposure control signal SC10 to a first input terminal (input terminal labeled 0) of the multiplexer 45, the multiplexer 46, the multiplexer 47, and the multiplexer 48. The outputs of the

multiplexers

45, 46, 47 and 48 are coupled to the first, second, third and fourth partial pixels of the pixel group G22 through the

drivers

41, 42, 43 and 44, respectively, to control the exposure time length. As is clear from fig. 9, in the first exposure mode, the first, second, third and fourth partial pixels of the pixel group G22 are controlled by the same exposure control signal SC40, as is apparent from the bold line of fig. 9 representing the manner in which the exposure control signal SC40 is output.

Fig. 10 is a schematic diagram of an embodiment of the operation of the exposure control circuit of the present application in the second exposure mode. In this embodiment, the second input (input labeled 1) of each multiplexer is selectively connected to the output by the control signal S to enter the second exposure mode.

As shown in fig. 10, the exposure control signal SC10 generated by the control unit 10 of the sub-exposure control circuit C11 is also supplied to the second input terminal (input terminal labeled 1) of the multiplexer 18 of the sub-exposure control circuit C11, the second input terminal (input terminal labeled 1) of the multiplexer 27 of the sub-exposure control circuit C12, the second input terminal (input terminal labeled 1) of the multiplexer 32 of the sub-exposure control circuit C21, and the second input terminal (input terminal labeled 1) of the multiplexer 41 of the sub-exposure control circuit C22. The exposure control signal SC20 generated by the control unit 20 of the sub-exposure control circuit C12 is also supplied to the second input terminal (input terminal labeled 1) of the multiplexer 28 of the sub-exposure control circuit C12, the second input terminal (input terminal labeled 1) of the multiplexer 42 of the sub-exposure control circuit C22, and the second input terminals (not shown) of the multiplexers of the other two adjacent sub-exposure control circuits. The connection manner of the second input terminals of the remaining multiplexers may be referred to fig. 10, and will not be described herein.

The bold line of fig. 10 represents the manner in which the respective exposure control signals are output, and it is clear from fig. 10 that in the first exposure mode, the fourth partial pixels of the pixel group G11, the third partial pixels of the pixel group G12, the second partial pixels of the pixel group G21, and the first partial pixels of the pixel group G22 are controlled by the same exposure control signal SC 10; the fourth partial pixels of the pixel group G12 and the second partial pixels of the pixel group G22 are controlled by the same exposure control signal SC 20; the fourth partial pixels of the pixel group G21 and the third partial pixels of the pixel group G22 are controlled by the same exposure control signal SC 30; the fourth partial pixels of the pixel group G22 are controlled by the same exposure control signal SC 40.

The exposure control circuit can obtain images with high dynamic range more quickly, and the resolution of exposure control can be improved to 4 times by utilizing almost hardware cost.

The application also proposes a pixel array 100 including an image sensor including an exposure control circuit 400. In some embodiments, the exposure control circuit 400 and the pixel array 100 may be provided in a 2.5D IC or a 3D IC. For example, the exposure control circuit 400 is disposed on a first substrate, the pixel array 100 is disposed on a second substrate different from the first substrate, and the first substrate and the second substrate are stacked by hybrid bonding, so that the exposure control circuit 400 is coupled to the pixel array 100.

The application also proposes an electronic device comprising the image sensor. In particular, the electronic apparatus includes, but is not limited to, mobile communication devices, ultra mobile personal computer devices, portable entertainment devices, and other electronic devices having data interaction capabilities. The mobile communication device is characterized by having a mobile communication function and mainly aims at providing voice and data communication. Such terminals include: smart phones (e.g., iPhone), multimedia phones, functional phones, and low-end phones, etc. Ultra mobile personal computer devices belong to the category of personal computers, have computing and processing functions, and generally have mobile internet access characteristics. Such terminals include: PDA, MID, and UMPC devices, etc., such as iPad. The portable entertainment device may display and play multimedia content. The device comprises: audio, video players (e.g., iPod), palm game consoles, electronic books, and smart toys and portable car navigation devices.

The foregoing description briefly sets forth features of certain embodiments of the present disclosure to provide a more thorough understanding of the various aspects of the present disclosure to those skilled in the art to which the present disclosure pertains. It will be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

An exposure control circuit for controlling exposure of a pixel array, the pixel array including at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group arranged in 2 rows and 2 columns, wherein each of the first pixel group, the second pixel group, the third pixel group, and the fourth pixel group includes a first portion pixel, a second portion pixel, a third portion pixel, and a fourth portion pixel, the exposure control circuit comprising:

a first sub-exposure control circuit, a second sub-exposure control circuit, a third sub-exposure control circuit and a fourth sub-exposure control circuit arranged in 2 rows and 2 columns are correspondingly coupled to the first pixel group, the second pixel group, the third pixel group and the fourth pixel group;

wherein:

in the first exposure mode, the exposure control circuit controls:

the first portion of pixels, the second portion of pixels, the third portion of pixels, and the fourth portion of pixels of the first pixel group all have a first exposure time length;

the first, second, third and fourth partial pixels of the second pixel group each have a second exposure time length;

The first, second, third and fourth partial pixels of the third pixel group each have a third length of exposure time; and

the first, second, third and fourth partial pixels of the fourth pixel group each have a fourth exposure time length;

wherein the first exposure time length, the second exposure time length, the third exposure time length, and the fourth exposure time length are not all the same as each other; and

in the second exposure mode, the exposure control circuit controls:

the first part of pixels of the first pixel group have a fifth exposure time length;

the second portion of pixels of the first pixel group and the first portion of pixels of the second pixel group all have a sixth exposure time length;

the second partial pixels of the second pixel group all have a seventh exposure time length;

the third partial pixels of the first pixel group and the first partial pixels of the third pixel group all have an eighth exposure time length;

the fourth partial pixels of the first pixel group, the third partial pixels of the second pixel group, the second partial pixels of the third pixel group, and the first partial pixels of the fourth pixel group all have a ninth exposure time length;

The fourth partial pixels of the second pixel group and the second partial pixels of the fourth pixel group all have a tenth exposure time length;

the third partial pixels of the third pixel group all have an eleventh exposure time length;

the fourth partial pixels of the third pixel group, the third partial pixels of the fourth pixel group, and the fourth partial pixels of the third pixel group all have a twelfth exposure time length; and

the third partial pixels of the fourth pixel group all have a thirteenth exposure time length;

wherein the fifth exposure time length, the sixth exposure time length, the seventh exposure time length, the eighth exposure time length, the ninth exposure time length, the tenth exposure time length, the eleventh exposure time length, the twelfth exposure time length, and the thirteenth exposure time length are not all the same as each other.
The exposure control circuit according to claim 1, wherein:

the first partial pixels of the first pixel group, the first partial pixels of the second pixel group, the first partial pixels of the third pixel group, and the first partial pixels of the fourth pixel group each include a×b pixels;

The second partial pixels of the first pixel group, the second partial pixels of the second pixel group, the second partial pixels of the third pixel group, and the second partial pixels of the fourth pixel group each include c×d pixels;

the third partial pixels of the first pixel group, the third partial pixels of the second pixel group, the third partial pixels of the third pixel group, and the third partial pixels of the fourth pixel group each include e×f pixels; and

the fourth partial pixels of the first pixel group, the fourth partial pixels of the second pixel group, the fourth partial pixels of the third pixel group, and the fourth partial pixels of the fourth pixel group each include g×h pixels;

wherein a, b, c, d, e, f, g and h are positive integers.
The exposure control circuit of claim 2, wherein a, b, c, d, e, f, g and h are both the same.
The exposure control circuit according to claim 2, wherein a, b, c and f are the same, d, e, g and h are the same, and a, b, c and f are different from d, e, g and h.
The exposure control circuit according to any one of claims 1 to 4, wherein the exposure control circuit controls switching between the first exposure mode and the second exposure mode alternately.
An exposure control circuit for controlling exposure of a pixel array, the pixel array including at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group arranged in 2 rows and 2 columns, wherein each of the first pixel group, the second pixel group, the third pixel group, and the fourth pixel group includes a first portion pixel, a second portion pixel, a third portion pixel, and a fourth portion pixel, the exposure control circuit comprising:

a first sub-exposure control circuit, a second sub-exposure control circuit, a third sub-exposure control circuit and a fourth sub-exposure control circuit arranged in 2 rows and 2 columns are correspondingly coupled to the first pixel group, the second pixel group, the third pixel group and the fourth pixel group;

wherein the first sub-exposure control circuit, the second sub-exposure control circuit, the third sub-exposure control circuit, and the fourth sub-exposure control circuit each include:

a control unit for generating an exposure control signal; and

the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer are respectively provided with a first input end, a second input end and an output end;

Wherein:

the output terminal of the first multiplexer of the first sub-exposure control circuit is coupled to the first partial pixel of the first pixel group to control an exposure time length, the output terminal of the second multiplexer of the first sub-exposure control circuit is coupled to the second partial pixel of the first pixel group to control an exposure time length, the output terminal of the third multiplexer of the first sub-exposure control circuit is coupled to the third partial pixel of the first pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the first sub-exposure control circuit is coupled to the fourth partial pixel of the first pixel group to control an exposure time length;

the output terminal of the first multiplexer of the second sub-exposure control circuit is coupled to the first partial pixel of the second pixel group to control an exposure time length, the output terminal of the second multiplexer of the second sub-exposure control circuit is coupled to the second partial pixel of the second pixel group to control an exposure time length, the output terminal of the third multiplexer of the second sub-exposure control circuit is coupled to the third partial pixel of the second pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the second sub-exposure control circuit is coupled to the fourth partial pixel of the second pixel group to control an exposure time length;

The output terminal of the first multiplexer of the third sub-exposure control circuit is coupled to the first partial pixel of the third pixel group to control an exposure time length, the output terminal of the second multiplexer of the third sub-exposure control circuit is coupled to the second partial pixel of the third pixel group to control an exposure time length, the output terminal of the third multiplexer of the third sub-exposure control circuit is coupled to the third partial pixel of the third pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the third sub-exposure control circuit is coupled to the fourth partial pixel of the third pixel group to control an exposure time length;

the output terminal of the first multiplexer of the fourth sub-exposure control circuit is coupled to the first partial pixel of the fourth pixel group to control an exposure time length, the output terminal of the second multiplexer of the fourth sub-exposure control circuit is coupled to the second partial pixel of the fourth pixel group to control an exposure time length, the output terminal of the third multiplexer of the fourth sub-exposure control circuit is coupled to the third partial pixel of the fourth pixel group to control an exposure time length, and the output terminal of the fourth multiplexer of the fourth sub-exposure control circuit is coupled to the fourth partial pixel of the fourth pixel group to control an exposure time length;

The first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the first sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the first sub-exposure control circuit;

the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the second sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the second sub-exposure control circuit;

the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the third sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the third sub-exposure control circuit;

the first input ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer of the fourth sub-exposure control circuit are all used for receiving the exposure control signals generated by the control unit of the fourth sub-exposure control circuit;

The second input terminal of the fourth multiplexer of the first sub-exposure control circuit, the second input terminal of the third multiplexer of the second sub-exposure control circuit, the second input terminal of the second multiplexer of the third sub-exposure control circuit, and the second input terminal of the first multiplexer of the fourth sub-exposure control circuit are all configured to receive the exposure control signal generated by the control unit of the first sub-exposure control circuit.
The exposure control circuit of claim 6, wherein the second input of the fourth multiplexer of the second sub-exposure control circuit and the second input of the second multiplexer of the fourth sub-exposure control circuit are configured to receive the exposure control signal generated by the control unit of the second sub-exposure control circuit.
The exposure control circuit of claim 6, wherein the second input of the fourth multiplexer of the third sub-exposure control circuit and the second input of the third multiplexer of the fourth sub-exposure control circuit are configured to receive the exposure control signal generated by the control unit of the third sub-exposure control circuit.
The exposure control circuit of claim 6, wherein the second input of the fourth multiplexer of the fourth sub-exposure control circuit is configured to receive the exposure control signal generated by the control unit of the fourth sub-exposure control circuit.
The exposure control circuit according to any one of claims 1 to 9, wherein the exposure control circuit controls a dynamic range of exposure of the pixel array in the first exposure mode to be larger than a dynamic range of exposure in the second exposure mode.
An image sensor, comprising:

the exposure control circuit according to any one of claims 1 to 10; and

the pixel array.
The image sensor of claim 11, wherein the exposure control circuit is disposed on a first substrate, the pixel array is disposed on a second substrate, and the first substrate and the second substrate are stacked by hybrid bonding.
An electronic device, comprising:

the image sensor of claim 12.