CN116210087A - Thin film transistor, manufacturing method thereof, display substrate and display device - Google Patents

Thin film transistor, manufacturing method thereof, display substrate and display device Download PDF

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Publication number
CN116210087A
CN116210087A CN202180002777.XA CN202180002777A CN116210087A CN 116210087 A CN116210087 A CN 116210087A CN 202180002777 A CN202180002777 A CN 202180002777A CN 116210087 A CN116210087 A CN 116210087A
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layer
substrate
barrier layer
electrode
thin film
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Inventor
屈财玉
郝艳军
张慧娟
樊宜冰
陈登云
宋尊庆
李栋
刘政
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor, a method of manufacturing the same, a display substrate, and a display device, the thin film transistor being provided on a substrate (10), the thin film transistor including: a first active layer (11) provided on one side of the substrate (10); a first gate electrode (12) provided on a side of the first active layer (11) away from the substrate (10); a first insulating layer (13) provided on the side of the first gate electrode (12) away from the substrate (10); a source electrode and a drain electrode (14) which are arranged on one side of the first insulating layer (13) far away from the substrate (10), wherein the source electrode and the drain electrode (14) are electrically connected with the first active layer (11); wherein, the first grid electrode(12) Comprising a laminate structure comprising: a first conductive layer (121); and a first barrier layer (122) provided on a side of the first conductive layer (121) away from the substrate (10), the side of the first barrier layer (122) away from the substrate (10) being in direct contact with a side of the first insulating layer (13) close to the substrate (10); wherein the first barrier layer (122) comprises TiN x1 Wherein 0.ltoreq.x1<0.2 X1 is the molar ratio of N/Ti.

Description

Thin film transistor, manufacturing method thereof, display substrate and display device Technical Field
The present disclosure relates to the field of display technology, and in particular, to a thin film transistor, a method of manufacturing the same, a display substrate, and a display device.
Background
In the related art, the display of the medium and large size display product is not uniform in the screen, and as the gate wiring grows, the resistance exists in the gate line, and the delay of the scanning signal can cause insufficient gate opening time, so that the display effect is poor and the brightness is not uniform. The middle of the screen on the visual display is cyan relative to the edges at two sides of the screen, and the edges at two sides of the screen are purple, so that the display effect is seriously affected.
Disclosure of Invention
In one aspect, a thin film crystal is providedAnd a body tube disposed on the substrate, wherein the thin film transistor includes: the first active layer is arranged on one side of the substrate base plate; the first grid electrode is arranged on one side, away from the substrate base plate, of the first active layer; the first insulating layer is arranged on one side, far away from the substrate, of the first grid electrode; the source electrode and the drain electrode are arranged on one side, far away from the substrate base plate, of the first insulating layer and are electrically connected with the first active layer; wherein the first gate includes a stacked structure including: a first conductive layer; the first barrier layer is arranged on one side, far away from the substrate, of the first conductive layer, and one side, far away from the substrate, of the first barrier layer is in direct contact with one side, close to the substrate, of the first insulating layer; wherein the first barrier layer comprises TiN x1 Wherein x1 is more than or equal to 0 and less than 0.2, and x1 is the molar ratio of N/Ti.
According to some exemplary embodiments, the stacked structure of the first gate further includes: a second barrier layer arranged between the first conductive layer and the first barrier layer, the second barrier layer comprising TiN x2 Wherein x2 is more than or equal to 0.1 and less than 0.8, and x2 is the molar ratio of N/Ti.
According to some exemplary embodiments, an adhesion force between a material of the first barrier layer and a material of the first insulating layer is greater than an adhesion force between a material of the second barrier layer and a material of the first insulating layer.
According to some exemplary embodiments, the first barrier layer has a first grain size and the second barrier layer has a second grain size, the first grain size being smaller than the second grain size.
According to some exemplary embodiments, the first barrier layer has a thickness in the range of 30 to 150 nanometers; and/or the thickness of the second barrier layer ranges from 30 to 150 nanometers.
According to some exemplary embodiments, the sum of the thickness of the first barrier layer and the thickness of the second barrier layer is in the range of 30 nm to 150 nm.
According toIn some exemplary embodiments, the stacked structure of the first gate further includes: a third barrier layer arranged between the first conductive layer and the substrate, the third barrier layer comprising TiN x3 Wherein x3 is more than or equal to 0 and less than 0.2, and x3 is the molar ratio of N/Ti.
According to some exemplary embodiments, the thin film transistor further comprises a second gate electrode, wherein the second gate electrode is disposed between the first active layer and the substrate base plate; the second grid electrode comprises a laminated structure, and the laminated structure of the second grid electrode is the same as that of the first grid electrode.
According to some exemplary embodiments, the first conductive layer comprises an aluminum alloy material.
In another aspect, there is also provided a method of manufacturing a thin film transistor, including: forming a first active layer on a substrate base plate; forming a first gate electrode on a side of the first active layer away from the substrate base plate; forming a first insulating layer on one side of the first gate electrode away from the substrate base plate; forming a source electrode and a drain electrode on one side of the first insulating layer away from the substrate base plate, wherein the source electrode and the drain electrode are electrically connected with the first active layer; wherein forming the first gate includes: forming a first conductive layer on one side of the first active layer away from the substrate base plate; and forming a first barrier layer on a side of the first conductive layer away from the substrate, the side of the first barrier layer away from the substrate being in direct contact with a side of the first insulating layer close to the substrate; wherein the first barrier layer comprises TiN x1 Wherein x1 is more than or equal to 0 and less than 0.2, and x1 is the molar ratio of N/Ti.
According to some exemplary embodiments, the method of manufacturing a thin film transistor further includes: a second gate electrode is formed on the substrate base plate before the first active layer is formed.
In another aspect, there is also provided a display substrate including: a substrate base; and a first transistor disposed on the substrate, wherein the first transistor is a thin film transistor as described above.
According to some exemplary embodiments, the display substrate further comprises a capacitor disposed on the substrate; the capacitor comprises a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode and the first grid are positioned on the same layer, the first capacitor electrode has a laminated structure, and the laminated structure of the first capacitor electrode is the same as that of the first grid.
According to some exemplary embodiments, the second capacitor electrode is electrically connected to the first active layer, the second capacitor electrode having a stacked structure identical to that of the first gate electrode.
According to some exemplary embodiments, the display substrate further includes a second transistor disposed on the substrate, the second transistor including: the third grid electrode is arranged on one side of the substrate base plate; the second insulating layer is arranged on one side of the third grid electrode far away from the substrate base plate; the second active layer is arranged on one side of the second insulating layer away from the substrate base plate; the third gate electrode and the first gate electrode are located on the same layer, and the third gate electrode has the same stacked structure as the first gate electrode.
According to some exemplary embodiments, the second transistor further comprises: and the fourth grid electrode is arranged on one side of the second active layer, which is far away from the substrate base plate, and has the same lamination structure as the first grid electrode.
According to some exemplary embodiments, the first active layer comprises a polysilicon material and the second active layer comprises a semiconductor oxide material.
According to some exemplary embodiments, the display substrate further comprises a shielding layer, wherein the shielding layer is disposed between the first active layer of the first transistor and the substrate.
In another aspect, there is also provided a display device comprising a display substrate as described above.
Drawings
Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1a schematically illustrates a cross-sectional structure diagram of a thin film transistor according to an exemplary embodiment of the present disclosure;
fig. 1b schematically illustrates a cross-sectional structure diagram of a thin film transistor according to another exemplary embodiment of the present disclosure;
fig. 2a schematically illustrates a cross-sectional structural schematic of a first gate according to an exemplary embodiment of the present disclosure;
Fig. 2b schematically illustrates a schematic cross-sectional structure of a first gate according to another exemplary embodiment of the present disclosure;
fig. 2c schematically illustrates a schematic cross-sectional structure of a first gate according to yet another exemplary embodiment of the present disclosure;
fig. 3a schematically illustrates a schematic of bonding a first insulating layer on a first barrier layer according to an embodiment of the disclosure;
FIG. 3b schematically illustrates a schematic view of first barrier cleaving from a first insulating layer when the N content of the first barrier material is high, in accordance with an embodiment of the present disclosure;
FIG. 3c schematically illustrates a schematic diagram of adhesion of a first barrier layer to a first insulating layer when the N content of the first barrier layer material is low, according to an embodiment of the disclosure;
FIG. 4a schematically illustrates a schematic diagram of grain size at a first barrier layer according to an embodiment of the present disclosure;
FIG. 4b schematically illustrates a schematic view of grain size at a second barrier layer according to an embodiment of the disclosure;
figure 4c schematically illustrates a schematic diagram of the barrier material's performance in resisting etching by an ILD dielectric layer etchant in accordance with an embodiment of the present disclosure;
FIG. 4d schematically illustrates a schematic diagram of the performance of a barrier material in resisting BOE etchant etching in accordance with an embodiment of the present disclosure;
Fig. 4e schematically illustrates a cross-sectional view of a first gate having a third barrier layer according to an exemplary embodiment of the present disclosure;
fig. 5 schematically illustrates a flow chart of a method of manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 6 schematically illustrates a specific flow of a thin film transistor at step S2 according to an exemplary embodiment of the present disclosure;
fig. 7a schematically illustrates an interface structure diagram of a thin film transistor at step S1 according to an exemplary embodiment of the present disclosure;
fig. 7b schematically illustrates an interface structure diagram of a thin film transistor at step S2 according to an exemplary embodiment of the present disclosure;
fig. 7c schematically illustrates an interface structure diagram of a thin film transistor at step S3 according to an exemplary embodiment of the present disclosure;
fig. 7d schematically illustrates an interface structure diagram of a thin film transistor at step S4 according to an exemplary embodiment of the present disclosure;
fig. 8 schematically illustrates a structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;
fig. 9 schematically illustrates a structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;
fig. 10 schematically illustrates a structural diagram of yet another display substrate according to an exemplary embodiment of the present disclosure.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are intended to be within the scope of the present disclosure, based on the described embodiments of the present disclosure.
It is noted that in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or description. As such, the dimensions and relative dimensions of the various elements are not necessarily limited to those shown in the figures. In the description and drawings, the same or similar reference numerals refer to the same or similar parts.
When an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions describing the relationship between elements should be interpreted in a similar manner, e.g. "between … …" pair "directly between … …", "adjacent" pair "directly adjacent" or "on … …" pair "directly on … …" etc. Furthermore, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. Further, the X-axis, Y-axis, and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that although the terms "first," "second," etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer and/or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below may be referred to as a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present disclosure.
For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" or "above" the other elements or features.
It should be noted that, in this document, the expression "adhesion force" may refer to the magnitude of the bonding force between two material layers in contact, for example, the contact between materials may be different material layers formed by different processes, or may be different material layers formed by the same process, and the adhesion force refers to the bonding strength between two materials, the larger the bonding strength, the larger the adhesion force, and vice versa, the smaller the bonding strength, and the smaller the bonding force.
Fig. 1a schematically illustrates a cross-sectional structure diagram of a thin film transistor according to an exemplary embodiment of the present disclosure.
Fig. 1b schematically illustrates a cross-sectional structure of a thin film transistor according to another exemplary embodiment of the present disclosure.
The structure of an exemplary thin film transistor according to the present disclosure is described in detail below in conjunction with fig. 1 a.
As shown in fig. 1a, a thin film transistor is disposed on an upper side of a substrate base 10, wherein the thin film transistor includes a first active layer 11, a first gate electrode 12, a first insulating layer 13, a source electrode and a drain electrode 14.
Wherein the first active layer 11 is disposed at one side of the substrate base 10. For example, on the film structure 15 provided on the upper side of the substrate base 10, the film structure 15 on the substrate base 10 may be a polyimide film or a buffer film. The first active layer 11 may be disposed on the polyimide film layer or on the buffer film layer. The film layer structure 15 may be a single-layer film layer structure or a multi-layer film layer structure.
A first gate insulating layer 16 is disposed on the first active layer 11. The material of the first gate insulating layer 16 may be, for example, silicon oxide or silicon nitride, a double layer structure composed of a silicon oxide film and a silicon nitride film, or the like.
The first gate electrode 12 is disposed on a side of the first active layer 11 remote from the substrate 10. For example, on the first gate insulating layer 16.
The first insulating layer 13 is disposed on a side of the first gate electrode 12 away from the substrate 10. For example, the first insulating layer 13 is provided on a side of the first gate insulating layer 16 remote from the substrate base plate 10, and the first insulating layer 13 is provided so as to cover the first gate electrode 12.
The source and drain electrodes 14 are disposed on a side of the first insulating layer 13 remote from the substrate 10, and the source and drain electrodes 14 are electrically connected to the first active layer 11. For example, an interlayer insulating layer 17 is provided on a side of the first insulating layer 13 remote from the substrate 10, the source and drain electrodes 14 are provided on the interlayer insulating layer 17, and a portion of the source and drain electrodes 14 passes through the interlayer insulating layer 17, the first insulating layer 13, and the first gate insulating layer 16 and is electrically connected to the active layer 11.
In an exemplary embodiment of the present disclosure, as shown in fig. 1b, the thin film transistor may further include a second gate electrode 18, the second gate electrode 18 being disposed between the first active layer 11 and the substrate base plate 10. For example, between the membrane layer structure 15 and the substrate base plate 10.
In an exemplary embodiment of the present disclosure, a multi-layered film structure is provided on the source and drain electrodes 14 for packaging the thin film transistor. For example, may include a planarization layer 19, a pixel defining layer 20, a light emitting layer 21, a cathode 22, an encapsulation layer 23, and an anode 24. The encapsulation layer 23 may include a plurality of inorganic thin film layers.
Fig. 2a to 2c schematically show cross-sectional structural diagrams of a first gate according to an exemplary embodiment of the present disclosure.
In one exemplary embodiment of the present disclosure, as shown in fig. 2a, the first gate electrode 12 has a stacked structure including a first conductive layer 121 and a first barrier layer 122. Wherein the first conductive layer 121 is disposed on a side of the first active layer 11 away from the substrate 10, specifically, the first conductive layer 121 is disposed on a side of the first gate insulating layer 16 away from the substrate 10. The first barrier layer 122 is disposed on a side of the first conductive layer 121 away from the substrate base plate 10, i.e., on an upper side of the first conductive layer 121.
The material of the first conductive layer 121 may be aluminum or an aluminum alloy having good conductive properties on the one hand and a low young's modulus on the other hand. The aluminum alloy may include at least one of the following elements: ce. Zr, sc, mn, ni, la. In the related art, mo is used to make the gate metal layer, and the resistivity of Mo is as high as 17.6 micro-ohm-cm, and in contrast, when the first conductive layer is aluminum or aluminum alloy, the resistivity of the first conductive layer is 4.2 micro-ohm-cm, which is far smaller than the resistivity of Mo, and the gate metal layer has good conductivity. The adoption of aluminum and aluminum alloy can enable the grid line of the first grid electrode to have lower resistance, the delay time of the scanning signal is shorter, and the display effect of the display substrate can be ensured.
According to the embodiment of the disclosure, aluminum and aluminum alloy are adopted as the first conductive layer material, so that the uniformity of display in a screen of a medium-and-large-size product can be ensured, the self resistance of the grid line is reduced, the delay time of a scanning signal is further shortened, and the display effect is improved. In addition, the first grid electrode material with low resistance is made of aluminum or aluminum alloy material, the Young modulus of the first grid electrode material is 90GPa, the Young modulus of the first grid electrode material is lower than that of grid electrode Mo (Young modulus is 137 GPa) in the related art, the bending resistance of the first grid electrode material is better, and the strain of the first grid electrode material is 5.97E-03 in a bending experiment with the radius of 3 mm. In the related art, mo wire is entirely broken after 2300 times of bending. The aluminum or aluminum alloy material is bent for 10 ten thousand times, and has no fracture and almost unchanged resistance, so that the folding product has better effect.
In an embodiment of the present disclosure, the first barrier layer 122 comprises TiN x1 Wherein x1 is more than or equal to 0 and less than 0.2, and x1 is the molar ratio of N/Ti, preferably more than or equal to 0.1 and less than or equal to 0.15. First barrier layer 122For adhesion to the first insulating layer 13, preventing peeling between the first barrier layer 122 and the first insulating layer 13. The different contents of N element and Ti element lead to different adhesion performance of the material of the first barrier layer and the inorganic layer SiN, and the molar ratio M of N to Ti content in the first barrier layer 122 is in the range of 0.ltoreq.M < 0.2, so that the first barrier layer 122 and the first insulating layer 13 have better adhesion. That is, the N content in the first barrier layer 122 of the present disclosure is set to a relatively low range, which has a good adhesion property with the first insulating layer 13 on the one hand, and suppresses the occurrence of surface defects of the first conductive layer 121 during the manufacturing process, for example, the occurrence of protrusions on the surface of the first conductive layer 121 while suppressing damage of the etching liquid to the surface of the metal line on the other hand. In addition, the first barrier layer 122 can effectively inhibit the damage of the etching solution to the surface of the metal line in the manufacturing process of the thin film transistor. For example, damage to the metal line surface by the BOE etchant and the ILD dielectric layer etchant is suppressed.
As shown in fig. 2b, the stacked structure of the first gate electrode 12 may further include a second barrier layer 123, wherein the second barrier layer 123 is disposed between the first conductive layer 121 and the first barrier layer 122, and the second barrier layer 123 includes TiN x2 Wherein x2 is more than or equal to 0.1 and less than 0.8, x2 is the molar ratio of N/Ti, and x2 is preferably more than or equal to 0.5 and less than or equal to 0.2 and less than 0.8. In the embodiment of the present disclosure, the first barrier layer 122 and the second barrier layer 123 are both made of titanium nitride, and the content of N element in titanium nitride has a great influence on the performance thereof, specifically including the etching resistance of the etching solution, and the adhesion between titanium nitride and other materials.
In conducting the related experiments, it was found that the effect of the content of N element in titanium nitride on its performance was not linear. For example, when the content of N element is low, the etching capability against the BOE etching liquid or the ILD dielectric layer etching liquid is high, and when the content of N element is 0, the etching capability against the BOE etching liquid or the ILD dielectric layer etching liquid is weak. That is, the content of N element needs to be kept in a low range to achieve a superior etching resistance against the etching liquid.
The content of N element in the titanium nitride is found to have a great influence on the adhesion between the first barrier layer material and the first insulating layer material in the test.
In an embodiment of the present disclosure, the adhesion between the material of the first barrier layer 122 and the material of the first insulating layer 13 is greater than the adhesion between the material of the second barrier layer 123 and the material of the first insulating layer 13.
Fig. 3a schematically illustrates a schematic of bonding a first insulating layer on a first barrier layer according to an embodiment of the disclosure.
The titanium nitride with a lower N content in the first barrier layer material has a higher adhesion between the titanium nitride with a lower N content and the material of the first insulating layer 13 than the titanium nitride with a higher N content. For example, tiN x1 Compared with TiN x2 With higher adhesion, i.e. TiN x1 Can be better bonded to the first insulating layer 13. As shown in FIG. 3a, when x1 takes on a value of 0.15, the composition contains TiN 0.15 The adhesion of the first barrier layer 122 to the first insulating layer 13 is good. After the first insulating layer 13 is laid on the gate material 12, no peeling occurs. In fig. 3a, although a white bright spot area H exists in the box, the bright spot area H is a perforated position of the interlayer insulating layer 17, not a peeling condition existing in the manufacturing process. It can be seen from fig. 3a that the material of the first barrier layer 122 can improve the adhesion with the first insulating layer by using titanium nitride having a lower N content.
The N content in the second barrier layer material is higher than that of the first barrier layer material, and therefore, the adhesion between the material of the second barrier layer 123 and the material of the first insulating layer 13 is smaller than that of the first barrier layer 122 and the material of the first insulating layer 13. In contrast, titanium nitride having a higher N content can better suppress defects occurring in the first conductive layer 121 during the manufacturing process on the first conductive layer 121. I.e., the material of the second barrier layer 123 has more excellent properties in suppressing defects of the first conductive layer 121 than the material of the first barrier layer 122. The material of the first barrier layer 122 has more excellent adhesion performance in terms of adhesion to the first insulating layer 13 than the material of the second barrier layer 123.
Fig. 3b schematically illustrates a schematic view of cleavage of the first barrier layer from the first insulating layer when the N-content of the first barrier layer material is high, according to an embodiment of the disclosure. Fig. 3c schematically illustrates a schematic diagram of adhesion of a first barrier layer to a first insulating layer when the N content of the first barrier layer material is low, according to an embodiment of the disclosure.
As shown in fig. 3b, when TiN is in the first barrier layer x1 Is susceptible to cleavage (peeling), i.e. in the first barrier layer (TiN in fig. 3b 0.9 ) And the first insulating layer (gi2+ild in fig. 3 b), resulting in low yield. Therefore, there is a need to reduce TiN x1 The content of N in the first barrier layer and the first insulating layer. On the other hand, when the N content in TiN is low, defects in the manufacturing process of the first conductive layer cannot be effectively suppressed, in order to better suppress defects in the manufacturing process of the first conductive layer, a second barrier layer is introduced, and the N content of the second barrier layer is set higher than that of the first barrier layer, for example, the second barrier layer includes TiN x2 Wherein x2 is more than or equal to 0.1 and less than 0.8, and preferably x2 is more than or equal to 0.5 and less than or equal to 0.8, and x 2=0.5 in the embodiment, the inhibition effect of the second barrier layer on the defects of the first conductive layer is realized. A second barrier layer is provided between the first barrier layer and the first insulating layer as shown in fig. 3c, which prevents cracks from forming between the first barrier layer and the first insulating layer on the one hand, and which may otherwise present manufacturing defects on the surface of the first conductive layer in a manner that no cracks are created between the first barrier layer and the first insulating layer, nor defects are present on the surface of the first conductive layer as shown in fig. 3 c.
According to the embodiment of the present disclosure, the provision of the first barrier layer 122 on the first conductive layer 121 improves the adhesion state between the first gate electrode 12 and the first insulating layer 13, preventing the occurrence of peeling between the first gate electrode 12 and the first insulating layer 13. In addition, the second barrier layer 123 disposed between the first conductive layer 121 and the first barrier layer 122 can make up for the defect suppression capability of the first barrier layer 122 on the surface of the first conductive layer 121.
Fig. 4a schematically illustrates a schematic of grain size at a first barrier layer according to an embodiment of the present disclosure.
Fig. 4b schematically illustrates a schematic view of grain size at a second barrier layer according to an embodiment of the disclosure.
As shown in fig. 4a, the material of the first barrier layer 122 is titanium nitride with low nitrogen content, such as TiN 0.15 It has better adhesion property with the first insulating layer than titanium nitride with high nitrogen content. In addition, the material of the first barrier layer 122 has finer grains, such as the enlarged region in box a, whose grain size is smaller and whose grain size is distributed in the range of 100 nm to 200 nm, and the fine grains have more excellent etching resistance in terms of etching resistance.
As shown in fig. 4b, the material of the second barrier layer 123 is titanium nitride with higher nitrogen content, such as TiN 0.5 It has a better suppressing effect on defects of the first conductive layer than titanium nitride having a low nitrogen content. In addition, the material of the second barrier layer 123 has finer and larger grains, such as the enlarged region in block B, whose grain size is larger and whose grain size is distributed in the range of 300 nm to 500 nm, and coarse grains whose etching resistance is relatively inferior to fine grains in terms of etching resistance.
Figure 4c schematically illustrates a schematic diagram of the performance of a barrier layer material in resisting etching by an ILD dielectric layer etching solution according to an embodiment of the disclosure.
When the etching liquid etching of the ILD dielectric layer is carried out, titanium nitride with different nitrogen contents has different etching resistance. As shown in FIG. 4c, the materials represented by (a) - (f) are respectively barrier-free (a), barrier-containing Ti (b), barrier-containing TiN 0.15 (c) Comprising barrier TiN 0.3 (d) Comprising barrier TiN 0.5 (e) Comprising barrier TiN 0.9 (f) A. The invention relates to a method for producing a fibre-reinforced plastic composite As can be seen, (b) etched depth was 51.6 nm, (c) etched depth was 47.4 nm, (d) etched depth was 55.6 nm, (e) etched depth was 75.1 nm, (f) etched depth was 83 nm, following the etchingThe N content is increased and the etching performance is reduced. I.e., the greater the nitrogen content, the greater the depth etched by the ILD dielectric layer etchant, and therefore the lower the titanium nitride (e.g., tiN 0.15 ) The etching resistance of the first barrier layer is improved.
Fig. 4d schematically illustrates a performance schematic of a barrier material against BOE etchant according to an embodiment of the present disclosure.
In addition, the etching resistance of the BOE etchant is also related to the nitrogen content of titanium nitride, and as shown in FIG. 4d, the materials represented by (a) - (d) are respectively TiN without barrier layer (a), ti (b), and TiN 0.5 (c) Comprising barrier TiN 0.9 (d) The nitrogen content of titanium nitride increases in sequence. As can be seen from fig. 4d, the corrosion resistance is more excellent at a lower nitrogen content. In particular, in the case of TiN containing barrier layer 0.5 (c) And the thickness of the residual unetched film is 47 nanometers, and the surface of the unetched film is flat. In the presence of a barrier layer TiN 0.9 (d) The remaining unetched thickness was 20 nm, and the surface thereof had a rugged structure due to etching. Therefore, when the N content is 0.5, the corrosion of the corrosion liquid of the BOE can be effectively blocked. In addition, the etched surface has a relatively flat plane, and has smaller resistance when other film structures are formed on the surface of the etched surface. Therefore, in order to enable the etched surface to have a relatively flat plane and improve the etching resistance, a barrier layer material with relatively low N content can be selected.
In an exemplary embodiment of the present disclosure, the thickness of the first barrier layer 122 ranges from 30 to 150 nanometers, preferably from 100 to 120 nanometers. The thickness of the second barrier layer 123 ranges from 30 nm to 150 nm, preferably from 30 nm to 50 nm.
The sum of the thickness of the first barrier layer 122 and the thickness of the second barrier layer 123 is in the range of 30 nm to 150 nm. I.e. the sum of the thicknesses between the first barrier layer 122 and the second barrier layer 123 meets a set range, e.g. the sum of the thicknesses is 50 nm, or 100 nm, etc. Can be adjusted according to actual requirements.
Exemplary implementations of the present disclosureIn an embodiment, as shown in fig. 2c, the stacked structure of the first gate electrode 12 further includes a third barrier layer 124 disposed between the first conductive layer 121 and the substrate 10. Specifically, the third barrier layer 124 is disposed on the first gate insulating layer 16, and the upper side of the third barrier layer 124 is the first conductive layer 121. The material of the third barrier layer 124 comprises TiN x3 Wherein 0.ltoreq.x3 < 0.2, preferably 0.1.ltoreq.x3.ltoreq.0.15.
In some embodiments, the conductive layer of the first gate 12 may also be in contact with the first active layer, and a third barrier layer 124 as shown in fig. 2c may be provided in order to avoid co-dissolution of the conductive layer metal of the first gate when in contact with the silicon of the first active layer. The third barrier layer 124 can prevent the first conductive layer 121 of the first gate electrode 12 from being co-dissolved with the active layer contact.
Fig. 4e schematically illustrates a cross-sectional view of a first gate having a third barrier layer according to an exemplary embodiment of the present disclosure.
For example, as shown in FIG. 4e, the first barrier layer in this embodiment comprises TiN 0.15 The first conductive layer is aluminum alloy, and the second barrier layer is TiN 0.5 The third barrier layer is TiN 0.15 . The first grid electrode with the laminated structure has higher yield in production and manufacture.
According to the embodiment of the disclosure, by providing the third barrier layer 124, on one hand, the high temperature aluminum alloy (i.e., the first conductive layer) is prevented from generating protrusions (hillock) to damage the lower film layer, and on the other hand, the occurrence of cracking (peeling) with the inorganic layer due to the high N content in TiN is avoided, so that the probability of generating defects in the manufacturing process is reduced.
The thickness of the third barrier layer 124 ranges between 30 nanometers and 150 nanometers, preferably between 30 and 50 nanometers.
In the embodiments of the present disclosure, the first gate structure adopts the stacked structure described above, and has a low resistance, for example, the first gate structure with low resistance includes two layers, an Al alloy material layer near the substrate, and TiN 0.15 A layer. For another example, the low-resistance first gate structure includes four layers of TiN in sequence 0.15 Layer, al alloy material layer, tiN 0.5 Layer, tiN 0 A layer.
In the exemplary embodiment of the present disclosure, the second gate electrode 18 also has a stacked structure, and the stacked structure of the second gate electrode 18 is the same as that of the first gate electrode 12. For example, the stacked structure of the second gate electrode 18 may include one or more of a first conductive layer, a first barrier layer, and a second and third barrier layer.
Fig. 5 schematically illustrates a flowchart of a method of manufacturing a thin film transistor according to an embodiment of the present disclosure.
Fig. 6 schematically shows a specific flow of a thin film transistor at step S2 according to an exemplary embodiment of the present disclosure.
As shown in fig. 5, the method of manufacturing the thin film transistor according to the embodiment of the present disclosure includes steps S01 to S05.
Fig. 7a schematically illustrates an interface structure diagram of a thin film transistor at step S1 according to an exemplary embodiment of the present disclosure.
In step S1, as shown in fig. 5 and 7a, a first active layer 11 is formed on a base substrate 10.
First, the substrate 10 (for example, glass substrate) is initially cleaned, the film structure 15 is formed on the substrate 10, for example, a double-layer PI glue is coated on the substrate 10, and a PI film 151 is formed by curing at 300 to 400 ℃ to form a PI film of about 10 um.
Then a thin film layer is manufactured on the substrate base plate/PI substrate, and the specific manufacturing process of the thin film layer is as follows: deposition of buffer layer 152 (of double-layer SiN) by Plasma Enhanced Chemical Vapor Deposition (PECVD) x /SiO 2 Film), firstly depositing a silicon nitride layer with the thickness of 50-300 nm, and then depositing a silicon dioxide layer with the thickness of 100-300 nm. And then depositing an amorphous silicon layer with the thickness of 40-50 nm according to the requirement. And after the amorphous silicon layer is deposited, heating the amorphous silicon layer at 400 ℃ for 0.5-3 hours. Then simultaneously performing Excimer Laser Annealing (ELA) process on the amorphous silicon region, patterning the polysilicon to form a channel, performing Vth pumping, and finally forming a first An active layer 11.
Then, on the basis of this, a first gate insulating layer 16 (GI 1 thin film layer) is deposited, and the specific manufacturing process of the first gate insulating layer 16 is as follows: depositing a dielectric layer (the dielectric layer is a double-layer structure SiN) by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method x /SiO 2 Film), firstly depositing a silicon oxide layer with the thickness of 400-1000nm, and then depositing a silicon nitride layer with the thickness of 100-500 nm.
Fig. 7b schematically illustrates an interface structure diagram of a thin film transistor at step S2 according to an exemplary embodiment of the present disclosure.
In step S2, as shown in fig. 5 and 7b, a first gate electrode 12 is formed on a side of the first active layer 11 remote from the substrate base plate 10.
For example, after the first gate insulating layer 16 is formed, the first gate electrode 12 is deposited by plasma sputtering (Sputer). And the first gate 12 layer is patterned.
Fig. 7c schematically illustrates an interface structure diagram of a thin film transistor at step S3 according to an exemplary embodiment of the present disclosure.
In step S3, as shown in fig. 5 and 7c, a first insulating layer 13 is formed on the side of the first gate electrode 12 remote from the substrate base plate 10.
A first insulating layer 13 (GI 2 thin film layer) is deposited on a side of the first gate electrode 12 away from the substrate 10, and the specific manufacturing process of the first insulating layer 13 is as follows: and depositing a dielectric layer (SiNx with a single-layer structure of 100-150 nm) by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
On the basis of the above, an interlayer insulating layer 17 (ILD film layer) is formed, and the specific manufacturing process for forming the interlayer insulating layer is as follows: depositing a dielectric layer (the dielectric layer is a double-layer structure SiN) by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method x /SiO 2 Film), firstly depositing a silicon oxide layer with the thickness of 150-200nm, then depositing a silicon nitride layer with the thickness of 200-300nm, patterning the interlayer insulating layer, and etching in a one-step etching or step-by-step etching mode.
Fig. 7d schematically illustrates an interface structure diagram of a thin film transistor according to an exemplary embodiment of the present disclosure at step S4.
In step S4, as shown in fig. 5 and 7d, source and drain electrodes 14 are formed on a side of the first insulating layer 13 remote from the substrate base plate 10, the source and drain electrodes 14 being electrically connected to the first active layer 11.
After the interlayer insulating layer 17 is formed, the source and drain electrodes 14 are further formed, the source and drain electrodes 14 are electrically connected to the first active layer 11, and then, the planarization layer 19, the pixel defining layer 20, the light emitting layer 21, the anode 24, the cathode 22, the encapsulation layer 23, and the like are sequentially formed on the side of the source and drain electrodes 14 away from the substrate 10.
In an exemplary embodiment of the present disclosure, the method of manufacturing a thin film transistor further includes step S0, and in step S0, the second gate electrode 18 is formed on the substrate base plate 10 before the first active layer 11 is formed.
In an exemplary embodiment of the present disclosure, as shown in fig. 6, forming the first gate electrode 12 may include steps S21 to S24 in particular in step S2. The specific steps of forming the first gate electrode are different depending on the structure of the first gate electrode 12.
For example, when the structure of the first gate electrode 12 is as shown in fig. 2a, the step of forming the first gate electrode 12 includes S22 and S24. That is, in step S22, the first conductive layer 121 is formed on the side of the first active layer 11 remote from the substrate base plate 10. After the first conductive layer 121 is formed, step S24 is performed, i.e., the first barrier layer 122 is formed on the side of the first conductive layer 121 remote from the substrate 10.
For another example, when the structure of the first gate 12 is as shown in fig. 2b, the step of forming the first gate includes step S22, step S23, and step S24. Specifically, in step S22, the first conductive layer 121 is formed on the side of the first active layer 11 remote from the substrate base plate 10. After the first conductive layer 121 is formed, step S23 is performed to form the second barrier layer 123 on the side of the first conductive layer 121 away from the substrate. Then, step S24 is performed to form a first barrier layer 122 on the side of the first conductive layer 121 away from the substrate 10 (i.e., on the second barrier layer 123).
For another example, when the structure of the first gate 12 is as shown in fig. 2c, the step of forming the first gate includes step S21, step S22, step S23, and step S24. Specifically, in step S21, the third barrier layer 124 is formed on the side of the first active layer remote from the substrate base plate. After the third barrier layer 124 is formed, step S22 is performed, that is, the first conductive layer 121 is formed on the side of the first active layer away from the substrate, specifically, the first conductive layer 121 is formed on the side of the third barrier layer 124 away from the substrate. After the first conductive layer 121 is formed, step S23 is performed to form the second barrier layer 123 on the side of the first conductive layer 121 away from the substrate. Then, step S24 is performed to form a first barrier layer 122 on the side of the first conductive layer 121 away from the substrate 10 (i.e., on the second barrier layer 123).
Fig. 8 schematically illustrates a structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
As shown in fig. 8, the display substrate includes a substrate 10, and a first transistor disposed on the substrate 10, the first transistor is a thin film transistor as described above, that is, includes a first active layer 11, a first gate electrode 12, and source and drain electrodes 14.
Specifically, a film layer structure 15 is disposed on the upper layer of the substrate 10, and the film layer structure 15 may include, for example, a PI film layer 151 and a buffer layer 152. The first transistor is formed on a side of the buffer layer 152 remote from the substrate base plate 10.
The display substrate further includes a capacitor 25 disposed on the substrate, the capacitor including a first capacitor electrode 251 and a second capacitor electrode 252, the first capacitor electrode 251 and the first gate electrode 12 being disposed on the same layer, the first capacitor electrode 251 having a stacked structure, the stacked structure of the first capacitor electrode 251 being the same as the stacked structure of the first gate electrode 12.
Fig. 9 schematically illustrates a structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
Fig. 9 shows another structure of a display substrate, which also includes the thin film transistor described above, wherein the display substrate further includes a capacitor 25' disposed on the substrate, the capacitor 25' including a first capacitor electrode 251' and a second capacitor electrode 252', the second capacitor electrode 252' being electrically connected to the first active layer 11, the second capacitor electrode 252' having a stacked structure, the stacked structure of the second capacitor electrode 252' being identical to that of the first gate electrode 12.
Fig. 10 schematically illustrates a structural diagram of yet another display substrate according to an exemplary embodiment of the present disclosure.
Fig. 10 shows a structure of yet another display substrate including a second transistor disposed on a substrate 10, in a region where C is shown, the second transistor including: a third gate electrode 26 provided on one side of the substrate 10; the second insulating layer 153 is disposed on a side of the third gate electrode 26 away from the substrate 10; a second active layer 27 disposed on a side of the second insulating layer 153 away from the substrate 10; the third gate electrode 26 is located at the same layer as the first gate electrode 12, and the third gate electrode 26 has the same stacked structure as the first gate electrode 12.
The second transistor further includes: the fourth gate electrode 28 is disposed on a side of the second active layer 27 away from the substrate 10, and the fourth gate electrode 28 has the same stacked structure as the first gate electrode 12.
In an embodiment of the present disclosure, the first active layer 11 comprises a polysilicon material and the second active layer 27 comprises a semiconductor oxide material.
For example, the first active layer 12 may include a polysilicon semiconductor material (e.g., low temperature polysilicon), an amorphous silicon semiconductor material, a non-silicon-based semiconductor material such as carbon nanotubes, and the like. In an embodiment of the present disclosure, the second active layer 27 may be formed of an oxide semiconductor, and for example, may include a ZnO-based oxide layer. The second active layer 27 may further contain a group III element such as In or Ga, a group IV element such as Sn, a combination thereof, or other elements. As another example, the active layer 27 may include a Cu oxide layer (CuBO 2 Layer, cuAlO 2 Layer, cuGaO 2 Layer, cuInO 2 Layer, etc.), a Ni oxide layer doped with Ti, a ZnO-based oxide layer doped with at least one of group I, group II, and group V elements, a ZnO-based oxide layer doped with Ag, a PbS layer, a LaCuOS layer, or a LaCuOSe layer. As an exampleThe second active layer 27 may include indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO), indium tin zinc oxide (Indium Tin Zinc Oxide, abbreviated as ITZO), or indium zinc oxide (Indium Zinc Oxide, abbreviated as IZO).
In an embodiment of the present disclosure, the display substrate further comprises a shielding layer 29, wherein the shielding layer 29 is disposed between the first active layer 11 of the first transistor and the substrate 10.
The present disclosure also provides a display device comprising a display substrate as described above.
Although a few embodiments of the present general technical concept have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general technical concept, the scope of which is defined in the claims and their equivalents.

Claims (19)

  1. A thin film transistor disposed on a substrate, wherein the thin film transistor comprises:
    The first active layer is arranged on one side of the substrate base plate;
    the first grid electrode is arranged on one side, away from the substrate base plate, of the first active layer;
    the first insulating layer is arranged on one side, far away from the substrate, of the first grid electrode;
    the source electrode and the drain electrode are arranged on one side, far away from the substrate base plate, of the first insulating layer and are electrically connected with the first active layer;
    wherein the first gate includes a stacked structure including:
    a first conductive layer; and
    a first barrier layer arranged on one side of the first conductive layer away from the substrate base plate,
    one side of the first barrier layer far away from the substrate base plate is in direct contact with one side of the first insulating layer close to the substrate base plate;
    wherein the first barrier layer comprisesTiN x1 Wherein x1 is more than or equal to 0 and less than 0.2, and x1 is the molar ratio of N/Ti.
  2. The thin film transistor of claim 1, wherein the stacked structure of the first gate electrode further comprises:
    a second barrier layer arranged between the first conductive layer and the first barrier layer, the second barrier layer comprising TiN x2 Wherein x2 is more than or equal to 0.1 and less than 0.8, and x2 is the molar ratio of N/Ti.
  3. The thin film transistor of claim 2, wherein an adhesion force between a material of the first barrier layer and a material of the first insulating layer is greater than an adhesion force between a material of the second barrier layer and a material of the first insulating layer.
  4. A thin film transistor according to claim 2 or 3, wherein the first barrier layer has a first grain size and the second barrier layer has a second grain size, the first grain size being smaller than the second grain size.
  5. The thin film transistor of claim 2, wherein the first barrier layer has a thickness in the range of 30 to 150 nanometers; and/or the number of the groups of groups,
    the thickness of the second barrier layer ranges from 30 to 150 nanometers.
  6. The thin film transistor of claim 5, wherein a sum of a thickness of the first barrier layer and a thickness of the second barrier layer is in a range of 30 nm to 150 nm.
  7. The thin film transistor according to any one of claims 1 to 6, wherein the stacked structure of the first gate electrode further comprises:
    a third barrier layer arranged between the first conductive layer and the substrate, the third barrier layer comprising TiN x3 Wherein x3 is more than or equal to 0 and less than 0.2, and x3 is N/Ti Molar ratio of (3).
  8. The thin film transistor of any one of claims 1 to 6, further comprising a second gate electrode, wherein the second gate electrode is disposed between the first active layer and the substrate base plate;
    the second grid electrode comprises a laminated structure, and the laminated structure of the second grid electrode is the same as that of the first grid electrode.
  9. The thin film transistor of any one of claims 1 to 6, the first conductive layer comprising an aluminum alloy material.
  10. A method of manufacturing a thin film transistor, comprising:
    forming a first active layer on a substrate base plate;
    forming a first gate electrode on a side of the first active layer away from the substrate base plate;
    forming a first insulating layer on one side of the first gate electrode away from the substrate base plate;
    forming a source electrode and a drain electrode on one side of the first insulating layer away from the substrate base plate, wherein the source electrode and the drain electrode are electrically connected with the first active layer;
    wherein forming the first gate includes:
    forming a first conductive layer on one side of the first active layer away from the substrate base plate; and
    forming a first barrier layer on one side of the first conductive layer far away from the substrate, wherein one side of the first barrier layer far away from the substrate is in direct contact with one side of the first insulating layer close to the substrate;
    Wherein the first barrier layer comprises TiN x1 Wherein x1 is more than or equal to 0 and less than 0.2, and x1 is the molar ratio of N/Ti.
  11. The manufacturing method of a thin film transistor according to claim 10, further comprising:
    a second gate electrode is formed on the substrate base plate before the first active layer is formed.
  12. A display substrate, comprising:
    a substrate base; and
    a first transistor disposed on the substrate,
    wherein the first transistor is the thin film transistor according to any one of claims 1 to 9.
  13. The display substrate of claim 12, further comprising a capacitor disposed on the substrate;
    the capacitor comprises a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode and the first grid are positioned on the same layer, the first capacitor electrode has a laminated structure, and the laminated structure of the first capacitor electrode is the same as that of the first grid.
  14. The display substrate of claim 13, wherein the second capacitor electrode is electrically connected to the first active layer, the second capacitor electrode having a stacked structure that is the same as the stacked structure of the first gate electrode.
  15. The display substrate of claim 12, wherein the display substrate further comprises a second transistor disposed on the substrate, the second transistor comprising:
    the third grid electrode is arranged on one side of the substrate base plate;
    the second insulating layer is arranged on one side of the third grid electrode far away from the substrate base plate;
    the second active layer is arranged on one side of the second insulating layer away from the substrate base plate;
    the third gate electrode and the first gate electrode are located on the same layer, and the third gate electrode has the same stacked structure as the first gate electrode.
  16. The display substrate of claim 15, wherein the second transistor further comprises:
    a fourth grid electrode arranged on one side of the second active layer away from the substrate base plate,
    the fourth gate electrode has the same stacked structure as the first gate electrode.
  17. The display substrate of claim 15 or 16, wherein the first active layer comprises a polysilicon material and the second active layer comprises a semiconductor oxide material.
  18. The display substrate of claim 12, further comprising a shielding layer, wherein the shielding layer is disposed between the first active layer of the first transistor and the substrate.
  19. A display device comprising the display substrate according to any one of claims 12 to 18.
CN202180002777.XA 2021-09-30 2021-09-30 Thin film transistor, manufacturing method thereof, display substrate and display device Pending CN116210087A (en)

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