CN116209346A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN116209346A CN116209346A CN202310265834.4A CN202310265834A CN116209346A CN 116209346 A CN116209346 A CN 116209346A CN 202310265834 A CN202310265834 A CN 202310265834A CN 116209346 A CN116209346 A CN 116209346A
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Abstract
The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a semiconductor substrate; the bottom conductive layer, the resistance change layer and the top conductive layer are sequentially arranged on the semiconductor substrate; the first protection layer is positioned on the side wall of the top conductive layer, and the side wall of the first protection layer is flush with the side wall of the resistance change layer and the side wall of the bottom conductive layer. The application provides a semiconductor structure and a forming method thereof, wherein a first protective layer and a second protective layer are formed on the side wall of an RRAM structure, so that the RRAM structure is protected from being polluted, and the reliability of the RRAM structure can be improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Resistance change memories (Resistive Random Access Memory, RRAM) are erasable memory technologies that can significantly improve endurance and data transfer speed. RRAM is a memory that changes the resistance of a material between a high resistance state and a low resistance state according to a voltage applied to a Metal Oxide, thereby opening or blocking a current flow path, and stores various information using this property.
RRAM structures generally include top and bottom conductive layers and a resistive layer disposed between the top and bottom conductive layers. Current RRAM structures are prone to shorting between the top and bottom conductive layers due to adhesion of the bottom conductive layer material to the sidewalls during etching of the top and bottom conductive layers and the resistive layer due to back-sputtering of the bottom conductive layer material during formation. In addition, the resistive layer is also easily polluted by impurity elements in the etching process, and the resistive characteristics of the resistive layer are affected, so that the reliability of the RRAM structure is affected.
Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can improve the reliability of an RRAM structure.
One aspect of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate; sequentially forming a bottom conductive material layer, a resistance change material layer and a top conductive material layer on the semiconductor substrate; etching the top conductive material layer to the resistance change material layer to form a top conductive layer; forming a first protective layer on the side wall of the top conductive layer; and etching the resistive material layer and the bottom conductive material layer along the side wall of the first protective layer to form a resistive layer and a bottom conductive layer.
In some embodiments of the present application, a first dielectric layer is further formed on the surface of the semiconductor substrate, a first metal layer is formed in the first dielectric layer, a second dielectric layer is formed on the surface of the first dielectric layer, a first through hole structure penetrating through the second dielectric layer and electrically connected with the first metal layer is formed in the second dielectric layer, and the bottom conductive material layer, the resistive material layer and the top conductive material layer are located on the surface of the second dielectric layer and the first through hole structure, and the bottom conductive layer is electrically connected with the first through hole structure.
In some embodiments of the present application, the resistive material layer and the bottom conductive material layer are etched along the first protective layer sidewall to form a resistive layer and a bottom conductive layer that are over etched into the second dielectric layer.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming a second protective layer on the surface of the second dielectric layer, the side wall of the bottom conductive layer, the side wall of the resistance change layer, the side wall of the first protective layer and the top conductive layer.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming a third dielectric layer on the surface of the second protective layer, and forming a second through hole structure electrically connected with the top conductive layer and a second metal layer electrically connected with the second through hole structure in the third dielectric layer.
In some embodiments of the present application, the material of the first via structure includes a metal having conductive properties or a metal compound including copper, and the metal compound includes tantalum nitride or titanium nitride.
In some embodiments of the present application, a method of etching the top conductive material layer to the resistive material layer to form a top conductive layer includes: sequentially forming a hard mask layer and a patterned photoresist layer on the surface of the top conductive material layer, wherein the patterned photoresist layer defines the position of the top conductive layer; etching the hard mask layer and the top conductive material layer by taking the patterned photoresist layer as a mask to form the top conductive layer; and removing the patterned photoresist layer.
In some embodiments of the present application, the top conductive material layer is etched to the point where the resistive material layer forms a top conductive layer, over etching into the resistive material layer.
In some embodiments of the present application, a method of forming a first protective layer on sidewalls of the top conductive layer includes: forming a first protective material layer on the surface of the resistance change material layer, the top conductive layer and the side wall; and etching the first protective material layer to remove the first protective material layer positioned on the surface of the resistance change material layer and the top conductive layer, wherein the first protective material layer positioned on the side wall of the top conductive layer forms the first protective layer.
In some embodiments of the present application, the resistive layer is a multilayer stack structure.
Another aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate; the bottom conductive layer, the resistance change layer and the top conductive layer are sequentially arranged on the semiconductor substrate; the first protection layer is positioned on the side wall of the top conductive layer, and the side wall of the first protection layer is flush with the side wall of the resistance change layer and the side wall of the bottom conductive layer.
In some embodiments of the present application, the semiconductor substrate surface further includes a first dielectric layer, a first metal layer is included in the first dielectric layer, the first dielectric layer and the first metal layer surface include a second dielectric layer, the second dielectric layer includes a first via structure penetrating through the second dielectric layer and electrically connected to the first metal layer, and the bottom conductive layer, the resistive layer and the top conductive layer are located on the surfaces of the second dielectric layer and the first via structure, and the bottom conductive layer is electrically connected to the first via structure.
In some embodiments of the present application, a portion of the second dielectric layer that is located below the bottom conductive layer is higher than a portion of the second dielectric layer that is not located below the bottom conductive layer.
In some embodiments of the present application, the semiconductor structure further comprises: the second protective layer is positioned on the surface of the second dielectric layer, the side wall of the bottom conductive layer, the side wall of the resistance change layer, the side wall of the first protective layer and the top conductive layer.
In some embodiments of the present application, the semiconductor structure further comprises: the third dielectric layer is positioned on the surface of the second protective layer, and the second metal layer is positioned in the third dielectric layer and is electrically connected with the second through hole structure of the top conductive layer and the second metal layer of the second through hole structure.
In some embodiments of the present application, the material of the first via structure includes a metal having conductive properties or a metal compound including copper, and the metal compound includes tantalum nitride or titanium nitride.
In some embodiments of the present application, a portion of the resistive layer below the top conductive layer is higher than a portion of the resistive layer below the first protective layer.
In some embodiments of the present application, the resistive layer is a multilayer stack structure.
In some embodiments of the present application, the semiconductor structure further includes: and the hard mask layer is positioned on the surface of the top conductive layer.
The application provides a semiconductor structure and a forming method thereof, wherein a first protective layer and a second protective layer are formed on the side wall of an RRAM structure to protect the RRAM structure from being polluted, so that the reliability of the RRAM structure can be improved, the RRAM structure is formed by two times of etching, and the difficulty of an etching process can be reduced.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale.
Wherein:
fig. 1 to 9 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
For the problem of the RRAM structure sidewall being polluted, in some processes, a bottom conductive layer is formed in a dielectric layer independently, so that the back splash of the bottom conductive layer material is avoided. However, this process still has problems: to embed the RRAM structure into the MIM, the aspect ratio of the opening for filling the bottom conductive layer is substantially 1: about 1, magnetron sputtering is a film forming method of metal or metal compound commonly used in the traditional CMOS MIM process, and the gap filling capability is generally limited. The special film forming equipment is required to be developed, and the cost of process development is greatly increased; if the embedded technology is needed to be embedded into a higher technical node, a higher requirement on the process capability of equipment is required; in addition, there is a large Overlap (overlay) of the bottom and top conductive layers, reducing the effective area of the RRAM structure, which is detrimental to improving RRAM memory Reliability (Reliability).
For the problem that the side wall of the RRAM structure is polluted, the application provides a semiconductor structure and a forming method thereof, wherein a first protective layer and a second protective layer are formed on the side wall of the RRAM structure to protect the RRAM structure from being polluted, and the reliability of the RRAM structure can be improved.
Fig. 1 to 9 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application. The semiconductor structure described herein is, for example, a resistance change memory structure. The following describes a method for forming a semiconductor structure according to an embodiment of the present application in detail with reference to the accompanying drawings.
Referring to fig. 1, a semiconductor substrate 100 is provided, a first dielectric layer 110 is further formed on the surface of the semiconductor substrate 100, a first metal layer 111 is formed in the first dielectric layer 110, a second dielectric layer 120 is formed on the surfaces of the first dielectric layer 110 and the first metal layer 111, and a first via structure 121 penetrating through the second dielectric layer 120 and electrically connected to the first metal layer 111 is formed in the second dielectric layer 120.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. The semiconductor substrate 100 may have active devices formed therein, such as MOS transistors composed of a source, a gate, and a drain.
In some embodiments of the present application, the material of the first dielectric layer 110 is, for example, silicon oxide. The material of the first metal layer 111 is, for example, copper. The first metal layer 111 may be electrically connected to active devices in the semiconductor substrate.
In some embodiments of the present application, the material of the second dielectric layer 120 is, for example, nitrogen doped silicon carbide (NDC). The material of the first via structure 121 includes a metal having conductive properties including copper or tungsten or a metal compound including tantalum nitride or titanium nitride.
Referring to fig. 2, a bottom conductive material layer 130a, a resistive material layer 140a, and a top conductive material layer 150a are sequentially formed on the semiconductor substrate 100 (specifically, on the surfaces of the second dielectric layer 120 and the first via structure 121).
In some embodiments of the present application, the methods of forming the bottom conductive material layer 130a, the resistive material layer 140a, and the top conductive material layer 150a include a chemical vapor deposition process, a physical vapor deposition process, or the like.
Referring to fig. 3, 4 and 5, the top conductive material layer 150a to the resistive material layer 140a are etched to form a top conductive layer 150.
Referring to fig. 3, a hard mask layer 160 and a patterned photoresist layer 161 are sequentially formed on the surface of the top conductive material layer 150a, and the patterned photoresist layer 161 defines the position of the top conductive layer 150.
In some embodiments of the present application, the material of the hard mask layer 160 is, for example, silicon nitride.
Referring to fig. 4, the hard mask layer 160 and the top conductive material layer 150a are etched using the patterned photoresist layer 161 as a mask to form the top conductive layer 150.
In some embodiments of the present application, the hard mask layer 160 and the top conductive material layer 150a may be etched once using the patterned photoresist layer 161 as a mask. In other embodiments of the present application, the patterned photoresist layer 161 may be used as a mask to etch the hard mask layer 160, and then the patterned photoresist layer 161 and the hard mask layer 160 may be used as masks to etch the top conductive material layer 150a.
Referring to fig. 5, the patterned photoresist layer 161 is removed.
In some embodiments of the present application, the step of removing the patterned photoresist layer 161 may be performed before etching the top conductive layer or after etching the top conductive layer, and the order of removing the patterned photoresist layer 161 is not limited in this application.
In some embodiments of the present application, the hard mask layer 160 may remain or may be removed.
In some embodiments of the present application, the top conductive material layer 150a to the resistive material layer 140a is etched to form the top conductive layer 150 over-etched into the resistive material layer 140 a. I.e., a portion of the resistive material layer 140a is also etched, so that a subsequently formed first protective layer may be ensured to completely cover the sidewalls of the top conductive layer 150.
In some embodiments of the present application, the material of the top conductive layer 150 includes a metal or metal compound having conductive properties, such as copper, tantalum nitride, or titanium nitride, etc.
In a conventional process, the top conductive layer, the resistive layer, and the bottom conductive layer are formed by etching the top conductive material layer 150a, the resistive material layer 140a, and the bottom conductive material layer 130a only once. Therefore, the back splash of the bottom conductive material is easy to adhere to the top conductive layer, the resistive layer and the side wall of the bottom conductive layer in the etching process, so that the top conductive layer and the bottom conductive layer are short-circuited, substances (especially substances containing nitrogen and oxygen) in the etching process such as etching gas or etching reaction byproducts are easy to pollute the top conductive layer, the resistive layer and the side wall of the bottom conductive layer, so that the top conductive layer, the resistive layer and the side wall of the bottom conductive layer are denatured, and the resistive performance of the resistive layer is especially affected. In the technical scheme of the application, the top conductive layer 150 is formed by etching, and then the protective layer is formed on the side wall of the top conductive layer 150 to protect the top conductive layer 150, so that the top conductive layer 150 is prevented from being polluted, and the short circuit between the top conductive layer 150 and the bottom conductive layer is prevented. In addition, the RRAM structure is formed by two times of etching, so that the difficulty of the etching process can be reduced.
Referring to fig. 6, a first protective layer 171 is formed on the sidewalls of the top conductive layer 150 and the sidewalls of the hard mask layer 160 and the sidewalls of the resistive material layer 140a under the top conductive layer 150 after the resistive material layer 140a is over etched. The first protective layer 171 may protect the top conductive layer 150.
In some embodiments of the present application, the material of the first protective layer 171 includes silicon oxide or silicon nitride, etc. The first protective layer 171 is formed by a chemical vapor deposition process or an atomic layer deposition process with good conformality.
In some embodiments of the present application, the method for forming the first protective layer 171 on the sidewall of the top conductive layer 150 includes: forming a first protective material layer on the surface of the resistive material layer 140a, on the top conductive layer 150 (specifically, on the surface of the hard mask layer 160) and on the sidewalls; and etching the first protective material layer to remove the first protective material layer positioned on the surface of the resistance change material layer and the top conductive layer, wherein the first protective material layer positioned on the side wall of the top conductive layer forms the first protective layer.
Referring to fig. 7, the resistive material layer 140a and the bottom conductive material layer 130a are etched along sidewalls of the first protective layer 171 to form the resistive material layer 140 and the bottom conductive layer 130. The top conductive layer 150 and the bottom conductive layer 130 are not shorted due to the protective effect of the first protective layer 160. Wherein the top conductive layer 150, the resistive layer 140, and the bottom conductive layer 130 form an RRAM structure.
In some embodiments of the present application, the resistive material layer 140a and the bottom conductive material layer 130a are etched along the sidewalls of the first protective layer 171 to form the resistive layer 140 and the bottom conductive layer 130 that are over-etched into the second dielectric layer 120. I.e., a portion of the second dielectric layer 120 is also etched, so that a second protective layer formed later can be ensured to completely cover the sidewalls of the bottom conductive layer 130.
In some embodiments of the present application, the material of the resistive layer 140 includes a functional material having memristive properties including HfO 2 、Ta 2 O 5 、WO 2 。
In some embodiments of the present application, the resistive layer 140 is a multi-layer stack structure. For example, the resistive layer 140 may include stacked first, second, third resistive layers, and the like. The materials of the first, second and third resistive layers may be the same or different. The materials of the first, second and third resistive layers comprise HfO 2 、Ta 2 O 5 、WO 2 Etc.
In some embodiments of the present application, the material of the bottom conductive layer 130 includes a metal or a metal compound having conductive properties, such as copper, tantalum nitride, or titanium nitride.
In some embodiments of the present application, the bottom conductive layer 130 and the first via structure 121 are electrically connected. The projection of the bottom conductive layer 130 in the vertical direction completely covers the projection of the first via structure 121 in the vertical direction.
Referring to fig. 8, a second protective layer 172 is formed on the surface of the second dielectric layer 120, the sidewall of the bottom conductive layer 130, the sidewall of the resistive layer 140, the sidewall of the first protective layer 171, and the top conductive layer 150 (specifically, the surface of the hard mask layer 160). The second protective layer 172 may protect the resistive layer 140 and the bottom conductive layer 130. The second protection layer 172 may protect the resistive layer 140 from being contaminated, thereby ensuring that the resistive characteristics of the resistive layer 140 are not affected, and improving the stability of the device.
In some embodiments of the present application, the material of the second protective layer 172 includes silicon oxide or silicon nitride, etc. The second protective layer 172 is formed by a chemical vapor deposition process or an atomic layer deposition process with good conformality.
Referring to fig. 9, a third dielectric layer 180 is formed on the surface of the second protective layer 172, and a second via structure 181 electrically connected to the top conductive layer 150 and a second metal layer 182 electrically connected to the second via structure 181 are formed in the third dielectric layer 180.
In some embodiments of the present application, the material of the third dielectric layer 180 is, for example, silicon oxide. The material of the second metal layer 182 is, for example, copper. The material of the second via structure 181 includes copper.
The first metal layer 111 and the first via structure 121, and the second metal layer 182 and the second via structure 181 are respectively any two-layer metal interconnection structures in the back-end process on the semiconductor substrate 100.
The application provides a method for forming a semiconductor structure, wherein a first protective layer and a second protective layer are formed on the side wall of an RRAM structure, so that the RRAM structure is protected from being polluted, and the reliability of the RRAM structure can be improved.
Embodiments of the present application also provide a semiconductor structure, as shown with reference to fig. 9, including: a semiconductor substrate 100; a bottom conductive layer 130, a resistive layer 140, and a top conductive layer 150 sequentially on the semiconductor substrate 100; the first protection layer 160 is located on the side wall of the top conductive layer 150, and the side wall of the first protection layer 160 is flush with the side walls of the resistive layer 140 and the bottom conductive layer 130.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. The semiconductor substrate 100 may have active devices formed therein, such as MOS transistors composed of a source, a gate, and a drain.
In some embodiments of the present application, the surface of the semiconductor substrate 100 further includes a first dielectric layer 110, the first dielectric layer 110 includes a first metal layer 111, the first dielectric layer 110 and the surface of the first metal layer 111 include a second dielectric layer 120, the second dielectric layer 120 includes a first via structure 121 penetrating through the second dielectric layer 120 and electrically connected to the first metal layer 111, the bottom conductive layer 130, the resistive layer 140 and the top conductive layer 150 are located on the surfaces of the second dielectric layer 120 and the first via structure 121, the bottom conductive layer 130 and the first via structure 111 are electrically connected, and the projection of the bottom conductive layer 130 in the vertical direction completely covers the projection of the first via structure 121 in the vertical direction.
In some embodiments of the present application, the material of the first dielectric layer 110 is, for example, silicon oxide. The material of the first metal layer 111 is, for example, copper.
In some embodiments of the present application, the material of the second dielectric layer 120 is, for example, nitrogen doped silicon carbide (NDC). The material of the first via structure 121 includes a metal having conductive properties including copper or tungsten or a metal compound including tantalum nitride or titanium nitride.
With continued reference to fig. 9, a bottom conductive layer 130, a resistive layer 140, and a top conductive layer 150 are sequentially formed on the semiconductor substrate 100 (specifically, on the surfaces of the second dielectric layer 120 and the first via structure 121). The top conductive layer 150, the resistive layer 140, and the bottom conductive layer 130 constitute an RRAM structure.
In some embodiments of the present application, a hard mask layer 160 is further formed on the surface of the top conductive layer 150. In some embodiments of the present application, the material of the hard mask layer 160 is, for example, silicon nitride.
In some embodiments of the present application, the material of the bottom conductive layer 130 includes a metal or a metal compound having conductive properties, such as copper, tantalum nitride, or titanium nitride.
In some embodiments of the present application, the material of the resistive layer 140 includes a functional material having memristive properties including HfO 2 、Ta 2 O 5 、WO 2 。
In some embodiments of the present application, the resistive layer 140 is a multi-layer stack structure. For example, the resistive layer 140 may include stacked first, second, third resistive layers, and the like. The first and second resistive layersThe material of the third resistive layer may be the same or different. The materials of the first, second and third resistive layers comprise HfO 2 、Ta 2 O 5 、WO 2 Etc.
In some embodiments of the present application, the material of the top conductive layer 150 includes a metal or metal compound having conductive properties, such as copper, tantalum nitride, or titanium nitride, etc.
In some embodiments of the present application, the portion of the second dielectric layer 120 that is located below the bottom conductive layer 130 is higher than the portion of the second dielectric layer 120 that is not located below the bottom conductive layer 130. The second protective layer 172 may thus completely cover the bottom conductive layer 130, thereby improving the protection effect.
In some embodiments of the present application, the portion of the resistive layer 140 under the top conductive layer 150 is higher than the portion of the resistive layer 140 under the first protective layer 171. This ensures that the first protective layer 171 completely covers the sidewalls of the top conductive layer 150.
With continued reference to fig. 9, a first protective layer 171 is formed on the sidewalls of the top conductive layer 150 and the hard mask layer 160 and on a portion of the sidewalls of the resistive layer 140. The first protective layer 171 may protect the top conductive layer 150.
In some embodiments of the present application, the material of the first protective layer 171 includes silicon oxide or silicon nitride, etc.
With continued reference to fig. 9, a second protective layer 172 is formed on the surface of the second dielectric layer 120, the sidewall of the bottom conductive layer 130, the sidewall of the resistive layer 140, the sidewall of the first protective layer 171, and the top conductive layer 150 (specifically, the surface of the hard mask layer 160). The second protective layer 172 may protect the resistive layer 140 and the bottom conductive layer 130.
In some embodiments of the present application, the material of the second protective layer 172 includes silicon oxide or silicon nitride, etc.
In the conventional structure, the first protective layer 171 and the second protective layer 172 are not provided, so that the top conductive layer 150 and the bottom conductive layer 130 are easily shorted, and the sidewalls of the top conductive layer 150, the resistive layer 140, and the bottom conductive layer 130 are easily contaminated and denatured, particularly affecting the resistive properties of the resistive layer 140. In the technical solution of the present application, the sidewalls of the top conductive layer 150, the resistive layer 140 and the bottom conductive layer 130 are formed with the first protective layer 171 and the second protective layer 172, so that the top conductive layer 150 and the bottom conductive layer 130 can be prevented from being shorted, and the resistive layer 140 is prevented from being polluted.
With continued reference to fig. 9, a third dielectric layer 180 is formed on the surface of the second protective layer 172, and a second via structure 181 electrically connected to the top conductive layer 150 and a second metal layer 182 electrically connected to the second via structure 181 are formed in the third dielectric layer 180.
In some embodiments of the present application, the material of the third dielectric layer 180 is, for example, silicon oxide. The material of the second metal layer 182 is, for example, copper. The material of the second via structure 181 includes copper.
The first metal layer 111 and the first via structure 121, and the second metal layer 182 and the second via structure 181 are respectively any two-layer metal interconnection structures in the back-end process on the semiconductor substrate 100.
The application provides a semiconductor structure and a forming method thereof, wherein a first protective layer and a second protective layer are formed on the side wall of an RRAM structure, so that the RRAM structure is protected from being polluted, and the reliability of the RRAM structure can be improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate;
sequentially forming a bottom conductive material layer, a resistance change material layer and a top conductive material layer on the semiconductor substrate;
etching the top conductive material layer to the resistance change material layer to form a top conductive layer;
forming a first protective layer on the side wall of the top conductive layer;
and etching the resistive material layer and the bottom conductive material layer along the side wall of the first protective layer to form a resistive layer and a bottom conductive layer.
2. The method of forming a semiconductor structure of claim 1, wherein a first dielectric layer is further formed on a surface of the semiconductor substrate, a first metal layer is formed in the first dielectric layer, a second dielectric layer is formed on a surface of the first dielectric layer and the first metal layer, a first via structure penetrating the second dielectric layer and electrically connected to the first metal layer is formed in the second dielectric layer, and the bottom conductive material layer, the resistive material layer, and the top conductive material layer are located on a surface of the second dielectric layer and the first via structure, and the bottom conductive layer is electrically connected to the first via structure.
3. The method of claim 2, wherein the resist material layer and the bottom conductive material layer are etched along the first protective layer sidewall over-etched into the second dielectric layer when forming a resist layer and a bottom conductive layer.
4. The method of forming a semiconductor structure of claim 2, further comprising: and forming a second protective layer on the surface of the second dielectric layer, the side wall of the bottom conductive layer, the side wall of the resistance change layer, the side wall of the first protective layer and the top conductive layer.
5. The method of forming a semiconductor structure of claim 4, further comprising: and forming a third dielectric layer on the surface of the second protective layer, and forming a second through hole structure electrically connected with the top conductive layer and a second metal layer electrically connected with the second through hole structure in the third dielectric layer.
6. The method of forming a semiconductor structure of claim 2, wherein the material of the first via structure comprises a metal having conductive properties or a metal compound comprising copper, the metal compound comprising tantalum nitride or titanium nitride.
7. The method of forming a semiconductor structure of claim 1, wherein etching the top conductive material layer to the resistive material layer to form a top conductive layer comprises:
sequentially forming a hard mask layer and a patterned photoresist layer on the surface of the top conductive material layer, wherein the patterned photoresist layer defines the position of the top conductive layer;
etching the hard mask layer and the top conductive material layer by taking the patterned photoresist layer as a mask to form the top conductive layer;
and removing the patterned photoresist layer.
8. The method of claim 1, wherein the top conductive material layer is etched to the point where the resistive material layer forms a top conductive layer, and is over etched into the resistive material layer.
9. The method of forming a semiconductor structure of claim 1, wherein forming a first protective layer on sidewalls of the top conductive layer comprises:
forming a first protective material layer on the surface of the resistance change material layer, the top conductive layer and the side wall;
and etching the first protective material layer to remove the first protective material layer positioned on the surface of the resistance change material layer and the top conductive layer, wherein the first protective material layer positioned on the side wall of the top conductive layer forms the first protective layer.
10. The method of forming a semiconductor structure of claim 10, wherein the resistive layer is a multi-layer stack structure.
11. A semiconductor structure, comprising:
a semiconductor substrate;
the bottom conductive layer, the resistance change layer and the top conductive layer are sequentially arranged on the semiconductor substrate;
the first protection layer is positioned on the side wall of the top conductive layer, and the side wall of the first protection layer is flush with the side wall of the resistance change layer and the side wall of the bottom conductive layer.
12. The semiconductor structure of claim 11, wherein the semiconductor substrate surface further comprises a first dielectric layer comprising a first metal layer therein, the first dielectric layer and the first metal layer surface comprising a second dielectric layer comprising a first via structure therethrough and electrically connected to the first metal layer, the bottom conductive layer, the resistive layer, and the top conductive layer being located on the second dielectric layer and the first via structure surface, the bottom conductive layer and the first via structure being electrically connected.
13. The semiconductor structure of claim 11, wherein a portion of the second dielectric layer that is located below the bottom conductive layer is higher than a portion of the second dielectric layer that is not located below the bottom conductive layer.
14. The semiconductor structure of claim 11, further comprising: the second protective layer is positioned on the surface of the second dielectric layer, the side wall of the bottom conductive layer, the side wall of the resistance change layer, the side wall of the first protective layer and the top conductive layer.
15. The semiconductor structure of claim 14, further comprising: the third dielectric layer is positioned on the surface of the second protective layer, and the second metal layer is positioned in the third dielectric layer and is electrically connected with the second through hole structure of the top conductive layer and the second metal layer of the second through hole structure.
16. The semiconductor structure of claim 12, wherein the material of the first via structure comprises a metal or a metal compound having conductive properties, the metal comprising copper, the metal compound comprising tantalum nitride or titanium nitride.
17. The semiconductor structure of claim 11, wherein a portion of the resistive layer under the top conductive layer is higher than a portion of the resistive layer under the first protective layer.
18. The semiconductor structure of claim 17, wherein the resistive layer is a multi-layer stack structure.
19. The semiconductor structure of claim 11, further comprising: and the hard mask layer is positioned on the surface of the top conductive layer.
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