CN116208731A

CN116208731A - PCIe cascade network port high-speed transmission method and system based on Zynq architecture

Info

Publication number: CN116208731A
Application number: CN202310146467.6A
Authority: CN
Inventors: 段瑞枫; 陈艳; 张就
Original assignee: Beijing Forestry University
Current assignee: Beijing Forestry University
Priority date: 2023-02-08
Filing date: 2023-02-08
Publication date: 2023-06-02

Abstract

The invention relates to a PCIe cascade network port high-speed transmission method and system based on Zynq architecture, wherein the method comprises the following steps: the Zynq board is electrically connected with the host through a PCIe protocol interface, wherein the Zynq board comprises PS and PL; PCIe data is written into an XDMAIP core, and the XDMA IP core opens a first data channel and a second data channel; when the PCIe data is transmitted in the first data channel or the second data channel, write request information is automatically generated and cached in the DDR; wherein the write request information includes: data length, data source address, and data destination address; based on the write request information, PCIe data between the host and the Zynq board completes high-speed transmission through the first data channel and the first data channel. The invention realizes a transmission channel based on a PCIe high-speed communication interface by means of the programmable characteristic of hardware on the basis of a Zynq platform, and completes the transmission of video data between a host and an FPGA.

Description

PCIe cascade network port high-speed transmission method and system based on Zynq architecture

Technical Field

The invention relates to the technical field of computers, in particular to a PCIe cascade network port high-speed transmission method and system based on a Zynq architecture.

Background

With the proliferation of network data, the amount of rich text, especially images and video, that needs to be processed increases exponentially. However, the conventional central processing unit (central processing unit, CPU) and graphics processing unit (graphics processing unit, GPU) architecture widely used currently has the defects of high energy consumption and low cost performance, and the transmission and processing of image video data are increasingly becoming research hot spots from a host to a FPGA (Field Programming Gate Array) hardware board card.

In the prior art, after network data is received by a network card, the data is generally directly delivered to a host CPU, and the host CPU performs data unpacking operation; similarly, for the reverse data flow, the host CPU performs the encapsulation operation, and then forwards the data frame with the packet header of each layer to the network card. In the whole process, a host CPU participates in the encapsulation and decapsulation operation of network data in the whole process, and the mode greatly increases the burden of the host.

Disclosure of Invention

According to the problems in the prior art, the invention provides a PCIe cascade port high-speed transmission method and system based on a Zynq architecture, which realize a transmission path based on a PCIe high-speed communication interface by means of hardware programmable characteristics on the basis of a Zynq platform and finish data transmission between a host and an FPGA board.

The technical scheme of the invention is as follows:

in a first aspect, the present disclosure provides a PCIe cascaded network port high-speed transmission method based on Zynq architecture, including:

the Zynq board is electrically connected with the host through a PCIe protocol interface, wherein the Zynq board comprises PS and PL;

PCIe data is written into an XDMA IP core, and the XDMA IP core opens a first data channel and a second data channel;

when PCIe data is transmitted in the first data channel or the second data channel, write request information is automatically generated and cached in the DDR;

wherein the write request information includes: data length, data source address, and data destination address;

based on the write request information, PCIe data between the host and the Zynq board completes high-speed transmission through the first data channel and the first data channel.

As a preferable technical scheme, the system further comprises a PCIe receiving module, wherein the first data channel is a H2C_0 channel;

based on the write request, the PCIe receive module writes PCIe data into the DDR through the h2c_0 lane.

As a preferable technical scheme, the system further comprises a PCIe sending module, and the second channel is a C2H_0 channel;

based on the write request, the PCIe sending module reads PCIe data cached in the DDR and carries the PCIe data into the XDMA IP core so that the XDMA IP core transmits the PCIe data to a data destination address through a C2H_0 channel;

wherein, the data destination address is a host or a Zynq board.

As a preferred technical scheme, the ethernet port receives PCIe data;

PCIe data is transmitted to the PS, the PS performs unpacking processing on the PCIe data and then buffers the unpacked PCIe data in the DDR, and the PCIe data is transported to the host based on the XDMA IP core.

As an optimal technical scheme, PCIe data in a data destination address is carried to PL through XDMA IP core, and the PCIe data is cached in DDR;

and the PCIe data are transmitted to the PS through the AXI bus, and the PS packages the PCIe data and sends the PCIe data to the external network equipment.

As a preferable technical scheme, after finishing writing and reading data to be transmitted, the DMA sends a channel clearing request to the PS;

based on the channel clear request, the driver erases the first data channel and the second data channel.

In a second aspect, the present disclosure provides a system for the PCIe cascaded network port high-speed transmission method based on Zynq architecture, including:

a host;

the Zynq board is provided with a PCIe protocol interface which is electrically connected with the host; the Zynq board comprises a PS unit and a PL unit, which correspond to the CPU board and the FPGA board respectively, and the FPGA board is provided with an XDMA IP core; the PCIe protocol interface verifies high-speed network data transfer based on the XDMA IP.

As the preferable technical scheme, the host also comprises a PCIe switch chip, and the Zynq board and the plurality of PCIe devices are electrically connected with the PCIe switch chip.

In a third aspect, the present specification provides an electronic device comprising:

at least one processor;

and a memory storing a computer program executable in the processor, the processor executing any one of the above transmission methods when executing the program.

In a fourth aspect, the present description provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, is a transmission method as defined above.

The technical scheme adopted by the invention has the beneficial effects that: based on the Zynq platform, a transmission channel based on a PCIe high-speed communication interface is realized by means of the programmable characteristic of hardware, the transmission of video data between a host and an FPGA is completed, namely, the characteristic that an XDMA IP core can open two independent channels at most is utilized, and the data is transmitted between a DMA register and MM (AXI Memory Map) by fully utilizing C2H_0 and H2C_0, and as the encapsulation and the deblocking of network data are completed on the Zynq board, the work load of a CPU of the host is effectively reduced; the PS is also designed to perform encapsulation and decapsulation of an Ethernet application layer on the video data and Ethernet transmission of the video data, and simultaneously, the function of expanding the network port as required is also added.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments are briefly described below to form a part of the present invention, and the exemplary embodiments of the present invention and the description thereof illustrate the present invention and do not constitute undue limitations of the present invention. In the drawings:

fig. 1 is a flowchart of a PCIe cascaded network port high-speed transmission method based on a Zynq architecture according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a PCIe cascaded network port high-speed transmission system based on a Zynq architecture according to an embodiment of the present invention;

FIG. 3 is a diagram of actual test results of PCIe 2.0x2 transmission rate provided by one embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. In the description of the present invention, it should be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Examples

According to fig. 1, the present disclosure provides a PCIe hierarchical port high-speed transmission method based on Zynq architecture, including:

the Zynq board is electrically connected with the host through a PCIe protocol interface, wherein the Zynq board comprises PS and PL; PL refers to a programmable logic array and PS refers to an ARM processor; preferably, the PCIe protocol interface is selected to be the PCIe 2.0 protocol.

PCIe data is written to the XDMA IP core, which opens the first data channel and the second data channel.

wherein the write request information includes: data length, data source address, and data destination address.

According to the method and system for PCIe cascade network port high-speed transmission based on Zynq architecture, the problem that the host is easily burdened is solved according to the fact that the existing host participates in the encapsulation and decapsulation operation of network data in the whole course, the solution is packet transmission, and optimization aiming at DDR cache modules is mainly channel independent and packet transmission operation. By utilizing the characteristic that the XDMA IP core can open two independent channels at most, the data is transmitted between the DMA register and MM (AXI Memory Map) by fully utilizing the C2H_0 and the H2C_0, and the encapsulation and the decapsulation of the network data are completed on the Zynq board, so that the load of a CPU is greatly reduced.

In one embodiment of the invention, the PS is designed to perform encapsulation and decapsulation of an Ethernet application layer on the video data and Ethernet transmission on the video data, and meanwhile, the function of expanding the network port according to the requirement is added. The data processing of the traditional network packet is moved downwards from the CPU to the hardware board card, so that the application capability of the processor in the field of network video receiving and transmitting can be effectively improved.

Preferably, DDR is a DDR3 register. In one embodiment of the invention, the parameters set by the DDR3 register for the MIG IP core are: the reference clock is 200Mhz, the operating frequency is 800Mhz, and the data bus is 32 bits. The single channel can only realize the transmission of one path of video data by means of C2H_0 and H2C_0, and once a plurality of paths of video data sources arrive, queuing is needed to wait, so that unacceptable delay is caused; meanwhile, for network packets with larger load, the direct transmission inevitably causes data loss or data congestion. The solution adopted in this specification is packet transmission. The optimization for the DDR3 cache module is mainly channel independent and packet transfer operations.

Specifically, the characteristic that the XDMA IP core can open up to two independent channels is utilized, and data is transferred between the DMA registers and MM (AXI Memory Map) by fully utilizing c2h_0 and h2c_0. Cfg Master (AXI 4-Lite Master) is a fixed 32-bit port for host access to user configuration and status registers; cfg Master (AXI 4-Lite Slave) may be used for user logic to access the internal configuration and status registers of the DMA subsystem; the Host DMAPBypass (AXI MM Master) port is the same width as the DMA channel data path and is intended for high bandwidth access of user memory that may be required in peer-to-peer applications (e.g., peer-to-peer transfers). When the data transmission from the FPGA board end to the host is carried out, the C2H control register is firstly written in to trigger and start the C2H transmission. Upon receiving PCIe data, the C2H channel generates a write request, the handle consisting essentially of a source address, which is the CPU board, a destination address, which is the host, and a data length. The C2H descriptor start address is written into a register, and the DMA obtains data according to the source address in the DDR and sends the data to the host destination address.

In one embodiment of the invention, the XDMA IP core consists essentially of control of DMA data flows and parsing of PCIe protocols. The DMA data stream includes two data streams, one is an H2C (host to card) data stream and the other is a C2H (card to host) data stream. The PCIe receiving module is in charge of receiving the stream data of the H2C channel and writing the data into the DDR3 cache module; the PCIe sending module is responsible for reading out video data from the on-board cache slice DDR3 and then sending the data to the XDMAIP core through the C2H channel.

For implementing PCIe interfaces on Zynq, xilinx corporation provides three PCIe interface implementation technologies, which are respectively:

the 7-series IP hard core is the most basic and most native, exposes more internal structures, such as a data receiving and transmitting engine, to a developer, has fewer functions compared with the following two technologies, and has larger secondary development difficulty and more complex workload for users.

AXI Memory Mapped To PCI Express IP core, which is to further encapsulate the above hard core, and the user can directly open the Example Design generation instance in the development software VIVADA to directly run; but a DMAIP core is also required if a DMA transfer of large data volumes is to be achieved.

The DMA/Bridge Subsystem for PCI Express (PCIe) IP core, abbreviated XDMA, encapsulates the 7-series integrated PCIe hard core with the DMAIP core, and allows users to run directly using the Example Design.

In summary, the XDMAIP core has the most abundant functions and is most convenient to develop secondarily, so that the system of the specification adopts the XDMA IP core.

After the data transfer is completed, the H2C and C2H status registers are completely cleared by the driver, disabling the DMA transfer and considering whether the next data transfer is performed.

According to fig. 2, the present disclosure provides a PCIe hierarchical port high-speed transmission system based on Zynq architecture, including:

a host;

the Zynq board is provided with a PCIe protocol interface which is electrically connected with the host; the Zynq board comprises a PS unit and a PL unit, which correspond to the CPU board and the FPGA board respectively, and the FPGA board is provided with an XDMA IP core; the PCIe protocol interface implements high-speed network data transmission based on the XDMAIP core.

The specification discloses a PCIe cascade port high-speed transmission system based on Zynq architecture. Taking video data as an example, after the data is received by a network port, the data is delivered to a PS part for data unpacking operation, then the analyzed payload part is cached by DDR, transported by XDMAIP and delivered to an upper computer, and directly played by a video player; on the contrary, the reverse data flow sends payload data from the upper computer, is transported to the PL part by XDMAIP, is buffered by DDR, is delivered to PS for data encapsulation operation, and is forwarded to the peripheral equipment by the network port.

In one embodiment of the present invention, the backplane of the Zynq board in this specification is a piece of Xilinx Kintex-7 Zynq XC7Z 030-FFG676-2 FPGA, which backplane supports modular design and dynamic reconfigurable configuration, which can provide fast computation and efficient storage for video processing applications. The 1 x2 PCIe Gen2 high-speed data transmission interfaces are carried on the board, other devices with PCIe interfaces are supported to be connected, and the whole board card can also be used as PCIe devices to run in a host. On-board 2 DDR3 with the size of 1GB and the bandwidth of 1600MHz support the reading and writing of a large amount of video and image data. And the on-board 3-path gigabit Ethernet port supports high-speed configurable network communication. PCIe-based high-speed data communication interfaces can provide powerful support for high-speed transmission and processing of large amounts of video data.

In one embodiment of the invention, the CPU board is provided with a plurality of PCIe physical interfaces for connecting PCIe board card devices inserted therein, and further comprises storage resources, IO resources, a GPU and PCIe switch chips for expanding the quantity of PCIe interfaces. Preferably, the PCIe switch chip has an upstream bus connected to the CPU board and a downstream bus connected to a plurality of terminal devices, see fig. 2. In a preferred embodiment, the CPU motherboard uses Ubuntu 16.04 operating system, preloaded with Zynq board, PCIe Switch chip driver.

Preferably, the PCIe IP core selects version 2.0, x2 communication links, and theoretical communication bandwidth is 1GB/s at maximum.

Preferably, the PCIe 2.0 protocol selects an 8b/10b encoding scheme.

Preferably, PCIe transmit bandwidth may reach 816MB/s and receive bandwidth may be up to 574MB/s.

In one embodiment of the present invention, according to the overall hardware interconnection structure of the system of fig. 2, the main board of the host computer is equipped with a PCIe physical interface, which can be connected to PCIe devices, including PCIe Switch chips, PCIe network cards, and other IO resources. PCIe Switch chips can extend one PCIe interface on a motherboard to multiple PCIe interfaces, with CPUs connected upstream and multiple PCIe devices of different types connected downstream, such as MZ7030FA development boards used in this specification. The network video encapsulation and decapsulation processing and PCIe data transmission program are realized by a Zynq board card, and video playing is realized by calling VLC by a Shell script program. The CPU main board adopts Ubuntu 22.04 operating system, and is preloaded with Zynq board card and PCIe Switch chip driver.

In an actual application scene, before the system is powered on, downloading a hardware logic program to a development board; after the system is powered on, the operating system starts and loads a PCIe driver, then detects terminal equipment connected to a PCIe bus, identifies an MZ7030FA development board, and can directly access based on a memory address and call VLC to play video data once the transmission of a PS end network data source is started.

In one embodiment of the invention, the design scheme of the data rapid processing system is introduced sequentially according to the unidirectional flow direction of the data, and the Ethernet module reads the data of the network port from the PS end by the C program on the ARM after receiving the data of the network port from the PS end, and performs the data packet decapsulation operation to obtain the data of the payload part to be temporarily stored in the DDR. And data interaction is performed between ARM and FPGA in the Zynq board card through DDR3, then the load is read through the control module and transmitted to PCIe, and the payload data is read directly by an upper computer.

In one embodiment of the invention, the high-speed data transmission structure between the PCIe interface and the host computer is realized by connecting the CPU with the MZ7030FA development board through the PCIe interface on the main board. Based on Ubuntu 22.04 operating system, the host on the CPU side is provided with PCIe drive and API running environment corresponding to the development board, and plays video data through VLC. The MZ7030FA development board designs a PCIe transmission module and a control module. The PCIe transmission module is realized based on the XDMAIP core, the highest X2 interface speed of the PCIe second generation is 1GB/s, the average use speed can reach about 70%, and the data transmission speed requirement under the agricultural monitoring scene is met. On one hand, the transmission module receives PCIe data sent by a host, wherein the PCIe data comprises a PCIe related packet header and a data payload part, and the PCIe data is temporarily stored to the DDR through the control module; on the other hand, the data is returned to the host computer through the PCIe transmission module according to the set path, and the host computer completes the video playing function. The control module provides starting control signals required by the PCIe transmission module and data carrying between PCIe and DDR, and ensures the stable operation of the system.

In one embodiment of the invention, the connection logic of the XDMAIP core is: the MIG core is mainly divided into user interface modules, and interfaces for interacting with user logic are mainly realized; a memory controller module that receives requests from the user interface module and stores them in a logical queue, which may request reordering to optimize system throughput and latency; the physical layer module provides control DDR3 and DDR2 interfaces and can calibrate static and dynamic delays of a system in a write path or a read path. The figure specifically shows the logical relationship of the XDMA IP core to other IP core connections, the XDMA IP is connected to MIG-7 through an arbiter, thereby reading the content of the PL DDR and uploading to the upper computer.

In an actual application scene, the system is generally a host provided with an Ubuntu 22.04 operating system, a main board of the host is provided with a slot of PCIe 2.0x2, and a Zynq MZ7030FA development board is provided. The development environment of Zynq MZ7030FA is Vivado 2019.1, and PCIe transmission test and video processing function test are performed on the basis of the development environment.

According to the actual test result of pcie 2.0x2 transmission rate in fig. 3, considering that the Zynq module consumes a certain time when performing channel switching, data will not be transmitted in this time, so the actual test result fails to reach 1GB/s. As can be seen from the figure, the amount of data transmitted is relatively small, the transmission rate is also low, and the transmission rate increases with the increase of the amount of data. The actual measured PCIe transmit rate is 816MB/s and the receive rate is 574MB/s. The video files used in the system in the test are stored on the mechanical hard disk, the sequential reading speed is larger than the sequential writing speed due to the limitation of the read-write speed of the mechanical hard disk, the test result is affected to a certain extent, the PCIe sending speed of the actual test is higher than the receiving speed, and if the solid state hard disk is adopted for the test, the speed is larger than the current test result. Meanwhile, the transmission process also comprises register state information reading and writing, so that the test reading and writing speed is lower than the theoretical speed. While there are a variety of factors that affect the transmission rate, the system can meet the data transmission needs of most video processing applications.

The present specification provides an electronic apparatus including:

at least one processor;

The present specification provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs a transmission method as any one of the above.

The above describes in detail a PCIe cascaded network port high-speed transmission method and system based on Zynq architecture in the embodiments of the present application, and specific examples are applied herein to describe the principles and implementations of the present application, where the description of the above embodiments is only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A PCIe cascade network port high-speed transmission method based on Zynq architecture is characterized by comprising the following steps:

when the PCIe data is transmitted in the first data channel or the second data channel, write request information is automatically generated and cached in the DDR;

2. The method of claim 1, further comprising a PCIe receive module, the first data lane being a h2c_0 lane;

based on the write request, the PCIe receive module writes the PCIe data into the DDR through the h2c_0 lane.

3. The method of claim 2, further comprising a PCIe transmit module, the second lane being a c2h_0 lane;

based on the write request, the PCIe sending module reads the PCIe data cached in the DDR and carries the PCIe data into the XDMA IP core so that the XDMA IP core transmits the PCIe data to the data destination address through the C2H_0 channel;

wherein, the data destination address is the host or the Zynq board.

4. A method according to claim 3, comprising:

an Ethernet port receives the PCIe data;

and the PCIe data is transmitted to the PS, the PS performs decapsulation processing on the PCIe data and then caches the PCIe data in the DDR, and the PCIe data is transported to the host based on the XDMAIP core.

5. A method according to claim 3, comprising:

carrying the PCIe data in the data destination address to the PL through the XDMAIP core, and caching the PCIe data in the DDR;

and the PCIe data are transmitted to the PS through an AXI bus, and the PS packages the PCIe data and sends the packaged PCIe data to external network equipment.

6. The method of any one of claims 1-5, further comprising:

after the DMA finishes writing and reading the data to be transmitted, a channel clearing request is sent to the PS;

based on the channel clear request, a driver erases the first data channel and the second data channel.

7. A system for the Zynq architecture-based PCIe cascaded network port high speed transmission method of any one of claims 1-6, comprising:

a host;

the Zynq board is provided with a PCIe protocol interface, and the PCIe protocol interface is electrically connected with the host; the Zynq board comprises a PS unit and a PL unit, which correspond to the CPU board and the FPGA board respectively, and the FPGA board is provided with an XDMAIP core; the PCIe protocol interface realizes high-speed network data transmission based on the XDMAIP core.

8. The system of claim 6, wherein the host further comprises a PCIe switch chip, the Zynq board and the plurality of PCIe devices are each electrically connected to the PCIe switch chip.

9. An electronic device, comprising:

at least one processor; and

a memory storing a computer program executable in the processor, the processor executing the transmission method of any one of claims 1-6 when the program is executed.

10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, performs the transmission method according to any one of claims 1-6.