CN116208147A

CN116208147A - Sectional type R-2R inverted trapezoidal resistance network with high spurious-free dynamic range

Info

Publication number: CN116208147A
Application number: CN202211573290.XA
Authority: CN
Inventors: 袁军; 吴亮波; 赵汝法; 尹国和; 王巍; 吴浩; 王育新; 王妍; 刘建伟; 梁宏玉
Original assignee: CETC 24 Research Institute; Chongqing University of Post and Telecommunications
Current assignee: CETC 24 Research Institute; Chongqing University of Post and Telecommunications
Priority date: 2022-12-08
Filing date: 2022-12-08
Publication date: 2023-06-02

Abstract

The invention claims a segmented R-2R inverted resistor network with high Spurious-free dynamic range, which improves the Spurious-free dynamic range (SFDR) of a circuit by segmenting the R-2R inverted resistor network and performing non-overlapping rotation selection processing on a high-order segment resistor network. The circuit mainly comprises: a thermometer decoder for transcoding the high 4-bit binary code into a 15-level thermometer code; the accumulator is used for accumulating the high 4-bit binary codes and generating a shift control signal (also called a pointer) required by the logarithmic shifter; the logarithmic shifter is used for carrying out shift operation according to the shift control signal input by the accumulator and the input thermometer code; a level holding circuit for compensating a level lost when the digital shifter performs a shifting operation; a latch for time domain alignment of the low 12 and high 4 bits signals; the segmented R-2R inverted resistor network is used for receiving the digital signals of the latches and then decoding the digital signals.

Description

Sectional type R-2R inverted trapezoidal resistance network with high spurious-free dynamic range

Technical Field

The invention belongs to the technical field of analog integrated circuit design, and particularly relates to a segmented R-2R inverted resistor network with a high spurious-free dynamic range.

Background

Data converters are extremely important modules in modern signal processing systems and are also bottlenecks that limit the overall system signal processing capability. The performance index of the data converter determines the quality of a product, and products with high performance are necessarily favored by consumers. In digital-to-analog converters, spurious-free dynamic range (SFDR), which refers to the ratio of the RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the sub-maximum distortion component, is an important dynamic performance parameter of data converters, is important in communication systems, such as in analog-to-digital conversion of small signals, where spurious emissions generated by a large signal path are similar to the signal path frequency, resulting in the masking of information within the small signal path.

For the Nyquist digital-to-analog converter, there are three design directions of voltage type, charge type and current type; for an oversampled digital-to-analog converter, there is a Sigma Delta digital-to-analog converter. But for high precision digital-to-analog converters, the choice of design is greatly constrained: the voltage and charge types are not suitable for the high precision field due to the structure, so only the current type digital-to-analog converter and the Sigma Delta digital-to-analog converter can be selected. The Sigma Delta digital-to-analog converter has the advantage that it can achieve high precision, even ultra high precision, but it has complex digital and analog circuits, not a low cost design. In the current type digital-to-analog converter, the R-2R inverted trapezoidal resistance network is a good scheme, most of the circuits of the current type digital-to-analog converter are composed of two resistors, namely R and 2R, the matching precision is high, and meanwhile the current type digital-to-analog converter has the advantage of small area. Although the R-2R inverted resistor network can be used as a high-precision data converter, the matching precision of the actual resistor can be up to 12 bits generally, and the high-precision requirement of 16 bits is not met. Therefore, the designer proposes a R-2R inverted resistor network of a sectional scheme, which is generally divided into two or three sections, such as a 12-bit R-2R inverted resistor network, designed into (4+8) sectional type, which means that the upper 4 bits are decoded into a 15-level thermometer code, the lower 8 bits keep a binary code, then the precision requirement of the lower section only needs 8 bits, the precision requirement of the upper section needs 12 bits, the precision requirement of a 12-bit data converter is met, and all the bit sections are not required to be 12-bit precision.

However, in the case of a 16-bit data converter, if the data converter is designed to be of a sectional type, a part of resistance is required to achieve 16-bit precision, so that a unit formed by an analog device cannot be completely matched, and the mismatch affects various performances of the whole converter, such as SFDR (small form factor digital error) and the like in the form of nonlinear errors. Therefore, to guarantee the performance requirements of high SFDR, designers typically choose to compensate for this mismatch in terms of switching transitions.

When the high-order section switch of the segmented R-2R inverted resistor network receives a control signal, the thermometer codes used can cause the selected frequency of one part of units to be far higher than that of other parts, so that the mismatch of the parts of units can appear in a power spectrum density diagram in a harmonic mode, and the SFDR of the system is greatly reduced. Thus, to optimize this phenomenon, a switching plus algorithm in the high-order segment is required: the accumulator accumulates the binary codes of the high-order segments, and takes the result as a pointer signal to control the shift operation of the logarithmic shifter on the thermometer codes, and the output code of the logarithmic shifter enables the frequency of the switch of each high-order segment to be the same, thereby greatly inhibiting the generation of harmonic waves and improving the SFDR of the system.

Disclosure of Invention

The present invention is directed to solving the above problems of the prior art. A segmented R-2R inverted resistor network with high spurious-free dynamic range is provided. The technical scheme of the invention is as follows:

a segmented R-2R inverted ladder resistor network of high spurious-free dynamic range comprising: thermometer decoder, accumulator, logarithmic shifter, level holding circuit, latch and segmented R-2R inverted ladder resistor network, wherein,

a thermometer decoder for transcoding the high 4-bit binary code into a 15-level thermometer code;

the accumulator is used for accumulating the high 4-bit binary codes and generating a shift control signal required by the logarithmic shifter;

the logarithmic shifter is used for carrying out shift operation according to the shift control signal input by the accumulator and the 15-stage thermometer code input;

a level holding circuit for compensating a level lost when the logarithmic shifter performs a shifting operation;

a latch for time domain alignment of the low 12 and high 4 bits signals;

the segmented R-2R inverted resistor network is used for receiving the digital signals of the latches and then decoding the digital signals.

2. Furthermore, the thermometer decoder is configured to transcode the high 4-bit binary code into a 15-level thermometer code, and specifically includes basic gate-level circuits such as a nand gate, a nor gate, and the like. For example, the upper 4 bits binary code is D _in3 D _in2 D _in1 D _in0 0001, then the transcoded thermometer code temp ₁₅ temp ₁₄ ……temp ₁ In the form of 000000000000001,

the device consists of two NOR gates and one NAND gate; for another example, the upper 4 bits binary code is D _in3 D _in2 D _in1 D _in0 0110, then the transcoded thermometer code temp ₁₅ temp ₁₄ ……temp ₁ 000000000111011->

Consists of two NAND gates and one NOT gate.

Further, the accumulator is composed of four full adders and eight D flip-flops, wherein the carry output end of the full adder 1 is connected with the carry input end of the full adder 2; the carry output end of the full adder 2 is connected with the carry input end of the full adder 3; the carry output end of the full adder 3 is connected with the carry input end of the full adder 4; the carry output end of the full adder 4 is connected with the carry input end of the full adder 1 to finish the carry algorithm; the output S of each full adder ₁ ～S ₄ The input of the D flip-flops reaches the D flip-flops 1-4, the eight D flip-flops are respectively controlled by two opposite phase clocks, wherein the D flip-flops 1-4 are latched, the D flip-flops 5-8 are read, and after one latching operation is completed, the results p [3:0] of the D flip-flops 5-8 are obtained]One side returns to the full adder input B ₁ ～B ₄ The thermometer code is controlled to perform a shift operation while being used as a control signal of the logarithmic shifter.

Further, the logarithmic shifter is configured to perform a shift operation according to a shift control signal p [3:0] input by the accumulator and 15-stage thermometer codes temp [ 1-15 ] input, and specifically includes 60 (15×4) muxes supporting a cyclic shift operation with a fixed bit width, where each MUX includes two NMOS switches, one of which receives the shift control signal and the other of which receives an inverse signal of the shift control signal.

Furthermore, the level holding circuit has 15 branches, each branch is composed of two inverters and a PMOS tube, the source electrode of the PMOS tube is connected to the power supply VDD, the grid electrode of the PMOS tube is connected to the output end of the inverter n_1 and the input end of the inverter n_2 of the branch, the drain electrode of the PMOS tube is connected to the input end of the inverter n_1, and the PMOS tube and the logarithmic shifter together complete the shifting operation, and the correct result is ensured.

Further, the latch is configured to time-domain align the low 12 bit signal and the high 4 bit signal, and specifically includes 12D flip-flops that receive the low 12 bit signal and 15D flip-flops that receive the high 4 bit signal after being transcoded into the 15-stage thermometer code. The low 12-bit signal always reaches the D trigger, the high 4-bit signal has a certain delay due to transcoding and algorithm, and the high 4-bit signal are output to the segmented R-2R inverted ladder resistor network together after the next clock rising edge comes.

Further, the segmented R-2R inverted resistor network is segmented by (4+12); the 4-bit binary code of the high-order segment is transcoded into a 15-level thermometer code, and the 12-bit binary code of the low-order segment does not perform transcoding operation; each branch of the high-order section consists of two large resistors R, a small resistor R and a single-pole double-throw switch, the single-pole double-throw switch receives signals d [ 1-15 ] for controlling the high position 4, one branch of the low-order section consists of two large resistors R and two small resistors R, the other 12 branches consist of three large resistors R, two small resistors R and a single-pole double-throw switch, and the single-pole double-throw switch receives signals b [11:0] for controlling the low position 12.

The invention has the advantages and beneficial effects as follows:

the invention provides a segmented R-2R inverted resistor network with high spurious-free dynamic range, which is characterized in that the influence of the on-resistance of a CMOS switch on the resistor network is counteracted by carrying out segmented processing on the traditional R-2R inverted resistor network and then adding a small resistor R between R. Because the inherent mismatch of the analog device is that the segmented R-2R inverted ladder resistor network still has higher second harmonic component, the invention designs the switch switching to be a scheme without overlapping rotation selection by adding a simple digital circuit, so that the probability of each CMOS switch being selected is as great, the times of selecting individual branches are avoided to be far higher than other branches, and the harmonic wave caused by input codes is further restrained, thereby realizing high spurious-free dynamic range.

Drawings

FIG. 1 is a block diagram of a conventional R-2R inverted ladder resistor network in accordance with a preferred embodiment of the present invention.

FIG. 2 is a block diagram of an R-2R inverted ladder resistor network according to an embodiment of the invention.

FIG. 3 is a top-level circuit block diagram implementing low-cost high spurious-free dynamic range in accordance with an embodiment of the present invention.

Fig. 4 is a schematic diagram of a full adder portion of an accumulator according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a D flip-flop array for use in an accumulator in accordance with an embodiment of the present invention.

Fig. 6 is a schematic diagram of a logarithmic shifter according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a level holding circuit structure according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a switching scheme for controlling a bypass switch with thermometer codes.

Fig. 9 is a schematic diagram of a switching scheme of non-overlapping rotation selection according to an embodiment of the present invention.

FIG. 10 is a graph of the power spectral density of the output signal of a conventional R-2R inverted ladder resistor network under a resistor mismatch condition.

FIG. 11 is a power spectral density plot of an output signal for an R-2R inverted ladder resistor network implementing a low cost, high spurious free dynamic range with resistor mismatch in accordance with an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and specifically described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only a few embodiments of the present invention.

The technical scheme for solving the technical problems is as follows:

as shown in fig. 1, the conventional R-2R inverted resistor network is shown, and the branches except the most significant branch (leftmost in fig. 1) are composed of two R and one single-pole double-throw switch, and the least significant branch (rightmost in fig. 1) is composed of two R and one gate to power supply VDD, are composed of three R and one single-pole double-throw switch. When the input code is applied to b ₁ ～b ₁₆ And when the digital-to-analog conversion is carried out on the R-2R inverted ladder resistor network. This structure is easy to implement, but has disadvantagesObvious: on the one hand, the matching precision of the resistor R is limited, and on the other hand, the single-pole double-throw switch consists of two CMOS switches, and the on resistance of the CMOS switches can influence the simple double resistance relation of R and 2R in an R-2R inverted trapezoidal resistor network.

As shown in FIG. 2, for a sectional R-2R inverted resistor network designed by the invention, the traditional R-2R inverted resistor network is subjected to (4+12) sectional processing, wherein the 4-bit binary code of the high-order section is transcoded into 15-level thermometer code, and the 12-bit binary code of the low-order section is not transcoded; each branch of the high-level section comprises two large resistors R, a small resistor R and a single-pole double-throw switch, the single-pole double-throw switch receives signals d [ 1-15 ] for controlling high 4 bits, the low-level section consists of one branch except for the two large resistors R and the two small resistors R, the other 12 branches comprise three large resistors R, two small resistors R and a single-pole double-throw switch, and the single-pole double-throw switch receives signals b [11:0] for controlling low 12 bits. It is particularly noted that the value of R should be consistent with the on-resistance of the CMOS switch, so that R and 2R in the R-2R inverted ladder network are converted into (r+r) and 2 (r+r), and still satisfy a simple double resistance relationship.

As shown in fig. 3, a top level circuit block diagram is provided in accordance with the present invention. The 16-bit binary code Din [15:0] is divided into two parts: one part directly enters the latch to wait for the latch to receive the instruction and then output, the other part is used as the input of the thermometer decoder, the 4-bit binary code is transcoded into the 15-level thermometer code, and meanwhile, the 4-bit binary code is also used as the input of the accumulator, the accumulator performs accumulation operation on each input, and the result is used as a pointer p [3:0] to control the shift of the 15-level thermometer code in the logarithmic shifter. Since the on-resistance and the open-circuit resistance of the CMOS switch in the conventional logarithmic shifter can make the output high level of the logarithmic shifter not reach the power supply voltage value, the output of the logarithmic shifter is connected to the level holding circuit to ensure that the output high level reaches the power supply voltage value. The output of the level holding circuit is connected to the latch and is output together with the code to be output, and the output is used as a control signal of the segmented R-2R inverted ladder resistor network.

As shown in fig. 4 and 5, is the presentThe main components of the accumulator designed by the invention comprise four full adders and eight D flip-flops, wherein the carry output end of the full adder 1 is connected with the carry input end of the full adder 2; the carry output end of the full adder 2 is connected with the carry input end of the full adder 3; the carry output end of the full adder 3 is connected with the carry input end of the full adder 4; the carry output end of the full adder 4 is connected with the carry input end of the full adder 1 to finish the carry algorithm; the output S of each full adder ₁ ～S ₄ The input of the D flip-flops reaches the D flip-flops 1-4, the eight D flip-flops are respectively controlled by two opposite phase clocks, wherein the D flip-flops 1-4 are latched, the D flip-flops 5-8 are read, and after one latching operation is completed, the results p [3:0] of the D flip-flops 5-8 are obtained]One side returns to the full adder input B ₁ ～B ₄ The thermometer code is controlled to perform a shift operation while being used as a control signal of the logarithmic shifter.

As shown in fig. 6, the logarithmic shifter designed for the present invention is used for performing a shift operation according to a shift control signal p [3:0] input by the accumulator and 15-stage thermometer codes temp [ 1-15 ] input, and specifically includes 60 (15×4) muxes supporting a cyclic shift operation with a fixed bit width, each MUX includes two NMOS switches, one of which receives a shift control signal and the other of which receives an inverse signal of the shift control signal.

As shown in FIG. 7, the level holding circuit designed for the present invention comprises 15 branches, each branch is composed of two inverters and a PMOS tube, the source electrode of the PMOS tube is connected to the power supply VDD, the grid electrode is connected to the output end of the inverter n_1 and the input end of the inverter n_2 of the branch, the drain electrode is connected to the input end of the inverter n_1, and the shift operation is completed together with the logarithmic shifter, and the correct result is ensured.

As shown in fig. 8, a schematic diagram of switching of the bypass switch is controlled by using thermometer codes. It can be seen from the figure that each time a branch is selected starting from branch 1, although the inputs are different, this results in branch 1 being selected at a higher frequency than the other branches, and that mismatch errors present in branch 1 will cause harmonic components, which are analyzed in a similar way.

Fig. 9 is a schematic diagram of a switching scheme of non-overlapping rotation selection according to an embodiment of the present invention. The same inputs are provided as in fig. 8, except that when the next input comes, the selection of the branch is not started from the branch 1 any more, but is started from the next branch of the branches selected last time, and the switching scheme of the switch makes the selected frequency of each branch the same, so that harmonic components caused by the branches with higher selected frequencies are greatly suppressed.

Simulation results are shown in fig. 10 and 11, and fig. 9 is a power spectrum density diagram of an output signal of a traditional R-2R inverted trapezoidal resistor network under a resistor mismatch condition, and the second harmonic component of the signal severely reduces the SFDR of the system. FIG. 11 is a graph of power spectral density of an output signal of an R-2R inverted ladder resistor network implementing a low cost and high spurious free dynamic range with suppressed second and third harmonics of the signal and increased SFDR by 11dB in accordance with an embodiment of the present invention.

In summary, the present invention has the following technical features: (1) The segmented R-2R inverted resistor network with high spurious-free dynamic range is provided, and the (4+12) segmentation processing is carried out on the traditional R-2R inverted resistor network; (2) The non-overlapping rotation selection algorithm can be realized by using basic circuits such as a full adder, a D trigger and various gate level circuits without complex algorithm logic, so that the mismatch of analog components is compensated, and the aim of high spurious-free dynamic range is fulfilled; (3) The resistor network structure and the algorithm circuit adopted by the invention are all expandable and are not limited to the bit number of the invention.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The above examples should be understood as illustrative only and not limiting the scope of the invention. Various changes and modifications to the present invention may be made by one skilled in the art after reading the teachings herein, and such equivalent changes and modifications are intended to fall within the scope of the invention as defined in the appended claims.

Claims

1. A segmented R-2R inverted resistor network of high spurious-free dynamic range comprising: thermometer decoder, accumulator, logarithmic shifter, level holding circuit, latch and segmented R-2R inverted ladder resistor network, wherein,

a latch for time domain alignment of the low 12 and high 4 bits signals;

a segmented R-2R inverted ladder resistor network, segmented by (4+12); the 4-bit binary code of the high-order segment is transcoded into a 15-level thermometer code, and the 12-bit binary code of the low-order segment does not perform transcoding operation; each branch of the high-order section consists of two large resistors R, a small resistor R and a single-pole double-throw switch, the single-pole double-throw switch receives signals d [ 1-15 ] for controlling the high position 4, one branch of the low-order section consists of two large resistors R and two small resistors R, the other 12 branches consist of three large resistors R, two small resistors R and a single-pole double-throw switch, and the single-pole double-throw switch receives signals b [11:0] for controlling the low position 12.

2. The segmented R-2R inverted ladder resistor network with high spurious free dynamic range of claim 1, wherein the thermometer decoder is configured to transcode high 4-bit binary code into 15-level thermometer code, specifically including basic gate-level circuits such as NAND gate, NOR gate and NOT gate, and the high 4-bit binary code is D _in3 D _in2 D _in1 D _in0 0001, then the transcoded thermometer code temp ₁₅ temp ₁₄ ……temp ₁ In the form of 000000000000001,

the device consists of two NOR gates and one NAND gate; the high 4-bit binary code is D _in3 D _in2 D _in1 D _in0 0110, then the transcoded thermometer code temp ₁₅ temp ₁₄ ……temp ₁ 000000000111011->

Consists of two NAND gates and one NOT gate.

3. A segmented R-2R inverted ladder resistor network of high spurious free dynamic range according to claim 1, wherein the accumulator is comprised of four full adders and eight D flip-flops, wherein the carry output of full adder 1 is connected to the carry input of full adder 2; the carry output end of the full adder 2 is connected with the carry input end of the full adder 3; the carry output end of the full adder 3 is connected with the carry input end of the full adder 4; the carry output end of the full adder 4 is connected with the carry input end of the full adder 1 to complete the carry-back algorithmThe method comprises the steps of carrying out a first treatment on the surface of the The output S of each full adder ₁ ～S ₄ The input of the D flip-flops reaches the D flip-flops 1-4, the eight D flip-flops are respectively controlled by two opposite phase clocks, wherein the D flip-flops 1-4 are latched, the D flip-flops 5-8 are read, and after one latching operation is completed, the results p [3:0] of the D flip-flops 5-8 are obtained]One side returns to the full adder input B ₁ ～B ₄ The thermometer code is controlled to perform a shift operation while being used as a control signal of the logarithmic shifter.

4. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the logarithmic shifter is configured to shift according to the shift control signal p [3:0] input by the accumulator and the 15-level thermometer codes temp [ 1-15 ], and specifically comprises 60 (15 x 4) muxes supporting a cyclic shift operation of a fixed bit width, each MUX comprising two NMOS switches, one NMOS switch receiving the shift control signal and the other receiving an inverse of the shift control signal.

5. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the level holding circuit has 15 branches, each branch is composed of two inverters and a PMOS tube, the source of the PMOS is connected to the power supply VDD, the gate is connected to the output terminal of the inverter n_1 and the input terminal of the inverter n_2 of the branch, the drain is connected to the input terminal of the inverter n_1, the shift operation is completed together with the logarithmic shifter, and the correct result is ensured.

6. The high spurious-free dynamic range segmented R-2R inverted resistor network of claim 1, wherein the latches are configured to time-domain align the low 12-bit and high 4-bit signals, and specifically comprise 12D flip-flops that receive the low 12-bit signals and 15D flip-flops that receive the high 4-bit signals after transcoding to a 15-level thermometer code. The low 12-bit signal always reaches the D trigger, the high 4-bit signal has a certain delay due to transcoding and algorithm, and the high 4-bit signal are output to the segmented R-2R inverted ladder resistor network together after the next clock rising edge comes.

7. A segmented R-2R inverted ladder network of high spurious free dynamic range according to claim 1, wherein the segmented R-2R inverted ladder network is segmented by (4+12); the 4-bit binary code of the high-order segment is transcoded into a 15-level thermometer code, and the 12-bit binary code of the low-order segment does not perform transcoding operation; each branch of the high-order section consists of two large resistors R, a small resistor R and a single-pole double-throw switch, the single-pole double-throw switch receives signals d [ 1-15 ] for controlling the high position 4, one branch of the low-order section consists of two large resistors R and two small resistors R, the other 12 branches consist of three large resistors R, two small resistors R and a single-pole double-throw switch, and the single-pole double-throw switch receives signals b [11:0] for controlling the low position 12.