CN116207957A - Inverter structure and fault response method thereof - Google Patents

Abstract

The invention provides an inverter structure and a fault response method thereof, and provides a main control chip and peripheral equipment of an MCU, a driving chip for controlling a plurality of groups of switching tubes and a hardware fault management main module; the hardware fault management main module is integrated with the multi-core CPU in the main control chip; judging whether hardware fails by MCU peripheral equipment, if yes, sending failure information to multi-core CPU; the multi-core CPU receives the fault information and then sends a response signal to the driving chip, so that the driving chip controls at least one group of switching tubes to enter an open circuit or short circuit state. According to the invention, the CPLD chip and related peripheral circuits can be directly omitted by integrating the hardware CPLD fault influence and PWM output protection logic into the MCU, so that the cost of the product is reduced, and the production beat of the product is improved.

Description

Inverter structure and fault response method thereof

Technical Field

The present invention relates to the field of electronic circuits, and in particular, to an inverter structure and a fault response method thereof.

Background

Along with the rapid development of the new energy automobile industry, more and more pure electric and plug-in hybrid electric vehicles move to consumer lives, the inverter topology shown in the following figure 1 is widely adopted, a high-voltage battery transmits energy to an IGBT (insulated gate bipolar transistor) module or a SIC (silicon carbide) device module through a voltage stabilizing filter capacitor, and a motor is driven to output torque after switching modulation.

However, various hardware faults may occur in the power output of the inverter, which causes torque runaway or high voltage risk and threatens personal safety. The main hardware faults include hardware bus overvoltage, phase current hardware overcurrent, IGBT or SIC switch through, IGBT gate drive power supply and the like. When single or multiple hardware faults occur, power output needs to be stopped, and the IGBT or SIC switch is controlled to respond to a specific safety state. Common safety conditions are a short circuit of the lower three pipes (hereinafter referred to as lower ASC), a short circuit of the upper three pipes (hereinafter referred to as upper ASC), and an open circuit of the upper and lower pipes (hereinafter referred to as FW). Wherein ASC is a loop for actively conducting three switches of the upper bridge or the lower bridge and providing motor phase current; FW is the current loop through the IGBT or SIC switch, where all six switches are open. FW is a common safety state, but if the motor rotation speed is high at this time, the back electromotive force voltage of the motor can boost the bus voltage through reverse charging of the diode, and if the bus voltage is high, undesirable high voltage can be caused, so that high voltage safety is threatened. The hardware overvoltage fault should respond to a lower three-tube short condition and if the hardware overvoltage and low side IGBT or (SIC) drive power occur simultaneously, then it should respond to an upper three-tube short condition.

Because faults such as overvoltage of a hardware bus or hardware damage of a driving circuit have high requirements on response time of a safety state, the current vehicle inverter on the market is realized by a multi-purpose programmable logic chip (such as Complex Programmable Logic Device, CPLD for short), and the structure shown in the figure 2 is that a main control chip is responsible for a motor control algorithm and provides six switching signals for the programmable logic chip (such as Complex Programmable Logic Device, CPLD for short) responsible for hardware fault response. The programmable logic chip is responsible for transmitting six-way switch signals to the driving chip, in addition, the hardware fault response chip is responsible for hardware fault response, if the hardware fault is detected, six-way switch signals sent by the main control chip are not directly output, and corresponding safety states such as lower/upper three-pipe short circuit (ASC) or full open circuit (FW) are directly output.

However, the programmable logic device has higher cost, requires peripheral circuits to be matched for use, and occupies a larger circuit board area. The scheme also needs to maintain an additional CPLD hardware program, needs to consider the problems of version upgrading, matching with MCU programs and the like, and brings certain inconvenience along with popularization of remote software upgrading of automobiles. In addition, a specific station is required to carry out program refreshing during production, and the production takt time of the product is affected.

With the increase of MCU calculation power, the integration of fault response logic into MCU brings much convenience and reduces product cost. But the response speed, reliability of fault signal capture, etc. present significant challenges. In addition, the original state management and fault diagnosis module of the MCU also needs to acquire the fault information which occurs and carry out a corresponding fault recovery mechanism.

In order to solve the above problems, a new inverter structure and a fault response method thereof are required.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing an inverter structure and a fault response method thereof, which are used for solving the problems that in the prior art, the cost of a programmable logic device is high, a peripheral circuit is required to be used in cooperation, a large circuit board area is occupied, an additional CPLD hardware program is required to be maintained, version upgrade is required to be considered, matching with an MCU program is required to be performed, and certain inconvenience is brought along with popularization of remote software upgrade of an automobile; when in production, a specific station is required to carry out program refreshing, so that the production takt time of the product is influenced; the response speed of MCU to the fault, reliability of fault signal acquisition need to be guaranteed.

To achieve the above and other related objects, the present invention provides a response method for hardware failure, including:

the MCU comprises a main control chip, peripherals, a driving chip for controlling a plurality of groups of switching tubes and a hardware fault management main module;

wherein, the liquid crystal display device comprises a liquid crystal display device,

the hardware fault management main module is integrated with a multi-core CPU in the main control chip;

the MCU peripheral is used for judging whether hardware fails, if yes, fault information is sent to the multi-core CPU;

the multi-core CPU is used for sending a response signal to the driving chip after receiving the fault information, so that the driving chip controls at least one group of switching tubes to enter an open circuit or short circuit state.

Preferably, the switching tube is at least one of an IGBT and a SIC switching tube.

Preferably, the MCU peripheral includes a direct current IO module, a peripheral capturing module and a peripheral handling module, where the direct current IO module is configured to receive a digital signal of an external MCU circuit, the peripheral information capturing module is configured to detect the digital signal to obtain the fault information, and the peripheral handling module is configured to receive the fault information.

Preferably, the hardware fault management master module includes a fault latch module, a fault response module, a shared memory module, and a fault management module.

Preferably, the method for continuously acquiring fault information of hardware by the MCU peripheral and sending the fault information to the multi-core CPU includes: the MCU peripheral comprises a direct current IO module, a peripheral capturing module and a peripheral carrying module, wherein the direct current IO module is used for receiving digital signals of a circuit in the MCU, detecting the digital signals according to the peripheral information capturing module, judging whether faults occur, if yes, sending fault information to the peripheral carrying module, and the peripheral carrying module stores the fault information to a designated memory address.

Preferably, the fault latch module, the fault response module and the shared memory module are respectively arranged on the secondary cores in the multi-core CPU.

Preferably, the fault management module is disposed on a main core in the multi-core CPU.

Preferably, the fault latch module is configured to obtain the fault information according to the peripheral handling module, and store the fault information to a memory address thereof to obtain the fault latch information.

Preferably, the fault response module is configured to send the response signal to the driving chip after obtaining the fault latch information.

Preferably, the response signal is a PWM wave.

Preferably, the MCU peripheral device further comprises a dead zone protection module, and the response signal eliminates the through signal of the response signal through the dead zone protection module and is sent to the direct current IO module.

Preferably, the shared memory module includes a fault register and a configuration register, the fault register determines a position corresponding to a fault according to the fault latch information, sets a corresponding bit, and the configuration register configures a fault clearing instruction, where the fault clearing instruction is used to clear the fault latch information in the fault latch or reset the bit in the fault register.

Preferably, the fault management module includes a fault diagnosis module and a fault clearing module, where the fault diagnosis module periodically reads the bit in the configuration register, counts the number of times of fault occurrence if a fault occurs, and determines whether the number of times is greater than a set threshold, if yes, the fault clearing module does not work, and the fault diagnosis module sends a response signal to the driving chip, so that the driving chip controls at least one group of switching tubes to enter an open circuit or a short circuit state.

Preferably, the fault management module includes a fault diagnosis module and a fault clearing module, where the fault diagnosis module is configured to periodically read the bit in the configuration register, count the number of times of occurrence of a fault, determine whether the number of times is greater than a set threshold, and if not, control the configuration register to send a fault clearing instruction through the fault clearing module, and reset the fault latch information and the bit in the fault register.

Preferably, the MCU peripheral is configured to determine whether a hardware failure occurs, and if not, control, by the failure clearing module, the configuration register to send a failure clearing instruction, and reset the failure latch information and the bit in the failure register.

A fault response method of an inverter structure, the fault response method being used for the inverter structure described above.

As described above, the inverter structure and the fault response method thereof of the present invention have the following advantages:

according to the invention, the CPLD chip and related peripheral circuits can be directly omitted by integrating the hardware CPLD fault influence and PWM output protection logic into the MCU, so that the cost of the product is reduced, and the production beat of the product is improved.

Drawings

Fig. 1 is a schematic diagram showing a structure of a prior art inverter for a vehicle;

FIG. 2 is a schematic diagram of a prior art MCU protection device;

FIG. 3 is a schematic diagram of an MCU protection device according to the present invention;

FIG. 4 is a schematic diagram of a main control chip according to the present invention;

FIG. 5 is a schematic diagram of hardware fault diagnosis and repair response logic of the present invention;

FIG. 6 shows a dead zone protection schematic of the present invention;

FIG. 7 is a schematic diagram of a master check hardware fault diagnosis of the present invention;

fig. 8 is a schematic diagram of a primary core fault clearing configuration of the present invention.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Referring to fig. 5, the present invention provides an inverter structure, comprising:

referring to fig. 3 and 4, an MCU main control chip 1, a peripheral 11, a driving chip 2 for controlling a plurality of groups of switching transistors 3 (not shown), and a hardware fault management main module are provided; wherein, the liquid crystal display device comprises a liquid crystal display device,

the hardware fault management main module 1221 is integrated in the multi-core CPU12 in the main control chip 1, and the MCU peripheral 11 is configured to obtain fault information of hardware, and send the fault information to the multi-core CPU12;

the MCU peripheral is used for judging whether hardware fails, if yes, fault information is sent to the multi-core CPU;

the multi-core CPU12 receives the fault information and sends a response signal to the driving chip 2, so that the driving chip 2 controls at least one group of switching tubes to enter an open circuit or short circuit state, thereby entering a specific safety state.

In one possible implementation, in the first step, the multiple groups of switching transistors 3 are at least one of IGBT and SIC switching transistors.

It should be noted that the switching tube may be multiple groups of IGBTs, multiple groups of SIC switching tubes, or multiple groups of IGBTs and multiple groups of SIC switching tubes according to the actual process requirements.

For example, referring to fig. 1, two groups of IGBTs respectively include a lower three tube located in an upper bridge circuit and a lower three tube located in a lower bridge circuit. Common safety conditions are a short circuit of the lower three pipes (hereinafter referred to as lower ASC), a short circuit of the upper three pipes (hereinafter referred to as upper ASC), and an open circuit of the upper and lower pipes (hereinafter referred to as FW). Wherein ASC is a loop for actively conducting three switches of the upper bridge or the lower bridge and providing motor phase current; FW is the current loop through the IGBT switches, where all six switches are open. FW is a common safety state, but if the motor rotation speed is high at this time, the back electromotive force voltage of the motor can boost the bus voltage through reverse charging of the diode, and if the bus voltage is high, undesirable high voltage can be caused, so that high voltage safety is threatened. The hardware overvoltage fault should respond to a lower three-tube short condition and if the hardware overvoltage and low side IGBT drive power occur simultaneously, then it should respond to an upper three-tube short condition.

It should be noted that, according to different designs of the switching tube in different hardware circuits, the switching tube also corresponds to more safety modes, and is not limited to the above-mentioned safety state.

In one possible implementation manner, the MCU peripheral 11 includes a direct current IO (input/output) module, a peripheral capture module 112, and a peripheral handling module 113, where after each fault passes through a circuit such as a comparator, a digital signal can be obtained, the direct current IO module 111 is configured to receive a digital signal of an external MCU circuit and output a control signal to the external MCU circuit, the peripheral capture module 112 is configured to detect a skip edge of the digital signal to obtain fault information, and when a falling edge occurs, it is indicated that a current hardware fault occurs, and the peripheral handling module 113 is configured to receive the fault information.

In one possible implementation, a hardware failure master module integrated in the multi-core CPU12 includes a failure latch module 1211, a failure response module 1212, a shared memory module 1213, and a failure management module 1221.

In one possible implementation, the fault latch module 1211, the fault response module 1212, and the shared memory module 1213 are each disposed in a secondary core 121 (CoreX) in the multi-core CPU 12.

In one possible implementation, the fault management module 1221 is provided in the main core 122 (CoreY) of the multi-core CPU 12.

In one possible implementation manner, the dominant frequency of the current dominant MCU is about hundred MHz, which can meet the requirement of fault detection time, can configure event detection type, and can directly request interrupt through a peripheral module. After the program initialization configuration is completed, each time a fault occurs, the peripheral capture module 112 detects a falling edge of a fault signal, and then triggers the peripheral handling module 113 to send fault information to a designated memory address to obtain fault latching information.

In one possible implementation manner, the fault response module is configured to send the response signal to the driving chip after obtaining the fault latch information.

However, for some special faults, the rising edge and the falling edge need to be detected, and then the peripheral handling module 113 is triggered to handle the current fault information to the designated memory address by the occurrence and recovery of the faults, so that the fault information in the memory is erased during the fault recovery, and the fault information is latched in the software processing logic, so that the fault information is ensured not to disappear due to the fault recovery.

In addition, to prevent high frequency disturbances of the signal, the peripheral capture module 112 may be configured with a filtering function to filter the fault signal in an appropriate amount. Therefore, the fail latch module 1211 needs to be provided for storing the fail information to its memory address, resulting in fail latch information.

In one possible implementation, the event of the peripheral handling module 113 acting may be used as a request source for a CPU interrupt, and each time the peripheral handling module 113 is configured to act, a CPU interrupt is triggered to process a hardware fault. The control hardware fault handling logic acquires information that a single or a plurality of hardware faults have occurred from the fault latch module 1211 in fig. 4, sets the fault response logic according to the fault priority, and then determines the final driving output state.

The corresponding output state can be realized by driving the direct current IO module 111 through the MCU peripheral 11. The fault response module 1212 is configured to obtain fault information, and send a response signal to the driving chip 2 through the dc IO module 111.

In one possible implementation, the response signal is a PWM wave, and the dc IO module 111 may send out PWM to bring at least one set of switching tubes into a desired safe state.

In one possible implementation, the hardware fault response may have multiple gate state switches, and the need to avoid the generation of a pass signal, and the need to insert dead zones, which would otherwise result in pass through of a switching tube, such as an IGBT. The CPLD is programmed by hardware language, and digital logic is designed to ensure safe hardware dead zone when the gate state is switched. In addition, during normal torque control, the MCU can send PWM waves, the PWM waves are output to the switching tube to drive through the CPLD, the CPLD can simultaneously carry out dead zone detection on the PWM waves, and if the dead zone is too small, the minimum safety dead zone is forcibly inserted, so that the occurrence of direct connection of the switch is prevented.

In this embodiment, the dead zone protection module 114 is formed by configuring the peripheral driving output module of a certain mainstream MCU, so that the same protection function as the CPLD can be achieved. Configuration logic as shown in fig. 6, when the emitted PWM wave has no dead zone or the dead zone is too small, the dead zone protection module 114 forcibly inserts the dead zone according to the initialized preconfigured value to avoid the through occurrence, and the response signal eliminates the through signal thereof through the dead zone protection module 114 and then sends the response signal to the direct current IO module 111.

In one possible implementation, the primary core 122 may diagnose and repair hardware failures, thus requiring information interaction with the failure interrupt response module. The embodiment adopts a memory interaction mode to realize the interaction of the information. Two groups of registers are defined in the memory of the fault interrupt module, one group is a fault register, the corresponding bit is set according to the detected fault, and the main core 122 diagnosis management module acquires fault information. The other set is a configuration register through which the master core 122 fault management module 1221 sends out fault clearing instructions for clearing fault latch information. The two sets of registers are read and written separately, so as to avoid the problem of multi-core data consistency, wherein the shared memory module 1213 comprises a fault register R1 and a configuration register R2, the fault register R1 judges the position corresponding to the fault according to the fault latch information, sets the corresponding bit, and the configuration register R2 configures a fault clearing instruction, and the fault clearing instruction is used for clearing the fault latch information in the fault latch module 1211 or resetting the bit in the fault register R1.

In one possible implementation, the master core 122 may diagnose and repair the hardware fault, as shown in fig. 5, and the fault management module 1221 may manage the hardware fault by sharing registers in the memory module 1213, where the fault management flows are shown in fig. 7 and 8. The fault management module 1221 is configured to obtain fault information and perform logic determination, if a fault exists, keep an open circuit state, and if no fault exists, send a fault clearing instruction to the configuration register, so that the fault latch information is cleared, and thus at least one group of switching tubes work normally.

Specifically, the shared memory module 1213 includes a fault register R1 and a configuration register R2, where the fault register R1 determines a position corresponding to a fault according to the fault latch information, sets a corresponding bit, and the configuration register R2 configures a fault clearing instruction for clearing the fault latch information in the fault latch module 1211 or resetting the bit in the fault register R1.

The fault management module 1221 includes a fault diagnosis module and a fault clearing module, where the fault diagnosis module periodically reads bit in the configuration register R2, counts the number of times of occurrence of a fault if the fault occurs, determines whether the number of times is greater than a set threshold, if yes, the fault clearing module does not work, and the fault diagnosis module sends a response signal to the driving chip, so that the driving chip controls at least one group of switching tubes to enter an open-circuit or short-circuit state, for example, the set threshold is set to be 5 times, and if the count of detected faults exceeds 5 times, at least one group of switching tubes enters the open-circuit or short-circuit state, that is, by continuously detecting the fault state of the hardware, the hardware detects that the state is the fault in a period of time, and switches the hardware to be a safe state.

The fault management module 1221 includes a fault diagnosis module and a fault clearing module, where the fault diagnosis module periodically reads bits in the configuration register R2, counts the number of times of fault occurrence if a fault occurs, and determines whether the number of times is greater than a set threshold, and if not, controls the configuration register R2 to send a fault clearing instruction through the fault clearing module, and resets the fault latch information and the bits in the fault register R1.

In addition, the MCU peripheral 11 is used to determine whether the hardware is faulty, if not, the fault clearing module controls the configuration register R2 to send a fault clearing instruction, and resets the fault latch information and the bit in the fault register R1.

The invention also provides a fault response method of the inverter structure corresponding to the method, and the fault response method is used for the inverter structure.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

In summary, the invention integrates the hardware CPLD fault influence and the PWM output protection logic into the MCU, so that the CPLD chip and related peripheral circuits can be directly omitted, thereby reducing the cost of the product and improving the production takt of the product. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (16)

1. An inverter structure, comprising:

the MCU comprises a main control chip, peripherals, a driving chip for controlling a plurality of groups of switching tubes and a hardware fault management main module; wherein, the liquid crystal display device comprises a liquid crystal display device,

the hardware fault management main module is integrated with a multi-core CPU in the main control chip;

the MCU peripheral is used for judging whether hardware fails, if yes, fault information is sent to the multi-core CPU;

the multi-core CPU is used for sending a response signal to the driving chip after receiving the fault information, so that the driving chip controls at least one group of switching tubes to enter an open circuit or short circuit state.

2. The inverter structure according to claim 1, wherein: the switching tube is at least one of an IGBT and an SIC switching tube.

3. The inverter structure according to claim 1, wherein: the MCU peripheral comprises a direct current IO module, a peripheral capturing module and a peripheral carrying module, wherein the direct current IO module is used for receiving digital signals of an external MCU circuit, the peripheral information capturing module is used for detecting the digital signals to obtain fault information, and the peripheral carrying module is used for receiving the fault information.

4. The inverter structure according to claim 1, wherein: the hardware fault management main module comprises a fault latching module, a fault responding module, a shared memory module and a fault management module.

5. An inverter structure according to claim 3, wherein: the MCU peripheral is used for continuously acquiring fault information of hardware, the MCU peripheral comprises a direct current IO module, a peripheral capturing module and a peripheral carrying module, the direct current IO module is used for receiving digital signals of circuits in the MCU, detecting the digital signals according to the peripheral information capturing module and judging whether faults occur or not, if yes, sending the fault information to the peripheral carrying module, and the peripheral carrying module stores the fault information to a designated memory address.

6. The inverter structure according to claim 4, wherein: the fault latch module, the fault response module and the shared memory module are respectively arranged in the secondary cores of the multi-core CPU.

7. The inverter structure according to claim 4, wherein: the fault management module is arranged on a main core in the multi-core CPU.

8. The inverter structure according to claim 5, wherein: the fault latch module is used for acquiring the fault information according to the peripheral handling module, and storing the fault information to a memory address of the peripheral handling module to obtain the fault latch information.

9. The inverter structure of claim 8 wherein: the fault response module is used for sending out the response signal to the driving chip after obtaining the fault latching information.

10. The inverter structure of claim 9 wherein: the response signal is a PWM wave.

11. The inverter structure of claim 10 wherein: the MCU peripheral also comprises a dead zone protection module, and the response signal eliminates the direct-current signal of the response signal through the dead zone protection module and then is sent to the direct-current IO module.

12. The inverter structure of claim 9 wherein: the shared memory module comprises a fault register and a configuration register, wherein the fault register judges the position corresponding to the fault according to the fault latch information, sets a corresponding bit, and the configuration register configures a fault clearing instruction which is used for clearing the fault latch information in the fault latch or resetting the bit in the fault register.

13. The inverter structure of claim 12 wherein: the fault management module comprises a fault diagnosis module and a fault clearing module, the fault diagnosis module periodically reads the bit in the configuration register, counts the times of fault occurrence when faults occur, judges whether the times are larger than a set threshold value, if yes, the fault clearing module does not work, and the fault diagnosis module sends a response signal to the driving chip so that the driving chip controls at least one group of switching tubes to enter an open circuit or short circuit state.

14. The inverter structure of claim 12 wherein: the fault management module comprises a fault diagnosis module and a fault clearing module, wherein the fault diagnosis module is used for periodically reading the bit in the configuration register, counting the times of fault occurrence if faults occur, judging whether the times are larger than a set threshold value, and if not, controlling the configuration register to send a fault clearing instruction through the fault clearing module to reset the fault latching information and the bit in the fault register.

15. The inverter structure according to claim 13 or 14, wherein: and the MCU peripheral is used for judging whether hardware fails, if not, the configuration register is controlled by the failure clearing module to send a failure clearing instruction, and the failure latching information and the bit in the failure register are reset.

16. The fault response method of an inverter structure according to any one of claims 1 to 15, wherein: the fault response method is for the inverter architecture.

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