CN116207144B - Ferroelectric camouflage transistor and read-write mode of safety circuit thereof - Google Patents

Ferroelectric camouflage transistor and read-write mode of safety circuit thereof Download PDF

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CN116207144B
CN116207144B CN202310077662.8A CN202310077662A CN116207144B CN 116207144 B CN116207144 B CN 116207144B CN 202310077662 A CN202310077662 A CN 202310077662A CN 116207144 B CN116207144 B CN 116207144B
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ferroelectric
transistor
camouflage
layer
drain
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CN116207144A (en
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廖敏
石万千
廖佳佳
齐立杨
周益春
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention provides a ferroelectric camouflage transistor and a read-write mode of a safety circuit thereof, which mainly relate to the technical field of chips and comprise a substrate, wherein an isolation layer and an active area are arranged on the substrate, a channel layer is arranged on the active area, the channel layer is made of a semiconductor material with dual polarization characteristics, an insulating layer is arranged on the channel layer, a ferroelectric material layer is arranged on the insulating layer, the ferroelectric material layer has strong ferroelectric polarization characteristics, and a gate electrode is arranged on the ferroelectric material layer.

Description

Ferroelectric camouflage transistor and read-write mode of safety circuit thereof
Technical Field
The invention mainly relates to the technical field of chips, in particular to a ferroelectric camouflage transistor and a read-write mode of a safety circuit thereof.
Background
With the rise of technologies such as the Internet of things, big data, artificial intelligence and the like, great convenience is brought to national citizens, such as smart phones, smart automobiles, cloud services and the like. But the popularization of information will also bring about a series of information security problems. The chip reverse engineering or chip decryption is used as a technology for verifying intellectual property of IC products and checking commercial piracy, and once the technology is illegally utilized by lawbreakers, huge economic loss and even threat to security of people and countries can be caused. The basic process is to dissect and restore the circuit design by chemical corrosion, plasma etching, optical imaging and other methods, so as to identify the function of the chip and decrypt the safety information.
The prior art scheme is as follows: in order to more effectively improve the security of the integrated circuit, the current security technologies are mainly divided into three types: (1) The logic confusion technology is used for resisting the threat brought by reverse engineering, and the principle is to conceal the circuit function by changing the original design structure or inserting additional circuit elements, and the logic confusion technology mainly comprises a behavior-level state redundancy technology and a physical-level circuit camouflage technology. The behavior-level state redundancy technology adds a large number of extra redundancy states into an original finite state machine and matches with the jump of a key sequence control state, if the key sequence is wrong, the original effective state cannot be jumped, and the chip cannot realize the correct logic function. (2) physical level circuit camouflage techniques. The actual functions of the circuit, such as virtual hole technology, ion doping technology, transmission tube threshold loss technology, etc., are hidden by hiding certain physical details in the layout. Compared with the behavior-level state redundancy technology, the physical-level circuit camouflage technology has better portability and safety and lower cost, and is suitable for being applied to the field of very large-scale integrated circuits. (3) IC camouflage is also a technology for actively protecting an integrated circuit, and the main working principle is to implement standard logic units which are very similar in physical but different in actual functions by modifying camouflage to standard logic gates. Therefore, when people dissect the design of the reduction circuit by optical imaging and other methods, the camouflaged circuit looks almost the same in appearance, and the logic circuits with different functions are difficult to distinguish, so that people cannot extract gate-level netlist information, and the threat brought by reverse engineering is resisted.
Logic confusion, IC camouflage, etc. are chip anti-cracking techniques that are often used by chip manufacturers, but are essentially designed to reduce the risk of chip decryption by increasing the complexity of the circuit. With the gradual powerful development of reverse engineering technology, such as SAT attack technology, logic confusion and camouflage devices of all integrated circuits can be broken. In addition, logic confusion, IC camouflage and other anti-cracking technologies require more components to hide the core functions of the circuit, and are a method for improving the safety performance of the circuit at the expense of the effective device integration density (i.e., reducing the chip performance), power consumption and cost advantages.
Disclosure of Invention
The invention aims to provide a ferroelectric camouflage transistor and a read-write mode of a safety circuit thereof, which solve the technical problem that the circuit safety performance is improved at the cost of sacrificing the integration density of effective devices (namely reducing the chip performance), power consumption and cost advantages in the prior art.
The invention discloses a ferroelectric camouflage transistor which comprises a substrate, wherein an isolation layer and an active region are arranged on the substrate, a channel layer is arranged on the active region, the channel layer is made of a semiconductor material with dual polarization characteristics, an insulating layer is arranged on the channel layer, a ferroelectric material layer is arranged on the insulating layer, the ferroelectric material layer has strong ferroelectric polarization characteristics, and a gate electrode is arranged on the ferroelectric material layer.
Further, the ferroelectric material layer is BiFeO 3 、BaTiO 3 Ferroelectric phase HfO 2 And doping system, PVDF and SrBi thereof 2 Ta 2 O 9 、PbZr x Ti 1-x O 3 AlScN or ferroelectric phase ZrO 2 And ferroelectric materials with strong polarization characteristics such as doped systems thereof.
Further, the active region comprises a channel layer, a source region and a drain region, and source and drain metal wires are respectively formed on the source region and the drain region and used for applying and reading electrical signals.
Further, the channel layer is a semiconductor which can exhibit bipolar properties.
Further, the channel layer is made of silicon material, black phosphorus or carbon nano tube.
Further, the source region and the drain region are heavily doped silicon, gold, titanium, scandium, tungsten, nickel, palladium or alloy materials thereof.
Further, the transistor is compatible with a top gate structure, a FinFET structure, a nano ring gate structure, a three-dimensional vertical channel structure and a local back gate structure.
Further, the substrate is a silicon, SOI, silicon oxide or aluminum oxide material.
Further, the isolation layer is insulating silicon oxide or silicon nitride.
Further, the insulating layer is an amorphous or paraelectric phase dielectric material
Further, the insulating layer is silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide, lanthanum oxide, silicon nitride, silicon oxynitride, titanium oxide, hafnium nitride, or the like.
Further, the thickness of the insulating layer is 0.5-10nm.
Further, the gate electrode is titanium nitride, hafnium nitride, tantalum nitride, tungsten, nickel, titanium, gold, aluminum, polysilicon, or ITO.
The second object of the invention is to protect a read-write method of a ferroelectric camouflage transistor, wherein the ferroelectric camouflage transistor is the above transistor.
Further, if VDS is applied to the drain while VGS is applied to the gate electrode, the IDS-VGS curve is measured.
Further, VDS is 0.05-3V, VGS is 0-3V. At this time, the device is in an NMOS state, and thus the device gradually changes from an off state to an on state as the gate voltage increases.
Further, VDS is-0.05 to-3V and VGS is 0 to-3V. The device is now in PMOS state, so the device gradually goes from off to on as the gate voltage sweeps from 0V to-3V.
The two working modes can be realized in the same device, so that the two working modes are completely identical from the device structure, and only the applied voltage mode is determined, the working mode can be decrypted whether the two working modes are used as NMOS or PMOS, and therefore, the information of the chip function is difficult to acquire in a chip physical analysis mode
Compared with the prior art, the invention has the following beneficial effects:
1. the invention directly optimizes the safety performance of the basic unit of the chip, and proposes a transistor based on a low-dimensional material which is regulated and controlled by a ferroelectric layer with stronger polarization characteristic. First, by using a low-dimensional material with bipolar property as a channel material of a transistor, electrons and holes can be transmitted at a similar current level, so that the P-N characteristics of the transistor can be switched by applying voltage, and by introducing a ferroelectric material with stronger polarization characteristics, the problems of reduced switching ratio of the transistor and the like caused by the small band gap of the low-dimensional material are well solved while the better electrical performance of the transistor is ensured. Compared with other anti-cracking technologies, the chip cracking method can increase the difficulty of cracking the chip without sacrificing the area and the power consumption, effectively reduce the integration difficulty and the cost of the chip and strengthen the safety of the chip.
Drawings
Fig. 1 is a schematic diagram of a ferroelectric field effect transistor structure according to the present invention.
Fig. 2 is a schematic diagram of a ferroelectric field effect transistor fabrication process according to the present invention.
Fig. 3 is a schematic diagram of the structure of the HAO ferroelectric capacitor of the present invention.
Fig. 4 is a schematic diagram of ferroelectric thin film ferroelectric property test according to the present invention.
Fig. 5 is a schematic diagram of the energy band of the ferroelectric layer modulating the schottky barrier of the channel and source drain in p-FET mode of operation of the transistor of the present invention. In the figure: 1-substrate, 2-isolation layer, 3-channel layer, 4-source region, 5-drain region, 6-insulating layer, 7-ferroelectric material layer, 8-gate electrode, 9-electrode cover layer, 10-source electrode, 11-drain electrode, 12-high-resistance silicon substrate, 13-W bottom electrode, 14-Al doped HfO 2 A ferroelectric layer, a 15-W top electrode.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments.
Example 1
A ferroelectric camouflage transistor and a read-write mode of a safety circuit thereof, wherein the ferroelectric camouflage transistor comprises a substrate 1, and the substrate 1 selects a (100) -oriented high-resistance silicon material;
forming an isolation layer 2 on the substrate 1, wherein the isolation layer 2 is SiO 2 A material;
an active region formed on the isolation layer 2, the active region being an operating region of the transistor. Which is constituted by a channel layer 3, a source region 4 and a drain region 5. The source region 4 and the drain region 5 are formed by tungsten material, and the channel layer 3 between the tungsten material and the tungsten material uses black phosphorus material with proper forbidden band width to realize the regulation of the transistor type. If a semiconductor capable of presenting bipolar is not selected as the channel layer 3, the type of the external voltage switching transistor cannot be applied;
an insulating layer 6 is formed on the channel layer, the insulating layer 6 in this example being alumina (Al 2 O 3 ) A material with a thickness of 2nm;
forming a ferroelectric material layer 7 with stronger polarization characteristics on the insulating layer, wherein the ferroelectric material layer 7 in the example is Al doped HfO 2 A ferroelectric thin film (HAO) having a thickness of 10nm; if the ferroelectric layer with stronger polarization characteristic is not selected as a dielectric material, the problems of reduced on-state current and increased off-state current of the device due to the Schottky barrier can occur, and the electrical performance of the device is greatly influenced;
forming a gate electrode 8 on the ferroelectric layer, the gate electrode in this example being W and having a thickness of 40nm;
forming an electrode coating 9, pt in this example, with a thickness of 10nm, on the gate electrode 8;
a gate stack structure formed on the insulating layer 6-ferroelectric material layer 7-gate electrode 8-electrode cover layer 9, the formation of which ensures an independent control circuit for the transistor gate;
a source electrode 10 and a drain electrode 11 are formed on the source region 4 and the drain region 5, respectively, for applying and reading an electrical signal. The source 10 and drain 11 in this example are Pt;
in order to verify the electrostatic grid regulation effect of the ferroelectric material with stronger polarization characteristic on communication, the embodiment prepares the material based on Al doped HfO 2 The ferroelectric capacitor structure is subjected to ferroelectric performance test, and the regulation and control effect and camouflage principle of the ferroelectric capacitor structure on the transistor are reflected by using the energy band diagram. The structure prepared is shown in figure 3.
The experimental procedure was as follows:
step 1: the high-resistance silicon substrate 12 is made of p-type heavily doped silicon material with (100) orientation, and the resistance is smaller than 0.005 omega cm;
step 2: an electrode is prepared.
A W bottom electrode 13 was grown on the high-resistance silicon substrate 12 with a thickness of 40nm by magnetron sputtering.
Step 3: and preparing a ferroelectric layer.
Al-doped HfO is prepared on the above-mentioned W bottom electrode 13 by ALD atomic deposition 2 The ferroelectric layer 14 has a thickness of 10nm.
Step 4: preparation of top electrode
A W top electrode 15 is grown on the ferroelectric layer under the coverage of the reticle by magnetron sputtering. The thickness was 40nm and the electrode diameter was 100. Mu.m. Then, at a temperature of 800 ℃ N 2 Annealing for 30s under atmosphere, and the formed MFM ferroelectric capacitor structure is shown in FIG. 3.
Ferroelectric performance test was performed on the ferroelectric capacitor structure, and the test results are shown in fig. 4.
FIG. 4 shows that Al doped HfO is used 2 The (HAO) ferroelectric film has a coercive voltage of about 1.3V and a saturated polarization strength of about 30. Mu.c/cm 2 The residual polarization Pr is 16.9 mu c/cm 2 And the hysteresis loop has a good squareness. The result shows that the ferroelectric film has better polarization characteristic, can effectively change the Schottky barrier between the channel and the source drain electrode, regulate and control the transistor to be in an electron injection or hole injection state, and further realize the transistor with reconfigurable polarity.
Fig. 5 is a band diagram of a transistor in p-FET mode in which the ferroelectric layer modulates the schottky barrier between the channel and the source/drain, and in p-FET mode, when the gate voltage Vg < 0, hole injection occurs at the source, the transistor is in on state, when the gate voltage vg=0, hole injection at the source is turned off, and at the drain, electron injection from the drain is suppressed due to further modulation of the band by ferroelectric polarization, and the transistor is in off state. If the ferroelectric layer is not introduced, the gate voltage is positive with respect to the drain voltage (vg=0, vd < 0), and thus electron injection occurs at the drain (as shown by the dotted line in fig. 5), resulting in an increase in off-state current, which seriously affects the switching ratio of the device. The principle in the n-FET operating mode is similar to the process described above.
The above is an embodiment exemplified in this example, but this example is not limited to the above-described alternative embodiments, and a person skilled in the art may obtain various other embodiments by any combination of the above-described embodiments, and any person may obtain various other embodiments in the light of this example. The above detailed description should not be construed as limiting the scope of the present embodiments, which is defined in the claims and the description may be used to interpret the claims.

Claims (10)

1. A ferroelectric camouflage transistor, characterized by: the semiconductor device comprises a substrate (1), wherein an isolation layer (2) and an active region are arranged on the substrate (1), a channel layer (3) is arranged on the active region, the channel layer (3) is made of a semiconductor material with bipolar characteristics, an insulating layer (6) is arranged on the channel layer (3), a ferroelectric material layer (7) is arranged on the insulating layer (6), the ferroelectric material layer (7) has strong ferroelectric polarization characteristics, a gate electrode (8) is arranged on the ferroelectric material layer (7), and the P-N characteristics of a transistor are switched through an external voltage, so that the same device realizes two working modes, and only if the applied voltage mode is determined, the device can be decrypted to work as an NMOS or a PMOS;
the ferroelectric camouflage transistor safety circuit is read and written in such a way that a source electrode (10) is grounded, VDS is applied to a drain electrode (11), and a gate voltage VGS is applied to a gate electrode (8), and at that time, an IDS-VGS curve is measured.
2. A ferroelectric camouflage transistor according to claim 1, wherein: the ferroelectric material layer (7) is BiFeO3, baTiO3, ferroelectric phase HfO2 and doping system thereof, PVDF, srBi2Ta2O9, pbZrxTi1-xO3, alScN or ferroelectric phase ZrO2 and doping system thereof.
3. A ferroelectric camouflage transistor according to claim 1 or 2, characterized in that: the active region comprises a channel layer (3), a source region (4) and a drain region (5), and a source electrode (10) and a drain electrode (11) which are respectively formed on the source region (4) and the drain region (5) are connected through metal wires and are used for applying and reading electrical signals.
4. A ferroelectric camouflage transistor according to claim 3, wherein: the channel layer (3) is a semiconductor which can exhibit bipolar properties.
5. A ferroelectric camouflage transistor according to claim 1 or 2, characterized in that: the transistor is compatible with a top gate structure, a FinFET structure, a nano ring gate structure, a three-dimensional vertical channel structure and a local back gate structure.
6. A ferroelectric camouflage transistor according to claim 1 or 2, characterized in that: the gate electrode (8) is titanium nitride, hafnium nitride, tantalum nitride, tungsten, nickel, titanium, gold, aluminum, polysilicon or ITO.
7. A ferroelectric camouflage transistor according to claim 1, wherein: the insulating layer (6) is an amorphous or paraelectric phase dielectric material.
8. A read-write mode of a ferroelectric camouflage transistor safety circuit according to any one of claims 1 to 7, wherein: the source (10) is grounded, VDS is applied to the drain (11), and simultaneously a gate voltage VGS is applied to the gate electrode (8), and the IDS-VGS curve at that time is measured.
9. The method of claim 8, wherein the step of writing and reading the ferroelectric camouflage transistor is performed by: the VDS is 0.05-3V, VGS is 0-3V, the device is in NMOS state, the device is changed from off state to on state along with the increase of VGS, when the grid voltage Vg=0, electron injection at the source electrode is closed, and at the drain electrode, hole injection from the drain electrode is inhibited due to further regulation and control of ferroelectric polarization on energy bands, and the transistor is in off state; if the ferroelectric layer is not introduced, the gate voltage is negative vg=0 and vd > 0 relative to the drain voltage, so that hole injection is generated at the drain, and the switching ratio of the device is seriously affected.
10. The method of claim 8, wherein the step of writing and reading the ferroelectric camouflage transistor is performed by: the VDS is-0.05 to-3V, VGS is 0 to-3V, the device is in a PMOS state, the device is changed from an off state to an on state along with VGS sweeping from 0 to-3V, when the grid voltage Vg=0, hole injection at the source electrode is closed, at the drain electrode, electron injection from the drain electrode is inhibited due to further regulation and control of ferroelectric polarization on energy bands, off-state current is reduced, and if no ferroelectric layer with ferroelectric property is introduced, electron injection is generated at the drain electrode due to the fact that the grid voltage is positive Vg=0 and Vd < 0 relative to the drain voltage, so that the switching ratio of the device is seriously affected.
CN202310077662.8A 2023-01-19 2023-01-19 Ferroelectric camouflage transistor and read-write mode of safety circuit thereof Active CN116207144B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916782A (en) * 2010-08-12 2010-12-15 复旦大学 Depression channel type transistor made of ferroelectric material and manufacturing method thereof
CN107204371A (en) * 2017-05-15 2017-09-26 北京大学 A kind of ferro-electric field effect transistor and preparation method thereof
CN109104880A (en) * 2016-04-01 2018-12-28 英特尔公司 The field effect transistor based on ferroelectricity with threshold voltage switching of on-state and off-state performance for enhancing
CN111312820A (en) * 2019-11-29 2020-06-19 中国科学院微电子研究所 Ferroelectric field effect transistor, three-dimensional memory and manufacturing method thereof
CN115472194A (en) * 2022-09-22 2022-12-13 北京大学 Method for realizing content addressable memory based on field effect transistor with bipolar characteristic

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11715797B2 (en) * 2019-08-27 2023-08-01 Micron Technology, Inc. Ferroelectric transistors and assemblies comprising ferroelectric transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916782A (en) * 2010-08-12 2010-12-15 复旦大学 Depression channel type transistor made of ferroelectric material and manufacturing method thereof
CN109104880A (en) * 2016-04-01 2018-12-28 英特尔公司 The field effect transistor based on ferroelectricity with threshold voltage switching of on-state and off-state performance for enhancing
CN107204371A (en) * 2017-05-15 2017-09-26 北京大学 A kind of ferro-electric field effect transistor and preparation method thereof
CN111312820A (en) * 2019-11-29 2020-06-19 中国科学院微电子研究所 Ferroelectric field effect transistor, three-dimensional memory and manufacturing method thereof
CN115472194A (en) * 2022-09-22 2022-12-13 北京大学 Method for realizing content addressable memory based on field effect transistor with bipolar characteristic

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