CN116206553A

CN116206553A - Line driving circuit and display screen

Info

Publication number: CN116206553A
Application number: CN202211699069.9A
Authority: CN
Inventors: 古涛; 扶伟; 周满城; 陈杰; 李荣荣
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-06-02

Abstract

The present disclosure relates to a line driving circuit and a display screen, wherein the line driving circuit comprises a line selection switch tube, a line signal supply end and a line signal control end, a first end of the line selection switch tube is connected with the line signal supply end, a control end of the line selection switch tube is connected with the line signal control end, a second end of the line selection switch tube is used for being connected with anodes of light emitting diodes of corresponding lines, the line driving circuit further comprises a bleeder circuit, and the bleeder circuit is connected with the line signal control end, the second end of the line selection switch tube and the ground; in a display stage, a row signal control end provides a first level to control a row selection switch tube to be conducted, and a bleeder circuit controls a second end of the row selection switch tube to be disconnected from the ground based on the first level; in the parasitic charge discharging stage, the row signal control end provides a second level to control the row selection switch tube to be disconnected, and the discharging circuit controls the conduction between the second end of the row selection switch tube and the ground based on the second level. The scheme can improve the upper afterglow phenomenon, thereby improving the display effect.

Description

Line driving circuit and display screen

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a row driving circuit and a display screen.

Background

In recent years, with the development of Mini-LEDs (Mini light emitting diodes), LED display screens have been increasingly widely applied, such as Smart wall (Smart tv wall), mini-LED tv, and so on, so that users have increasingly stringent requirements on display.

A common problem with LED displays today is the upper afterglow, which is literally understood to mean that there is an excess of light on the display that is lit. When a set of data is sent to the scan panel and displayed by the light panel, the LED that is theoretically not lit is lit and the more pronounced is the increase in refresh rate.

Disclosure of Invention

The invention aims to provide a row driving circuit and a display screen, which are used for improving the upper afterglow phenomenon and further improving the display effect.

The first aspect of the present disclosure provides a row driving circuit, where the row driving circuit includes a row selection switch tube, a row signal supply end, and a row signal control end, where a first end of the row selection switch tube is connected to the row signal supply end, a control end of the row selection switch tube is connected to the row signal control end, a second end of the row selection switch tube is used to connect to an anode of a light emitting diode in a corresponding row, and the row driving circuit further includes a bleeder circuit, where the bleeder circuit is connected to the row signal control end, the second end of the row selection switch tube, and ground;

in a display stage, a control end of the row selection switch tube responds to a first level provided by the row signal control end to control the connection between the first end and the second end of the row selection switch tube, and the bleeder circuit controls the disconnection between the second end of the row selection switch tube and the ground based on the first level provided by the row signal control end;

in a parasitic charge discharging stage, a control end of the row selection switch tube responds to a second level provided by the row signal control end to control disconnection between a first end and a second end of the row selection switch tube, and the discharging circuit controls conduction between the second end of the row selection switch tube and ground based on the second level provided by the row signal control end.

In one exemplary embodiment of the present disclosure, the bleeder circuit comprises:

the first end of the drain switch tube is grounded, and the second end of the drain switch tube is connected with the second end of the row selection switch tube;

the discharge control unit is connected with the row signal control end, the second end of the row selection switch tube and the control end of the discharge switch tube;

in a display stage, a control end of the row selection switch tube responds to a first level provided by the row signal control end, and controls conduction between a first end and a second end of the row selection switch tube so that the row level provided by the row signal supply end is written into the second end of the row selection switch tube, and the discharge control unit generates a disconnection level based on the first level provided by the row signal control end and the row level of the second end of the row selection switch tube and writes the disconnection level into the control end of the discharge switch tube so as to control disconnection between the first end and the second end of the discharge switch tube;

in a parasitic charge discharging stage, a control end of the row selection switch tube responds to a second level provided by the row signal control end to control disconnection between a first end and a second end of the row selection switch tube, the discharging control unit generates a conducting level based on the second level provided by the row signal control end and the row level of the second end of the row selection switch tube, and the conducting level is written into the control end of the discharging switch tube to control conduction between the first end and the second end of the discharging switch tube.

In an exemplary embodiment of the present disclosure, the row driving circuit further includes a first resistor having one end connected to the first end of the bleeder switching tube and the other end grounded.

In one exemplary embodiment of the present disclosure, the first resistor is an adjustable resistor.

In one exemplary embodiment of the present disclosure, in the row parasitic charge bleeding phase, when the level of the second end of the row selection switch tube is bled from the row level to a reference level, the bleeding control unit generates the off level based on the second level provided by the row signal control end and the reference level of the second end of the row selection switch tube;

wherein the reference level is a row normal off level.

In an exemplary embodiment of the present disclosure, the bleeder switch tube is an N-type MOS tube, the row selection switch tube is a P-type MOS tube, the first level and the off level are low levels, and the second level and the on level are high levels.

In one exemplary embodiment of the present disclosure, the bleed control unit includes a comparator and an and gate; the negative input end of the comparator is used for writing reference level, and the positive input end of the comparator is connected with the second end of the row selection switch tube;

the first input end of the AND gate is connected with the output end of the comparator, the second input end of the AND gate is connected with the row signal control end, and the output end of the AND gate is connected with the control end of the bleeder switch tube.

In one exemplary embodiment of the present disclosure, the bleed control unit includes: a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein the sum of the resistance values of the second resistor and the third resistor is determined based on a reference level;

one end of the second resistor and one end of the third resistor are connected with the base electrode of the first NPN transistor, the other end of the second resistor and the emitter electrode of the first NPN transistor are grounded, and the other end of the third resistor is connected with the second end of the row selection switch tube;

one end of the fourth resistor and one end of the fifth resistor are connected with a power supply voltage end, the other end of the fourth resistor, the collector of the first NPN transistor and the base of the second NPN transistor are connected with each other, the other end of the fifth resistor is connected with the collector of the second NPN transistor and the base of the third NPN transistor, the emitter of the second NPN transistor is grounded, the collector of the third NPN transistor is connected with the power supply voltage end, and the emitter of the third NPN transistor is connected with the collector of the fourth NPN transistor;

one end of the sixth resistor is grounded, the other end of the sixth resistor is connected with the emitter of the fourth NPN transistor and the control end of the bleeder switch tube, and the base electrode of the fourth NPN transistor is connected with the row signal control end.

In an exemplary embodiment of the present disclosure, the second resistor is an adjustable resistor, and the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are fixed resistors.

The second aspect of the present disclosure provides a display screen, including a lamp panel, a row driving chip and a column driving chip, where the lamp panel has a plurality of light emitting diodes arranged in an array along a row direction and a column direction, a plurality of scanning lines and a plurality of column data lines, each scanning line is connected to an anode of each light emitting diode in a row, each column data line is connected to a cathode of each light emitting diode in a column, and the column driving chip is connected to the plurality of column data lines, so as to provide a column level to the cathodes of the light emitting diodes in a corresponding column through the data lines; the row driving chip comprises a plurality of row driving circuits, wherein the second end of each row selecting switch tube of each row driving circuit is correspondingly connected with one row of scanning lines.

The beneficial effects of the present disclosure are:

in the scheme of the disclosure, a bleeder circuit is added into a row driving circuit, in a display stage, a control end of a row selection switch tube responds to a first level provided by a row signal control end, the first end and a second end of the row selection switch tube are controlled to be conducted, the bleeder circuit controls the second end of the row selection switch tube to be disconnected from the ground based on the first level provided by the row signal control end, and at the moment, the row level provided by a row signal supply end can be written into the second end of the row selection switch tube, namely: writing to the anode of the light emitting diode, and matching with the column level at the cathode of the light emitting diode to light the light emitting diode so as to realize display; during the row parasitic charge drain phase, namely: in the stage between the closing of the display of the current row and the opening of the display of the next row, the control end of the row selection switch tube responds to the second level provided by the control end of the row signal to control the disconnection between the first end and the second end of the row selection switch tube, and the bleeder circuit controls the conduction between the second end of the row selection switch tube and the ground based on the second level provided by the control end of the row signal, so that when the display of the next row is performed, the charge on the parasitic capacitance of the current row is sufficiently released, the voltage on the second end (namely, the anode of the light-emitting diode of the current row) of the row selection switch tube is reduced to lower voltage, and therefore, the light-emitting diode of the current row is not lightened by mistake when the display of the next row is performed, and the phenomenon of upper afterglow is eliminated.

In addition, the bleeder circuit and the row selection switch tube share the row signal control end, so that the display stage and the charge release stage can be realized without arranging an additional signal end, the number of control lines can be reduced, the wiring space is saved, more light emitting diodes can be conveniently designed in a limited space, and high PPI (pixel density unit) display is realized.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic view showing a part of the structure of a display screen according to a first embodiment of the present disclosure.

Fig. 2 is a schematic view showing a partial structure of another display screen mentioned in the first embodiment of the present disclosure.

Fig. 3 is a schematic view showing a part of a structure of still another display screen mentioned in the first embodiment of the present disclosure.

Fig. 4 is a schematic view showing a part of the structure of a display screen according to the second embodiment of the present disclosure.

Fig. 5 shows a timing diagram of the display screen mentioned in the embodiments of the present disclosure.

Reference numerals illustrate:

10. a lamp panel; 101. a light emitting diode; 102. a scanning line; 103. a data line; 11. a row driving chip; 110. a row driving circuit; 1101. a bleeder circuit; 12. a column driving chip;

p1, a row selection switch tube; n1, a bleeder switch tube; n2, a bleed-off control unit; v, comparator; AND gate; r1 to R6, first to sixth resistances; T1-T4, first-fourth NPN transistors; VCC, power supply voltage terminal; s, a row signal supply end; G. a row signal control end; C. parasitic capacitance, GND, ground; x, row direction; y, column direction.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.

In this disclosure, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Example 1

The first embodiment of the disclosure provides a display screen, which may be a Mini-LED, micro-LED (Micro-scale light emitting diode), OLED (organic light emitting diode) or the like.

Referring to fig. 1, the display screen may include a lamp panel 10, a row driving chip 11 and a column driving chip 12, the lamp panel 10 having a plurality of Light Emitting Diodes (LEDs) 101 arrayed in a row direction X and a column direction Y, a plurality of scanning lines 102 and a plurality of column data lines 103, each scanning line 102 being connected to an anode of each light emitting diode 101 in a row, each column data line 103 being connected to a cathode of each light emitting diode 101 in a column, the column driving chip 12 being connected to the plurality of column data lines 103 for providing a column level to a cathode of each light emitting diode 101 in a corresponding column; the row driving chip 11 may include a plurality of row driving circuits 110, where the row driving circuits 110 may include a row selection switch tube P1, a row signal supply terminal S and a row signal control terminal G, the first terminal of the row selection switch tube P1 is connected to the row signal supply terminal S, the control terminal of the row selection switch tube P1 is connected to the row signal control terminal G, the second terminal of each row selection switch tube P1 of the row driving circuits 110 is correspondingly connected to a row scan line 102 for connection to the anode of each light emitting diode 101 of the corresponding row, and the control terminal of the row selection switch tube P1 is used for responding to the level provided by the row signal control terminal G to control the connection or disconnection between the first terminal and the second terminal of the row selection switch tube P1, so as to control the connection or disconnection between the row signal supply terminal S and the anode of the light emitting diode 101, and when the connection between the first terminal and the second terminal of the row selection switch tube P1 is performed, the row level provided by the row signal supply terminal S may be written to the anode of the light emitting diode 101 of the corresponding row through the scan line 102 and matched with the column level at the cathode of the light emitting diode 101 to realize the display.

For example, referring to fig. 1, when scanning the nth row of LEDs, namely: when the control end of the n-th row of row selection switch tube P1 responds to the level signal Scan (n) provided by the row signal control end G to control the first end and the second end of the row selection switch tube P1 to be turned on, and when the row signal provided by the n-th row of row signal supply end S is written into the n-th row of Scan line 102, the voltage on the n-th row of Scan line 102 (i.e. the anode voltage of the n-th row of LEDs) is pulled up, and the column driving chip 12 controls the time when the data line 103 is pulled down, the corresponding LEDs display the response brightness, and at this time, the lit n-th row of LEDs, but because the row interval time is too short and the parasitic capacitance C exists in the n-1-th row (i.e. the previous row) of Scan line 102, the voltage on the n-1-th row of Scan line 102 is not completely discharged, so that the n-1-th row of Scan line 102 and the data line 103 form a discharge loop, and the n-1-th row of LEDs are mistakenly lit up, and an up-afterglow phenomenon occurs.

In order to solve the above afterglow phenomenon, referring to fig. 2, the row driving circuit 110 of the present embodiment may further include a bleeder circuit 1101, and the bleeder circuit 1101 is connected to the row signal control terminal G, the second terminal of the row selection switch tube P1, and the ground GND. This bleeder circuit 1101 can quickly release the charge on the parasitic capacitance C of the present row scan line 102 at a stage between the turn-off of the present row's corresponding LED and the turn-on of the downstream corresponding LED, and it should be understood that the LED-on stage of the present row is defined as a display stage, and the stage between the turn-off of the present row's corresponding LED and the turn-on of the downstream corresponding LED can be defined as a row parasitic charge bleeder stage of the present row.

In the display stage, the control terminal of the row selection switch tube P1 responds to the first level provided by the row signal control terminal G to control the conduction between the first terminal and the second terminal of the row selection switch tube P1, and the bleeder circuit 1101 controls the disconnection between the second terminal of the row selection switch tube P1 and the ground based on the first level provided by the row signal control terminal G, at this time, the row level provided by the row signal supply terminal S may be written into the second terminal of the row selection switch tube P1, that is: writing to the anode of the light emitting diode 101, and matching with the column level at the cathode of the light emitting diode 101 to light the light emitting diode 101 so as to realize display; during the row parasitic charge drain phase, namely: in the stage between the closing of the present line display and the opening of the next line display, the control end of the line selection switch tube P1 responds to the second level provided by the line signal control end G to control the disconnection between the first end and the second end of the line selection switch tube P1, and the bleeder circuit 1101 controls the conduction between the second end of the line selection switch tube P1 and the ground GND based on the second level provided by the line signal control end G, so that the charge on the parasitic capacitance C of the present line is sufficiently released during the next line display, and the voltage on the second end of the line selection switch tube P1 (i.e., the anode of the present line light emitting diode 101) is reduced to a lower voltage, so that the light emitting diode 101 of the present line is not turned on by mistake during the next line display, and the phenomenon of upper afterglow is eliminated.

In addition, the bleeder circuit 1101 and the row selection switch tube P1 of the present application share the row signal control end G, so that the display stage and the charge release stage can be realized without setting an additional signal end, thereby reducing the number of control lines, saving the wiring space, and facilitating the design of more light emitting diodes 101 in a limited space, so as to realize high PPI (pixel density unit) display.

As shown in fig. 3, the bleeder circuit 1101 may include a bleeder switch tube N1 and a bleeder control unit N2, wherein a first end of the bleeder switch tube N1 is grounded GND, and a second end of the bleeder switch tube N1 is connected to a second end of the row selection switch tube P1; the drain control unit N2 is connected to the row signal control terminal G and to the second terminal of the row selection switch tube P1, and to the control terminal of the drain switch tube N1.

In the display stage, the control end of the row selection switch tube P1 responds to the first level provided by the row signal control end G to control the connection between the first end and the second end of the row selection switch tube P1, so that the row level provided by the row signal supply end S is written into the second end of the row selection switch tube P1, and the drain control unit N2 generates an off level based on the first level provided by the row signal control end G and the row level of the second end of the row selection switch tube P1, and writes the off level into the control end of the drain switch tube N1 to control the disconnection between the first end and the second end of the drain switch tube N1.

In the parasitic charge discharging stage, the control end of the row selection switch tube P1 responds to the second level provided by the row signal control end G to control the disconnection between the first end and the second end of the row selection switch tube P1, the discharging control unit N2 generates a conducting level based on the second level provided by the row signal control end G and the row level of the second end of the row selection switch tube P1, and the conducting level is written into the control end of the discharging switch tube N1 to control the conduction between the first end and the second end of the discharging switch tube N1.

In this embodiment, the on/off of the bleeder switch N1 is implemented based on the level provided by the row signal control terminal G and the second terminal of the row selection switch P1, that is, the duration of the row parasitic charge bleeder phase is not only related to the level provided by the row signal control terminal G, but also related to the level provided by the second terminal of the row selection switch P1 (i.e., the level on the current row scan line 102), so that the phenomena of caterpillars are avoided, where caterpillars refer to: if one LED breaks down in the display screen, other lamps in the column where the lamp is positioned are always in a high-brightness display state, and the LED lamps in the column form an abnormal lamp column with non-uniform brightness, which is similar to a caterpillar.

Illustratively, in the row parasitic charge discharging phase, when the level of the second end of the row selection switch tube P1 is discharged from the row level to the reference level Vref, the discharging control unit N2 generates an off level based on the second level provided by the row signal control end G and the reference level Vref of the second end of the row selection switch tube P1 to control the discharging switch tube N1 to be turned off, so that the caterpillar phenomenon can be avoided, and it should be understood that this reference level Vref may be a row normal off level, that is: the present row of LEDs is at a level corresponding to the off state, and the row level provided to the LED anode by the row signal supply terminal S is a normal row on level, which is a level signal higher than the reference level Vref.

As shown in fig. 3, the bleeder switch N1 may be an N-type MOS transistor, and the row selection switch P1 may be a P-type MOS transistor, and the first level and the off level are low, and the second level and the on level are high.

The bleed control unit N2 of the present embodiment may include a comparator V AND an AND gate AND; the negative input end of the comparator V is used for writing a reference level Vref, and the positive input end of the comparator V is connected with the second end of the row selection switch tube P1; the first input end of the AND gate AND is connected with the output end of the comparator V, the second input end of the AND gate AND is connected with the row signal control end G, AND the output end of the AND gate AND is connected with the control end of the bleeder switch tube N1.

For example, as shown in fig. 5, in the display stage t1 of the n-1 row, the signal Scan (n-1) provided by the row signal control terminal G of the n-1 row is at a low level to control the row selection switch tube P1 of the n-1 row to be turned on, so that the row level provided by the row signal supply terminal S of the n-1 row is written into the Scan line 102 of the n-1 row to control the LED of the n-1 row to be lighted for display, at this time, the level of the second terminal of the row selection switch tube P1 of the n-1 row is at a row level, the positive input terminal of the comparator V of the n-1 row is written into the row level, and since the row level is higher than the reference level Vref, the output terminal of the comparator V of the n-1 row outputs a high level, namely: the level written in the first input terminal of the AND gate AND of the N-1 th row is high, AND since the signal Scan (N-1) supplied from the row signal control terminal G of the N-1 th row is low, the second input terminal of the AND gate AND of the N-1 th row is also low, AND when the first input terminal of the AND gate AND of the N-1 th row is high AND the second input terminal is low, the output terminal of the AND gate AND of the N-1 th row is low, so that the bleeder switch tube N1 of the N-1 th row is turned off, that is: at this time, the bleeder circuit 1101 of the n-1 line is in a non-bleeder state to avoid affecting the normal display.

As shown in fig. 5, at the row parasitic charge bleeding phase t2 of row n-1, namely: in the phase between the display phase t1 of the n-1 th row and the display phase t3 of the n-1 th row being turned on, the signal Scan (n-1) provided by the row signal control terminal G of the n-1 th row is at a high level to control the row selection switch transistor P1 to be turned off, and when the discharging operation is just started, the row level of the second terminal of the row selection switch transistor P1 is higher than the reference level Vref, so that the output terminal of the comparator V of the n-1 th row outputs a high level, that is: the level written in the first input terminal of the AND gate AND of the N-1 th row is high, AND since the signal provided by the row signal control terminal G of the N-1 th row is high, the second input terminal of the AND gate AND of the N-1 th row is also high, AND when the first input terminal of the AND gate AND of the N-1 th row is high, the output terminal of the AND gate AND of the N-1 th row is high, so that the bleeder switch tube N1 of the N-1 th row is turned on, that is: at this time, the bleeder circuit 1101 of the n-1 row is in a bleeder state, and the charge of the parasitic capacitor C on the scan line 102 of the n-1 row is rapidly discharged to the ground.

It should be understood that, during the discharging process, if the level of the second end of the N-1 th row selecting switch tube P1 is higher than the reference level Vref, the N-1 th row discharging switch tube N1 is still in the on state, and the discharging is continued, and when the level of the second end of the N-1 th row selecting switch tube P1 is discharged from the row level to the reference level Vref, namely: after the discharge is finished, the output end of the comparator V of the n-1 row outputs a low level, namely: the level written in the first input terminal of the AND gate AND of the N-1 th row is low, AND since the signal supplied from the row signal control terminal G of the N-1 th row is high, the second input terminal of the AND gate AND of the N-1 th row is also high, AND when the first input terminal of the AND gate AND of the N-1 th row is low AND the second input terminal is high, the output terminal of the AND gate AND of the N-1 th row is low, so that the bleeder switching tube N1 of the N-1 th row is turned off.

Note that, in fig. 5, scan (n-1) is a signal provided by the Row signal control terminal G of the n-1 th Row, scan (n) is a signal provided by the Row signal control terminal G of the n-1 th Row, row (n-1) is a signal on the Scan line 102 of the n-1 th Row, and it can be seen from fig. 5 that the level on the Scan line 102 of the n-1 th Row is not completely discharged to the Row normal off level in the t2 stage of the bleeder circuit 1101, so that the upper afterglow phenomenon is easy to occur, and the level on the Scan line 102 of the n-1 th Row is completely discharged to the Row normal off level in the t2 stage of the bleeder circuit 1101, so that the upper afterglow phenomenon is avoided.

As shown in fig. 3, the row driving circuit 110 may further include a first resistor R1, wherein one end of the first resistor R1 is connected to the first end of the bleeder switch N1, and the other end is grounded GND, wherein the discharging time of the bleeder circuit 1101 depends on the resistance value of the first resistor R1.

Because the parasitic capacitance C generated on the scan line 102 is different for different products, in order to adapt to the different products, the first resistor R1 of the embodiment is an adjustable resistor, and the discharging time of the discharging circuit 1101 can be adjusted by adjusting the resistance value of the first resistor R1 so as to match the products with different refresh rates and different items.

For example, the resistance of the first resistor R1 can be adjusted by a register in the row driving chip 11, and when designing, a default value, such as 10 ohms, can be set for the first resistor R1, and then the parasitic capacitance C can be calculated according to the actual project, so as to determine the actually required resistance at the first resistor R1, and then converted into a code to be written into the corresponding register.

Example two

The main difference between the present embodiment and the first embodiment is that the structure of the bleed control unit N2 is different, and other structures can refer to the content of the first embodiment, and the description thereof will not be repeated here.

Specifically, as shown in fig. 4, the bleeder control unit N2 of the present embodiment includes a first NPN transistor T1, a second NPN transistor T2, a third NPN transistor T3, a fourth NPN transistor T4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, wherein the sum of the resistance values of the second resistor R2 and the third resistor R3 is determined based on a reference level Vref (i.e., a normal line-off level).

As shown in fig. 4, one end of the second resistor R2 and one end of the third resistor R3 are connected to the base of the first NPN transistor T1, the other end of the second resistor R2 and the emitter of the first NPN transistor T1 are grounded GND, and the other end of the third resistor R3 is connected to the second end of the row selection switch tube P1; one end of the fourth resistor R4 and one end of the fifth resistor R5 are connected with a power supply voltage end VCC, the other end of the fourth resistor R4, a collector of the first NPN transistor T1 and a base of the second NPN transistor T2 are connected with each other, the other end of the fifth resistor R5 is connected with a collector of the second NPN transistor T2 and a base of the third NPN transistor T3, an emitter of the second NPN transistor T2 is grounded GND, a collector of the third NPN transistor T3 is connected with the power supply voltage end VCC, and an emitter of the third NPN transistor T3 is connected with a collector of the fourth NPN transistor T4; one end of the sixth resistor R6 is grounded GND, the other end of the sixth resistor R6 is connected to the emitter of the fourth NPN transistor T4 and the control end of the bleeder switch N1, and the base of the fourth NPN transistor T4 is connected to the row signal control end G.

It should be appreciated that the voltage provided by the supply voltage terminal VCC is high.

As shown in fig. 5, in the display stage T1 of the N-1 row, the signal Scan (N-1) provided by the row signal control terminal G of the N-1 row is at a low level to control the row selection switch transistor P1 of the N-1 row to be turned on, so that the row level provided by the row signal supply terminal S of the N-1 row is written to the Scan line 102 of the N-1 row to control the LED of the N-1 row to be turned on for display, at this time, the level of the second terminal of the row selection switch transistor P1 of the N-1 row is at a row level higher than the reference level Vref corresponding to the sum of the resistances of the second resistor R2 and the third resistor R3 in the N-1 row, and at this time, the first NPN transistor T1 is turned on, the second NPN transistor T2 is turned off, and the third NPN transistor T3 is turned on, and when the signal Scan (N-1) provided by the row signal control terminal G of the N-1 row is at a low level, the fourth transistor T4 is turned off, so that the drain terminal of the N-1 row switch transistor N is turned on to ground: at low level, the bleeder switching tube N1 is open, i.e.: at this time, the bleeder circuit 1101 of the n-1 line is in a non-bleeder state to avoid affecting the normal display.

As shown in fig. 5, at the row parasitic charge bleeding phase t2 of row n-1, namely: in the period between the display period T1 of the N-1 row and the display period T3 of the N-1 row being turned on, the signal Scan (N-1) provided by the row signal control terminal G of the N-1 row is at a high level to control the row selection switch transistor P1 to be turned off, when the discharging operation is just started, the row level of the second terminal of the row selection switch transistor P1 is higher than the reference level Vref, at this time, the first NPN transistor T1 is turned on, the second NPN transistor T2 is turned off, the third NPN transistor T3 is turned on, and when the signal Scan (N-1) provided by the row signal control terminal G of the N-1 row is at a high level, the fourth NPN transistor T4 is turned on, so that the control terminal of the discharging switch transistor N1 of the N-1 row is connected to the power supply voltage terminal VCC, namely: the power supply voltage end VCC provides high level for the control end of the N-1 row bleeder switch tube N1, and the bleeder switch tube N1 is conducted, namely: at this time, the bleeder circuit 1101 of the n-1 row is in a bleeder state, and the charge of the parasitic capacitor C on the scan line 102 of the n-1 row is rapidly discharged to the ground.

It should be understood that, during the discharging process, the signal Scan (N-1) provided by the row signal control terminal G of the N-1 row is at a high level, the fourth NPN transistor T4 is turned on, if the level of the second terminal of the row selection switch tube P1 of the N-1 row is higher than the reference level Vref, the discharging switch tube N1 of the N-1 row is still in a conductive state, and the discharging is continued, when the level of the second terminal of the row selection switch tube P1 of the N-1 row is discharged from the row level to the reference level Vref, that is: after the discharge is completed, at this time, the first NPN transistor T1 is turned off, the second NPN transistor T2 is turned on, and the third NPN transistor T3 is turned off, so that the control terminal of the bleeder switching transistor N1 of the N-1 th row is grounded, that is: at low level, the bleeder switching tube N1 is open, i.e.: at this time, the bleeder circuit 1101 of the n-1 line is in a non-bleeder state to avoid affecting the normal display. In this embodiment, the second resistor R2 and the third resistor R3 play a role in voltage division, and the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 play a role in protection, so that the whole discharge control unit N2 is protected, and the stability of the row driving circuit 110 is improved.

For example, the second resistor R2 is an adjustable resistor, and since the normal closing voltages of the rows corresponding to different products are different, the resistance value of the second resistor R2 can be adjusted according to the actual products by designing the second resistor R2 as an adjustable resistor, so that the adaptability of the row driving circuit 110 is improved; the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 can be fixed resistors, so that the cost is reduced.

In the description of the present specification, a description of the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, which is therefore intended to be within the scope of the present disclosure as defined by the claims and specification.

Claims

1. The line driving circuit comprises a line selection switch tube, a line signal supply end and a line signal control end, wherein a first end of the line selection switch tube is connected with the line signal supply end, a control end of the line selection switch tube is connected with the line signal control end, and a second end of the line selection switch tube is used for being connected with anodes of light emitting diodes of corresponding lines;

2. The row driver circuit of claim 1, wherein the bleeder circuit comprises:

3. The row driver circuit of claim 2, further comprising a first resistor having one end connected to the first end of the bleeder switch tube and the other end grounded.

4. A row driver circuit according to claim 3, wherein the first resistor is an adjustable resistor.

5. The row driving circuit according to any one of claims 1 to 4, wherein,

in the parasitic charge discharging stage, when the level of the second end of the row selection switch tube is discharged from the row level to a reference level, the discharging control unit generates the disconnection level based on the second level provided by the row signal control end and the reference level of the second end of the row selection switch tube;

wherein the reference level is a row normal off level.

6. The row driver circuit of claim 5, wherein the bleeder switch is an N-type MOS transistor, the row select switch is a P-type MOS transistor, the first level and the off level are low, and the second level and the on level are high.

7. The row driver circuit of claim 6, wherein the bleed control unit comprises a comparator and an and gate; the negative input end of the comparator is used for writing reference level, and the positive input end of the comparator is connected with the second end of the row selection switch tube;

8. The row drive circuit of claim 6, wherein the bleed control unit comprises: a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein the sum of the resistance values of the second resistor and the third resistor is determined based on a reference level;

9. The row driver circuit of claim 8, wherein the second resistor is an adjustable resistor, and the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are fixed resistors.

10. The display screen comprises a lamp panel, a row driving chip and a column driving chip, wherein the lamp panel is provided with a plurality of light emitting diodes, a plurality of rows of scanning lines and a plurality of columns of data lines, the light emitting diodes are arrayed along the row direction and the column direction, each row of scanning lines is connected with anodes of the light emitting diodes in one row, each column of data lines is connected with cathodes of the light emitting diodes in one column, and the column driving chip is connected with the plurality of columns of data lines and is used for providing column levels for cathodes of the light emitting diodes in the corresponding column through the data lines; the line driving chip comprising a plurality of line driving circuits according to any one of claims 1 to 9, wherein a second end of a line selection switching tube of each of the line driving circuits is connected to a corresponding one of the scanning lines.