CN116206546A - Pixel circuit and display panel - Google Patents

Abstract

The invention discloses a pixel circuit and a display panel. The pixel circuit comprises a light emitting module connected between a first power supply and a second power supply; a driving transistor connected between the first power supply and the light emitting module, the driving transistor including a first gate and a second gate; the initialization module is connected between the initialization line and the first grid electrode; the second grid is used for inputting a first bias control signal in an initial stage and inputting a second bias control signal in a brightness maintaining stage; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal. The technical scheme provided by the embodiment of the invention solves the problem that the display panel has screen flicker.

Description

Pixel circuit and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit and a display panel.

Background

With the development of display technology, the requirements of people on the display technology are also increasing, and the display panel is required to realize the picture display with lower driving frequency. When the conventional display panel displays pictures at a low frequency, a screen body flickers, and the display effect of the display panel is affected.

Disclosure of Invention

The invention provides a pixel circuit and a display panel, which are used for solving the problem that a screen body flickers when the display panel displays pictures at a lower frequency.

According to an aspect of the present invention, there is provided a pixel circuit including:

the light-emitting module is connected between the first power supply and the second power supply;

a driving transistor connected between the first power supply and the light emitting module, the driving transistor including a first gate and a second gate;

the initialization module is connected between the initialization line and the first grid electrode;

the second grid is used for inputting a first bias control signal in an initial stage and inputting a second bias control signal in a brightness maintaining stage; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal.

Optionally, the pixel circuit further includes:

the initialization module comprises a first initialization module, a first pole of the first initialization module is connected with a first grid electrode of the driving transistor, and a second pole of the first initialization module is connected with a second pole of the driving transistor;

the first initialization module comprises a third grid electrode and a fourth grid electrode; the third grid is used for inputting a first light-emitting control signal;

the fourth grid is used for inputting a first light-emitting control signal; alternatively, the fourth gate is used to input the first bias control signal in the initial stage and to input the second bias control signal in the brightness maintaining stage.

Optionally, when the screen is displayed in the first frequency range, the second gate and/or the fourth gate is configured to input the first bias control signal in an initial stage and input the second bias control signal in a brightness maintaining stage;

preferably, the first frequency range comprises frequencies less than 60 Hz.

Optionally, the voltage of the first bias control signal is constant;

at least one of the voltage of the second bias control signal is constant, the voltage gradually decreases, or the voltage is pulsed.

Optionally, the voltage of the second bias control signal input to the second gate and/or the fourth gate is linearly decreased; or alternatively, the process may be performed,

the second gate and/or the fourth gate are configured such that the duty ratio of the inputted second bias control signal is equal or gradually reduced.

Optionally, the luminance maintenance phase includes N sub-emission periods;

the second gate and/or the fourth gate is configured such that the voltage of the second bias control signal input in each sub-emission period gradually decreases, and the voltage amplitude of the second bias control signal input in the (i+1) th sub-emission period is smaller than the voltage amplitude of the second bias control signal transmitted in the (i) th sub-emission period;

wherein N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

Optionally, the luminance maintenance phase includes N sub-emission periods;

the second gate and/or the fourth gate is configured such that a voltage amplitude of the second bias control signal input in the j+1th sub-emission period is greater than a voltage amplitude of the second bias control signal input in the j-th sub-emission period and is equal to a voltage amplitude of the second bias control signal transmitted in the j-1 th sub-emission period;

wherein N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

Optionally, the initializing module further includes:

a second initialization module;

the first pole of the second initialization module is connected with the anode of the light-emitting module, and the second pole of the second initialization module is connected with the initialization line;

the second initialization module comprises a fifth grid electrode and a sixth grid electrode;

the fifth gate is used for inputting a second light-emitting control signal, and the sixth gate is used for inputting a first light-emitting control signal.

In a second aspect, an embodiment of the present invention provides a display panel, including: the pixel circuit as set forth in any of the first aspects.

Optionally, the display panel further includes:

at least one first bias line extending along a first direction, the first bias line being for connecting a second gate of the pixel circuit;

at least one switch module connected between the first bias line and the second gate of the pixel circuit;

the second grid electrodes of the pixel circuits positioned in the same column are connected with the same first bias line along the first direction;

along the second direction, the control signals input by the control ends of the switch modules positioned in two adjacent rows are different; wherein the second direction intersects the first direction.

According to the technical scheme, the pixel circuit comprises a light emitting module and a driving transistor, wherein the driving transistor comprises a first grid electrode and a second grid electrode, the second grid electrode is used for inputting a first bias control signal in an initial stage and inputting a second bias control signal in a brightness maintaining stage; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal. The arrangement is such that the pixel circuit receives the second bias control signal of smaller amplitude in the luminance maintaining phase, the variation of the driving current of the pixel circuit is smaller. When the display panel displays pictures with lower frequency, the driving current of the pixel driving circuit can be kept consistent, and the display effect of the display panel is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of driving a pixel circuit according to an embodiment of the present invention;

FIG. 4 is a timing diagram of driving another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 7 is a timing diagram of driving another pixel circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As mentioned in the background art, there is a problem in that a screen flickers when a picture is displayed at a low frequency. The inventor finds that the minimum refresh rate of LTPO (Low Temperature Polycrystalline Oxide, low-temperature polycrystalline oxide) screen technology can be 1Hz, and lower refresh rate can bring lower power consumption, and a large amount of electric quantity is saved by reducing the refresh rate. When the LTPO panel displays a picture at a low frequency, for example, 1Hz or even 0.1Hz, data is written into the pixel circuit of the display panel at 60Hz, and the characteristics of the driving transistor of the pixel circuit are easily changed, so that the driving current is changed, which causes a problem of flicker of the panel.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 1, a display device 200 includes a display panel 100. The display panel 100 includes a plurality of pixel circuits 1.

The display panel 100 may further include a plurality of Scan lines Scan 1-Scan n, a plurality of Data lines Data1-Data n, a plurality of light emission control lines EM 1-EM n, and a driving chip 300, wherein the pixel circuit 1 is disposed in a region defined by the intersection of the Scan lines and the Data lines, the Scan signals are input to the corresponding pixel circuit 1 through the Scan lines, the pixel circuit 1 is connected to the Data lines electrically connected thereto under the action of the Scan signals input to the Scan lines electrically connected thereto, the driving chip 300 inputs the Data signals to the corresponding pixel circuit 1 through the Data lines, the voltage of the Data signals corresponds to the driving voltage, and the light emission brightness of the light emitting module is determined, that is, the display gray scale of the light emitting module is determined.

The light emitting modules may include light emitting modules that emit light of different colors. In the present application, a light emitting module with a red light emitting color, a light emitting module with a green light emitting color, and a light emitting module with a blue light emitting color are described as examples, and the light emitting module may include light emitting modules with other colors, which is not limited in any way.

The display panel 100 further includes an initialization line Vref. Each pixel circuit 1 is connected to a first power supply line VDD, a second power supply line VSS, and an initialization line Vref, respectively. The first power line VDD is used to transmit a first voltage signal, which is typically a high level signal, to the anode of the light emitting module. The second power line VSS is used to transmit a second voltage signal, which is typically a low level signal, to the cathode of the light emitting module. Referring to fig. 1, the display panel 100 further includes a first bias line Vini for transmitting a first bias control signal to the pixel circuit 1.

The pixel circuit 1 may include a plurality of thin film transistors and a memory module. The thin film transistor may include a driving transistor and a switching transistor. The driving transistor and the light emitting module are sequentially connected between the first power line VDD and the second power line VSS. The driving transistor may generate a driving current to drive the light emitting module connected to the pixel circuit 1 to emit light. The switching transistor then mainly plays a switching role.

Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Fig. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention. Fig. 4 is a driving timing chart of another pixel circuit according to an embodiment of the present invention. Referring to fig. 1 to 4, the pixel circuit 1 provided in this embodiment includes a light emitting module D1, where the light emitting module D1 is connected between a first power supply VDD and a second power supply VSS; the driving transistor M1, the driving transistor M1 is connected between the first power supply VDD and the light emitting module D1. The driving transistor M1 includes a first gate and a second gate; the initialization module 2 is connected between the initialization line Vref and the first grid electrode; the second grid is used for inputting a first bias control signal in an initial stage t1 and inputting a second bias control signal in a brightness maintaining stage t 2; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal.

Specifically, the light emitting module D1 emits light by being driven by a driving circuit, which may be, for example, the driving circuit shown in fig. 2. Referring to fig. 1 to 4, the pixel circuit 1 provided in the present embodiment may correspond to one specific circuit structure of the pixel circuit 1 in the display panel 100 shown in fig. 1. Referring to fig. 1 and 2, the pixel circuit 1 includes a driving transistor M1, an initializing module 2, a data writing module 3, a light emission control module 5, and a memory module 4.

The operation of the pixel circuit 1 includes an initial stage t1 and a luminance maintaining stage t2. The initial stage T1 includes an initialization stage T1, a data writing stage T2, and a subthreshold swing compensation stage T3. The luminance maintenance period T2 includes a light-emitting period T4.

Referring to fig. 3, in the initialization phase T1, the first light emitting control line EM1 is at a high level, the second light emitting control line EM2 is at a low level, the initialization module 2 is turned on, and the initialization line Vref transmits an initialization signal to the gate G of the driving transistor M1 and the anode of the light emitting module D1. The total time of the initialization period T1 is the overlapping time of the light-emitting signal of the second light-emitting control signal EM1 and the off signal of the first light-emitting control signal EM2 before the data writing period T2. The time of initialization may be adjusted by timing.

In the data writing stage T2, the first light emission control line EM1 and the second light emission control line EM2 are both at a high level, the Scan signal Scan is at a low level, the initialization module 2 and the data writing module 3 are both turned on, and the data voltage is written to the gate G of the driving transistor M1 through the turned-on data writing module 3 and the initialization module 2. The total time of the data writing phase T2 is the time of the blanking signal of the Scan signal Scan before the sub-threshold swing compensation phase T3.

In the sub-threshold swing compensation phase T3, the Scan signal Scan is at a high level, the data writing module 3 is turned off, the first light emitting control line EM1 is at a high level, the initializing module 2 is turned on, and the driving transistor M1 continues to charge the gate G. The voltage at the S point of the driving transistor M1 is maintained by the memory module 4 so that the driving transistor M1 can continue to charge the gate G to compensate the threshold voltage Vth of the driving transistor M1. The compensation time can be adjusted by timing as needed.

In the light emitting stage T4, the first light emitting control line EM1 and the second light emitting control line EM2 are both low, the light emitting control module 5 is turned on, the driving transistor M1 is turned on, and the light emitting module D1 emits light.

Referring to fig. 4, the second gate of the driving transistor M1 of the pixel circuit 1 provided in the present embodiment is used to input the first bias control signal in the initial stage t1 and to input the second bias control signal in the luminance maintaining stage t2. The second gate of the driving transistor M1 is connected to a first bias line Vini for providing a bias control signal to the second gate of the driving transistor M1 of the pixel circuit 1. When the pixel circuit 1 displays a picture on the display panel, the first bias line Vini transmits the first bias control signal to the second gate electrode in the initial stage t1, and transmits the second bias control signal to the second gate electrode in the luminance maintaining stage t2. At least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal.

Specifically, the pixel circuit 1 includes a light emitting module D1 and a driving circuit. The pixel circuit 1 writes data to the gate G of the driving transistor M1 of the driving circuit in an initial stage t1 in response to the scan signal and the data signal, and keeps the light emitting module D1 stably emitting light in a luminance keeping stage t2. The first bias line Vini provides a bias control signal for the pixel circuit 1, and the bias control signal adjusts the magnitude of the driving current transmitted to the light emitting module D1 by the driving circuit by adjusting the threshold voltage of the driving transistor. The arrangement is such that the variation of the driving current in the luminance maintaining period t2 is small, so that the uniformity of the light emitting luminance of the light emitting module D1 is good, and the problem of flicker when the display panel displays a picture in a frequency range with a low driving frequency is solved.

Since the characteristics of the driving transistor of the pixel circuit 1 are easily changed in a frequency range where the driving frequency is low, the magnitude of the threshold voltage of the driving transistor is gradually increased with the increase of the light emission time, so that the driving current flowing through the driving transistor is gradually reduced, and thus the light emission luminance of the light emitting module D1 is reduced. By setting the pixel circuit 1, when displaying a picture, the second gate inputs the first bias control signal in the initial stage t1 and inputs the second bias control signal in the luminance maintaining stage t2, at least part of the second bias control signal has a smaller amplitude than the first bias control signal. The arrangement is such that in an initial phase t1 the light emitting module D1 of the pixel circuit 1 receives a first bias control signal of larger amplitude. In the luminance maintaining period t2, the magnitude of the threshold voltage of the driving transistor M1 gradually increases. By setting the bias control signal with larger amplitude, the fluctuation of the threshold voltage of the driving transistor M1 is reduced, so that the fluctuation of the driving current is reduced, the driving current is as consistent as possible in the brightness maintaining stage t2, the brightness uniformity of the display panel in the first frequency range is improved, and the display effect of the display panel is improved.

According to the technical scheme, the pixel circuit comprises a light emitting module and a driving transistor, wherein the driving transistor comprises a first grid electrode and a second grid electrode, the second grid electrode is used for inputting a first bias control signal in an initial stage and inputting a second bias control signal in a brightness maintaining stage; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal. The arrangement is such that the pixel circuit receives the second bias control signal of smaller amplitude in the luminance maintaining phase, the variation of the driving current of the pixel circuit is smaller. When the display panel displays pictures with lower frequency, the driving current of the pixel driving circuit can be kept consistent, and the display effect of the display panel is improved.

Optionally, fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 5 and 6, the initialization module 2 provided in this embodiment includes: a first initialization module 21; a first pole of the first initialization module 21 is connected to the first gate of the driving transistor M1, and a second pole of the first initialization module 21 is connected to the second pole of the driving transistor M1; the first initialization module 21 includes a third gate and a fourth gate; the third grid is used for inputting a first light-emitting control signal; referring to fig. 5, the fourth gate electrode is used to input the first light emitting control signal; alternatively, referring to fig. 6, the fourth gate is used to input the second bias control signal.

In an alternative embodiment, referring to fig. 5, the fourth gate electrode of the first initialization module 21 may be connected to the first light emitting control line EM1. The third grid electrode and the fourth grid electrode of the first initialization module 21 are connected with the same first light emitting control line EM1, wiring is convenient, driving process is simple, and implementation is easy.

Optionally, with continued reference to fig. 5, the pixel circuit 1 of the display panel provided in the embodiment of the present invention includes: the light emitting module D1 is connected between a first power supply VDD and a second power supply VSS; a driving transistor M1 connected between the first power supply VDD and the light emitting module D1 to control a driving current, the driving transistor M1 including a first gate and a second gate; the memory module 4, the memory module 4 connects the first grid of the driving transistor M1. The first bias line Vini is connected to the second gate electrode, and the second gate electrode inputs the first bias control signal in the initial stage t1 and the second bias control signal in the luminance maintaining stage t2.

Specifically, when the driving frequency is within the first frequency range during the display of the display panel, the threshold voltage of the driving transistor M1 is negatively biased during the luminance maintaining period t2, and the magnitude of the threshold voltage of the driving transistor M1 is gradually increased. The longer the luminance maintaining period t2 lasts, the larger the amplitude fluctuation of the threshold voltage of the driving transistor M1 will be. Since at least part of the second bias control signal has a smaller amplitude than the first bias control signal, the first bias control signal is input in the initial stage t1 by setting the second gate, and the second bias control signal is input in the luminance maintaining stage t2. The arrangement is such that the second gate inputs the first bias control signal having a larger amplitude in the initial stage t1, so that the data signal can be written into the first gate of the driving transistor M1 in the initial stage t 1.

In the luminance maintaining period t2, the magnitude of the threshold voltage of the driving transistor M1 gradually increases. By inputting the second bias control signal to the second gate electrode of the driving transistor M1 in the brightness maintaining stage t2, the bias control signal with larger amplitude acts on the second gate electrode of the driving transistor M1, so that the fluctuation of the threshold voltage of the driving transistor M1 is reduced, and the fluctuation of the driving current is reduced, so that the driving current is consistent as much as possible in the brightness maintaining stage t2, and the uniformity of the display brightness of the display panel 100 in the first frequency range with lower driving frequency is better, and the display effect of the display panel 100 is further improved.

In another alternative embodiment, referring to fig. 6, the display panel further includes a second bias line Vini2, and the fourth gate of the first initialization module 21 may be connected to the second bias line Vini2. The fourth gate of the first initialization module 21 inputs the second bias control signal.

Alternatively, fig. 7 is a driving timing diagram of another pixel circuit according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 6 and 7, when the fourth gate of the first initialization module 21 is connected to the second bias line Vini2, the fourth gate of the first initialization module 21 inputs the first bias control signal in the initial stage t1 and inputs the second bias control signal in the brightness maintaining stage t2.

Specifically, the first initialization module 21 may include a first transistor M3, and the first transistor M3 may include an Indium Gallium Zinc Oxide (IGZO) transistor. Since the threshold voltage of the IGZO transistor is also easily biased positively and negatively, the first initialization module 21 is connected to the first gate of the driving transistor M1, and the fluctuation of the threshold voltage of the first transistor M3 is easily coupled to the voltage affecting the first gate of the driving transistor M1. The first bias control signal is input in the initial stage t1 and the second bias control signal is input in the luminance maintaining stage t2 by setting the fourth gate of the first initialization module 21. The bias control signal with larger amplitude can be applied to the fourth grid electrode of the first initialization module 12, so that fluctuation of the threshold voltage of the first initialization module 12 is reduced, coupling of the first initialization module 12 to the first grid electrode of the driving transistor M1 is consistent, fluctuation of the voltage of the first grid electrode of the driving transistor M1 connected with the first pole of the first initialization module 12 is small, driving current is consistent as much as possible in a brightness maintaining stage t2, uniformity of display brightness of the display panel in a first frequency range with lower driving frequency is good, and display effect of the display panel is further improved.

Optionally, with continued reference to fig. 6 on the basis of the foregoing embodiment, the initialization module 2 of the pixel circuit 1 of the display panel provided in the embodiment of the present invention may further include: a second initialization module 22; the first pole of the second initialization module 22 is connected with the anode of the light emitting module D1, and the second pole of the second initialization module 22 is connected with an initialization line Vref; the second initialization module 22 includes a fifth gate and a sixth gate; the fifth gate is used for inputting a second light-emitting control signal, and the sixth gate is used for inputting a first light-emitting control signal.

Specifically, the second initialization module 22 may include a second transistor M4, the data writing module 3 includes a third transistor M2, the light emitting control module 4 includes a fourth transistor M5 and a fifth transistor M6, and the memory module 4 includes a first memory module C1 and a second memory module C2.

It should be noted that the driving transistor M1, the switching transistor, and the memory module 4 may form various types of pixel circuits 1 in various connection relationships. The pixel circuit 1 shown in fig. 5 and 6 is only an example, and the pixel circuit 1 may be other forms of pixel circuits 1, such as a 6T2C pixel circuit 1, a 7T1C pixel circuit 1, and an 8T2C pixel circuit 1, where T represents a transistor, and C represents a capacitor. Fig. 5 and 6 exemplarily show the case of the 6T2C pixel circuit 1, and are not limited to the pixel circuit 1.

Optionally, with continued reference to fig. 4 and 7, the pixel circuit provided in this embodiment is configured such that, when displaying a picture in the first frequency range, the second gate and/or the fourth gate is configured to input the first bias control signal in an initial stage and to input the second bias control signal in a brightness maintaining stage.

Specifically, the first bias line Vini and/or the second bias line Vini2 are configured to provide a bias control signal to the pixel circuit 1, and when the pixel circuit 1 displays a picture in the first frequency range, the first bias line Vini and/or the second bias line Vini2 are configured to transmit the first bias control signal in the initial stage t1 and transmit the second bias control signal in the luminance maintaining stage t2, and at least a portion of the second bias control signal has a magnitude smaller than that of the first bias control signal. The arrangement is such that in the luminance maintaining phase t2, the first bias line Vini and/or the second bias line Vini2 transmits the second bias control signal with smaller amplitude to the pixel circuit 1, so that the variation of the driving current of the pixel circuit 1 is smaller, so that the driving current can be kept consistent when the display panel is in the first frequency range with lower display frequency, and the display effect of the display panel is improved.

Optionally, on the basis of the above embodiment, the first frequency range comprises frequencies less than 60 Hz.

Specifically, the first frequency range includes frequencies less than 60Hz, such as frequencies of 30Hz, frequencies of 1Hz, frequencies of 0.1Hz, and the like.

Illustratively, when the display panel displays a picture at a frequency of 1Hz, the data lines write data at a frequency of 60Hz in the initial stage t 1. In the luminance maintaining period t2, the driving frequency of 1Hz is maintained. At this time, since the driving frequency of 1Hz is low compared with the frequency of 60Hz, the time of the luminance maintaining period t2 becomes long. As the luminance maintaining period t2 is prolonged, the magnitude of the threshold voltage of the driving transistor M1 is gradually increased. The second bias control signal with larger amplitude is input to the second grid electrode and/or the fourth grid electrode through the arrangement in the brightness maintaining stage t2, so that fluctuation of threshold voltage of the driving transistor is reduced, fluctuation of driving current is reduced, the driving current is enabled to be consistent as much as possible in the brightness maintaining stage t2, the flicker problem existing when the display panel displays pictures in a first frequency range with lower driving frequency is reduced, and the display effect of the display panel is improved.

Optionally, based on the foregoing embodiment, with continued reference to fig. 4 and fig. 7, a voltage of the first bias control signal of the display panel provided by the embodiment of the present invention is constant; at least one of the voltage of the second bias control signal is constant, the voltage gradually decreases, or the voltage is pulsed. The second bias control signal transmitted by the second gate and the second bias control signal transmitted by the fourth gate may be set to be the same or different.

Specifically, since the frequency of the initial stage t1 is 60Hz, the time in the initial stage t1 is shorter, the driving current of the pixel circuit 1 is not easy to change, the voltage of the first bias control signal is kept constant, the first bias control signal is easier to realize, the realization difficulty of the driving chip 300 for generating the first bias control signal is reduced, and the manufacturing cost of the display panel is reduced.

With continued reference to fig. 4 and 7, by setting the voltage of the second bias control signal constant, the voltage gradually decreasing, or the voltage changing in pulses, etc., the pixel circuit 1 inputs the second bias control signal with smaller amplitude to the second gate and/or the fourth gate during at least part of the brightness maintaining period t2, so as to compensate the change of the driving current during the brightness maintaining period t2 as much as possible, and the driving current of the pixel circuit 1 fluctuates less. By the arrangement, the light emitting module D1 can display pictures more uniformly in the brightness maintaining stage t2, and the display effect of the display panel is further improved. Optionally, with continued reference to fig. 4 and fig. 7, based on the foregoing embodiments, the voltage of the second gate and/or the fourth gate of the display panel provided by the embodiments of the present invention configured to be the input second bias control signal linearly decreases; or the second gate and/or the fourth gate are configured such that the duty ratio of the inputted second bias control signal is equal or gradually reduced.

Specifically, the duty ratio of the second bias control signal input by the second gate and/or the fourth gate in the luminance maintaining period t2 is set to be equal or gradually reduced, so that the amplitude of the second bias control signal is reduced to a certain extent in the luminance maintaining period t2, thereby compensating for the increase of the threshold voltage of the driving transistor of the pixel circuit 1. On the other hand, the duty ratio of the second bias control signal may be set to be equal or gradually reduced as required, so that the second bias control signal compensates for the fluctuation of the driving current of the display panel as much as possible, thereby improving the display effect of the display panel.

Due to the gradual increase of the magnitude of the threshold voltage of the driving transistor M1 of the pixel circuit 1 in the luminance maintaining period t2, the threshold voltage of the driving transistor M1 is approximately linearly changed, and the second bias control signal input by the second gate and/or the fourth gate is linearly reduced, so that the compensation of the fluctuation of the driving current of the pixel circuit 1 is more uniform, and the display effect of the display panel is further improved.

Optionally, based on the foregoing embodiment, with continued reference to mode one in fig. 4, the luminance maintaining stage t2 of the display panel provided by the embodiment of the present invention includes N sub-light-emitting periods L1 to Ln; the second gate and/or the fourth gate is configured such that the voltage of the second bias control signal input per sub-emission period gradually decreases, and the voltage amplitude of the second bias control signal input in the (i+1) th sub-emission period is smaller than the voltage amplitude of the second bias control signal transmitted in the (i) th sub-emission period; wherein N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

Specifically, each sub-light emitting stage may be one frame, and the luminance maintaining stage t2 is divided into N sub-light emitting periods. The voltage of the second bias control signal input by the second gate and/or the fourth gate in each sub-emission period may be gradually reduced, so that the increase of the magnitude of the threshold voltage of the driving transistor M1 of the pixel circuit 1 can be compensated in each sub-emission period, so that the threshold voltage of the driving transistor M1 remains unchanged in each sub-emission period, the driving current in each sub-emission period is uniform, and the display effect of the display panel is improved.

Since the driving transistor M1 of the pixel circuit 1 is in the luminance maintaining stage t2, the threshold voltage of the driving transistor M1 is negatively biased with the continuation of the sub-emission stage, the magnitude of the threshold voltage of the driving transistor M1 is gradually increased, and the longer the luminance maintaining time, the larger the magnitude of the threshold voltage of the driving transistor M1. By setting the voltage amplitude of the second bias control signal input by the second gate and/or the fourth gate in the i+1th sub-emission period to be smaller than the voltage amplitude of the second bias control signal input by the i+1th sub-emission period, the second bias control signal with smaller voltage amplitude is transmitted in the i+1th sub-emission period with larger amplitude of the threshold voltage of the driving transistor M1, the threshold voltage stability of the driving transistor M1 in the brightness maintaining period t2 is further improved, and the display effect of the display panel is further improved.

Optionally, based on the foregoing embodiment, with continued reference to mode two in fig. 4, the luminance maintaining stage t2 of the display panel provided by the embodiment of the present invention includes N sub-light-emitting periods; the second gate and/or the fourth gate is configured such that a voltage amplitude of the second bias control signal input in the j+1th sub-emission period is greater than a voltage amplitude of the second bias control signal input in the j-th sub-emission period and is equal to a voltage amplitude of the second bias control signal transmitted in the j-1 th sub-emission period; wherein N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

Specifically, the voltage amplitude of the second bias control signal transmitted in the j+1th sub-emission period is greater than the voltage amplitude of the second bias control signal transmitted in the j-1 th sub-emission period and is equal to the voltage amplitude of the second bias control signal transmitted in the j-1 th sub-emission period, so that the threshold voltage of the driving transistor M1 is stabilized in the brightness maintaining period t2, the display effect of the display panel is further improved, and the driving chip 300 is facilitated to generate the second bias control signal.

The embodiment of the invention provides a display panel. With continued reference to fig. 1, the display panel 100 provided in the embodiment of the present invention includes the pixel circuit 1 provided in any of the above embodiments, and has the beneficial effects of the pixel circuit 1 provided in any of the above embodiments, which are not described herein again. The display panel 100 provided by the embodiment of the invention can be applied to terminals such as mobile phones, tablet computers and wearable equipment.

Optionally, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 9 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 8, the display panel provided in this embodiment may further include: at least one first bias line Vini extending in the first direction Y, the first bias line Vini being for connecting the second gate of the pixel circuit 1; at least one switching module 7, the switching module 7 being connected between the first bias line Vini and the second gate of the pixel circuit 1; the second gates of the pixel circuits 1 located in the same column are connected to the same first bias line Vini along the first direction Y; along the second direction X, the control signals input by the control ends of the switch modules 7 located in two adjacent rows are different; wherein the second direction X intersects the first direction Y.

Specifically, one first bias line Vini is arranged for each column for transmitting the first bias control signal and the second bias control signal to the second gate of the pixel circuit 1. Referring to fig. 8, it is exemplarily shown that each column of pixels corresponds to the first bias line Vini-1, the first bias line Vini-2, and the first bias line Vini-3, respectively, along the first direction Y. In the second direction X, corresponding switch modules 7 are arranged per row, the switch modules 7 may comprise switch transistors. The scan signals received by the control terminals of the switch modules 7 in the same row are the same, and the scan signals received by the control terminals of the switch modules 7 in adjacent rows are different. The switch module scans line by line according to the scanning signal received by the control module. When the scanning signal arrives, the switching block 7 of the row is turned on, controlling the first bias line Vini to transmit a bias control signal to the second gate of the pixel circuit 1. Referring to fig. 9, the second gate and the first power supply VDD form a capacitor C2, and the capacitor C2 is responsible for storing the bias control signal of the second gate of the driving transistor M1 of each pixel circuit 1 within 1 s.

In the initial stage t1, i.e. the writing frame, the first bias control signal transmitted by the first bias line Vini is the first power supply signal VDD, and in the brightness maintaining stage t2, i.e. the brightness maintaining frame, the second bias control signal transmitted by the first bias line Vini is the voltage signal shown in fig. 4, so that the potential of the second gate is maintained, and thus the current of the driving transistor M1 is maintained unchanged, and the cycle is thus repeated. The characteristic difference of the writing frame and the holding frame driving transistor M1 is well compensated, transient characteristic change of the driving transistor M1 is improved, and low-frequency or cut-frequency flicker is further improved.

Optionally, the display panel 100 may further include a second bias line Vini2, and the second bias line Vini2 may be disposed to extend along the first direction Y, the second bias line Vini2 being used to connect the fourth gate electrode of the pixel circuit 1; at least one switching module 7, the switching module 7 being connected between the second bias line Vini2 and the fourth gate of the pixel circuit 1; the fourth grid electrodes of the pixel circuits 1 positioned in the same column are connected with the same second bias line Vini2 along the first direction Y; along the second direction X, the control signals input by the control terminals of the switch modules 7 located in two adjacent rows are different. This arrangement can make the second bias control signal compensate for fluctuations in the drive current of the display panel as much as possible, further improving the display effect of the display panel.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A pixel circuit, comprising:

the light-emitting module is connected between the first power supply and the second power supply;

a driving transistor connected between the first power source and the light emitting module, the driving transistor including a first gate and a second gate;

an initialization module connected between an initialization line and the first gate; the second grid is used for inputting a first bias control signal in an initial stage and inputting a second bias control signal in a brightness maintaining stage; wherein at least a portion of the second bias control signal has a magnitude less than a magnitude of the first bias control signal.

2. The pixel circuit according to claim 1, wherein,

the initialization module comprises a first initialization module, a first pole of the first initialization module is connected with the first grid electrode of the driving transistor, and a second pole of the first initialization module is connected with the second pole of the driving transistor;

the first initialization module comprises a third grid electrode and a fourth grid electrode; the third grid is used for inputting a first light-emitting control signal;

the fourth grid is used for inputting a first light-emitting control signal; or the fourth gate is used for inputting the first bias control signal in an initial stage and inputting the second bias control signal in a brightness maintaining stage.

3. The pixel circuit according to claim 2, wherein,

when a picture is displayed in a first frequency range, the second grid electrode and/or the fourth grid electrode is/are configured to input a first bias control signal in an initial stage and to input a second bias control signal in a brightness maintaining stage;

preferably, the first frequency range comprises frequencies less than 60 Hz.

4. A pixel circuit according to claim 3, wherein,

the voltage of the first bias control signal is constant;

the second bias control signal has at least one of a constant voltage, a gradual voltage decrease, or a pulsed voltage.

5. The pixel circuit according to claim 2, wherein,

the voltage of the second bias control signal input to the second gate and/or the fourth gate is linearly decreased; or alternatively, the process may be performed,

the second gate and/or the fourth gate are configured to have the duty ratio of the second bias control signal input equal or gradually decreasing.

6. The pixel circuit of claim 2, wherein the brightness maintaining stage comprises N sub-emission periods;

the second gate and/or the fourth gate is configured such that a voltage of a second bias control signal input in each of the sub-emission periods gradually decreases, and a voltage amplitude of the second bias control signal input in an i+1th sub-emission period is smaller than a voltage amplitude of the second bias control signal transmitted in the i-th sub-emission period;

wherein N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

7. The pixel circuit of claim 2, wherein the brightness maintaining stage comprises N sub-emission periods;

the second gate and/or the fourth gate is configured such that a voltage amplitude of the second bias control signal input in the j+1th sub-emission period is greater than a voltage amplitude of the second bias control signal input in the j-th sub-emission period and is equal to a voltage amplitude of the second bias control signal transmitted in the j-1 th sub-emission period;

wherein N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

8. The pixel circuit of claim 2, wherein the initialization module further comprises:

a second initialization module;

the first pole of the second initialization module is connected with the anode of the light-emitting module, and the second pole of the second initialization module is connected with an initialization line;

the second initialization module comprises a fifth grid electrode and a sixth grid electrode;

the fifth gate is used for inputting a second light-emitting control signal, and the sixth gate is used for inputting a first light-emitting control signal.

9. A display panel, comprising: a pixel circuit as claimed in any one of claims 1 to 8.

10. The display panel of claim 9, further comprising:

at least one first bias line extending in a first direction, the first bias line being for connecting a second gate of the pixel circuit;

at least one switching module connected between the first bias line and the second gate of the pixel circuit;

the second grid electrodes of the pixel circuits positioned in the same column are connected with the same first bias line along the first direction;

along a second direction, control signals input by control ends of the switch modules positioned in two adjacent rows are different; wherein the second direction intersects the first direction.

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