CN116205883A

CN116205883A - PCB surface defect detection method, system, electronic equipment and medium

Info

Publication number: CN116205883A
Application number: CN202310198320.1A
Authority: CN
Inventors: 秦浩
Original assignee: Lingtu Data Hangzhou Co ltd
Current assignee: Lingtu Data Hangzhou Co ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-06-02

Abstract

The invention belongs to the technical field of deep learning target detection, and aims to provide a PCB surface defect detection method, a system, electronic equipment and a medium. The method comprises the following steps: acquiring a PCB image to be detected and a PCB template image matched with the PCB image to be detected; inputting the PCB image to be detected and the PCB template image into a PCB surface defect detection model in pairs to obtain a surface defect prediction result of the PCB corresponding to the PCB image to be detected, wherein the surface defect prediction result comprises position information, defect category and confidence score of the surface defect of the PCB; the PCB surface defect detection model is obtained based on a YOLOx model and comprises a main network layer, a feature fusion layer, a detection head and a prediction layer which are sequentially connected, wherein the main network layer adopts a ConvNeXt network. The PCB surface defect detection model is obtained by selecting the YOLOx model in the single-stage detection network class, the network structure can be optimized on the basis of ensuring the detection speed, and the detection precision is further improved.

Description

PCB surface defect detection method, system, electronic equipment and medium

Technical Field

The invention belongs to the technical field of deep learning target detection, and particularly relates to a PCB surface defect detection method, a system, electronic equipment and a medium.

Background

In recent years, with the development of industries such as communications, computers, electronics, etc., the printed circuit board (Printedcircuit boards, PCB) industry has also rapidly developed. But the quality of the PCB is currently not optimistic. The quality of the PCB depends on the quality of each line and each hole on the printed PCB, and any of thousands of lines and holes on a board has quality problems such as too thin, too thick, incomplete, pinholes, adhesion, disconnection, dislocation, etc., which affect the quality of the final product, or cause waste. The more layers of the PCB, the more pronounced the problem, and the higher the rejection rate that results.

Thus, in the PCB production process, how to improve the product quality of the intermediate process, how to reduce the rejection rate, and how to improve the PCB quality are constantly pursued targets of various PCB manufacturers. Because the PCB is affected by a plurality of uncertain factors in the production process, the defects of the PCB are difficult to avoid, and the faults are mostly line errors and mainly can be divided into: short circuit, open circuit, burr, notch, pinhole, residual copper. If these quality problems are not checked out in time, hidden danger is left in the debugging and using process of the PCB, and larger loss is caused, so that strict intermediate inspection is necessary to be implemented.

Early PCB detection adopts a mode of checking by naked eyes, however, the detection precision and efficiency of the method depend on the working experience of detection personnel to a great extent, and meanwhile, the detection precision is also reduced with the duration of time, and the detection scheme is high in instability as a whole. Because of the defects existing in manual detection, at present, online detection of the PCB becomes a consensus of manufacturers and enterprises.

At present, a detection scheme based on computer vision is presented, the detection of the surface defects of the PCB is carried out in an image recognition mode, direct contact with the PCB is not needed, the possibility of secondary damage of the PCB is avoided, meanwhile, the detection efficiency of images is greatly improved along with the development of computer hardware, in the field of image detection, a target detection algorithm based on deep learning and a traditional detection algorithm are improved in detection precision and detection degree, and more recognition detection scenes adopt the scheme to carry out floor conversion.

Specifically, the current PCB defect detection algorithm based on deep learning is mainly divided into a two-stage target detection algorithm and a one-stage target detection algorithm, wherein the detection speed based on the one-stage target detection algorithm is higher. Based on this, in the prior art, chinese patent publication No. CN114372949a discloses a PCB surface defect detection method based on an improved YOLOv5 algorithm, which can optimize a network structure on the basis of ensuring a detection speed. However, in using the prior art, the inventors found that there are at least the following problems in the prior art:

the prior art adopts an anchor frame mechanism based on YOLOv5, namely, a regression frame-based detection and identification algorithm in a one-stage target detection algorithm is utilized, but the anchor frame mechanism introduces a plurality of super parameters and depends on manual design, so that the anchor frame mechanism cannot be well popularized to other data sets, and the generalization of a model is not strong; meanwhile, in the PCB defect detection process based on the anchor frame method, the detection requirement cannot be met due to an unknown mode or over sensitivity to certain super parameters, and the method is not suitable for small target detection of PCB defects in industrial scenes.

In addition, if the anchor-free method in the one-stage target detection algorithm is adopted, the problem that the precision is limited is caused by the missing detection or false detection phenomenon exists, particularly, if only the characteristics of a test image are considered during the detection of the PCB defect based on the anchor-free method, the feature matching of the test image and the PCB template image is not considered, the missing detection or false detection of a test result can sometimes occur, the precision is limited, and the training is not easy to converge.

Disclosure of Invention

The invention aims to solve the technical problems at least to a certain extent, and provides a PCB surface defect detection method, a system, electronic equipment and a medium.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

in a first aspect, a method for detecting a surface defect of a PCB is provided, including:

acquiring a PCB image to be detected and a PCB template image matched with the PCB image to be detected;

inputting the PCB image to be detected and the PCB template image into a PCB surface defect detection model in pairs to obtain a surface defect prediction result of the PCB corresponding to the PCB image to be detected, wherein the surface defect prediction result comprises position information, defect type and confidence score of the surface defect of the PCB; the PCB surface defect detection model is obtained based on a YOLOx model and comprises a main network layer, a feature fusion layer, a detection head and a prediction layer which are sequentially connected, wherein the main network layer adopts a ConvNeXt network;

the main network layer is used for extracting the characteristics of the PCB image to be detected and the PCB template image to obtain the characteristic vector of the PCB image to be detected;

the feature fusion layer is used for carrying out feature fusion on the feature vectors of the PCB image to be detected to obtain fused feature information;

and the detection head is used for carrying out defect position information conversion, defect category conversion and confidence score conversion on the fused characteristic information so that the prediction layer can obtain the position information, defect category and confidence score of the PCB surface defect corresponding to the PCB image to be detected according to the converted data.

The PCB surface defect detection model is obtained by selecting the YOLOx model in the single-stage detection network class, the network structure can be optimized on the basis of ensuring the detection speed, and the detection precision is further improved. Specifically, the YOLOx model introduces an advanced anchor-free method and is provided with a dynamic label distribution function to improve the performance of the detector, and is obviously superior to the YOLOv5 model in terms of precision. Specifically, the invention establishes a PCB surface defect detection model based on a YOLOx model, and replaces a CSPDarknet network of a main feature extraction network original by the YOLOx model with a ConvNeXt network so as to extract features; through example detection, the invention not only avoids the problem of poor model generalization caused by the sensitivity of an anchor frame mechanism to super parameters by using the thought of an improved YOLOx network, but also can realize higher-precision PCB defect detection, greatly reduces the missing detection phenomenon of defect detection, and improves the detection speed.

In one possible design, the PCB surface defect detection model further includes an image input layer disposed at the input of the backbone network layer; the image input layer is used for inputting the PCB image to be detected and the PCB template image into the backbone network layer in pairs.

In one possible design, the backbone network layer includes a shallow feature extraction layer, a middle feature extraction layer, and a deep feature extraction layer;

the shallow feature extraction layer is used for respectively carrying out shallow feature extraction on the PCB image to be detected and the PCB template image to obtain the PCB image feature to be detected and the PCB template image feature, then obtaining the feature difference between the PCB image feature to be detected and the PCB template image feature, carrying out feature extraction on the feature difference again to obtain a shallow feature image, and finally outputting the shallow feature image to the middle layer feature extraction layer;

the middle-layer feature extraction layer is used for extracting middle-layer features of the shallow-layer feature map to obtain a middle-layer feature map;

the deep feature extraction layer is used for carrying out deep feature extraction on the middle layer feature map to obtain a deep feature map.

In one possible design, taking the GIoU as a performance evaluation index of the PCB surface defect detection model, and taking the GIoU_LOSS as a positioning LOSS function of the PCB surface defect detection model; wherein, the performance evaluation index is:

；

wherein A is a prediction frame, B is a target frame, C is the minimum convex set of the prediction frame and the target frame, and IoU is the intersection ratio of the prediction frame and the target frame;

the positioning loss function is:

GIoU_LOSS=1-GIoU。

in one possible design, the feature fusion layer includes a spatial pyramid pooling layer, an FPN layer, and a PAN layer connected in sequence with the backbone network layer;

the input end of the space pyramid pooling layer is connected with the output end of the deep feature extraction layer and is used for carrying out multiple receptive field fusion on the deep feature map to obtain feature vectors of the PCB image to be detected;

the FPN layer comprises a first convolution structure layer, a second convolution structure layer and a third convolution structure layer which are sequentially connected; the input end of the first convolution structure layer is connected with the output end of the spatial pyramid pooling layer, the input end of the second convolution structure layer is respectively connected with the output end of the middle layer feature extraction layer and the output end of the first convolution structure layer, and the input end of the third convolution structure layer is respectively connected with the output end of the shallow layer feature extraction layer and the output end of the second convolution structure layer; the first convolution structure layer and the second convolution structure layer are connected through an upsampling layer, and the upsampling layer is used for upsampling operation;

the PAN layer comprises a fourth convolution structure layer and a fifth convolution structure layer which are sequentially connected, wherein the input end of the fourth convolution structure layer is respectively connected with the output end of the third convolution structure layer and the output end of the second convolution structure layer, and the input end of the fifth convolution structure layer is respectively connected with the output end of the first convolution structure layer and the output end of the fourth convolution structure layer.

In one possible design, the detection head includes a first detection head, a second detection head, and a third detection head, where an input end of the first detection head is connected to an output end of the third convolution layer, an input end of the second detection head is connected to an output end of the fourth convolution layer, and an input end of the third detection head is connected to an output end of the fifth convolution layer.

In one possible design, the PCB surface defect detection model is trained using the concept of migration learning.

In a second aspect, a system for detecting surface defects of a PCB is provided, for implementing a method for detecting surface defects of a PCB as described in any one of the above; the PCB surface defect detection system comprises an acquisition unit and a prediction unit; wherein, the liquid crystal display device comprises a liquid crystal display device,

the acquisition unit is used for acquiring a PCB image to be detected and a PCB template image matched with the PCB image to be detected;

the predicting unit is used for inputting the PCB image to be detected and the PCB template image into a PCB surface defect detecting model in pairs to obtain a surface defect predicting result of the PCB corresponding to the PCB image to be detected, wherein the surface defect predicting result comprises position information, defect category and confidence score of the PCB surface defect; the PCB surface defect detection model is obtained based on a YOLOx model and comprises a main network layer, a feature fusion layer, a detection head and a prediction layer which are sequentially connected, wherein the main network layer adopts a ConvNeXt network.

In a third aspect, an electronic device is provided, comprising:

a memory for storing computer program instructions; the method comprises the steps of,

a processor for executing the computer program instructions to perform the operations of the method for detecting surface defects of a PCB as described in any one of the preceding claims.

In a fourth aspect, a computer readable storage medium is provided for storing computer readable computer program instructions configured to perform the operations of the PCB surface defect detection method as claimed in any one of the preceding claims when run.

Drawings

FIG. 1 is a flowchart of a method for detecting surface defects of a PCB in embodiment 1;

fig. 2 is a schematic structural diagram of a surface defect detection model of a PCB in embodiment 1;

fig. 3 is a block diagram of a PCB surface defect detection system in example 2.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present invention, but is not intended to limit the present invention.

Example 1:

the present embodiment discloses a method for detecting surface defects of a PCB, which may be performed by, but not limited to, a computer device or a virtual machine having a certain computing resource, for example, an electronic device such as a personal computer, a smart phone, a personal digital assistant or a wearable device, or a virtual machine.

As shown in fig. 1, a method for detecting surface defects of a PCB may include, but is not limited to, the following steps:

s1, acquiring a PCB image to be detected and a PCB template image matched with the PCB image to be detected;

s2, inputting the PCB image to be detected and the PCB template image into a PCB surface defect detection model in pairs to obtain a surface defect prediction result of the PCB corresponding to the PCB image to be detected, wherein the surface defect prediction result comprises position information, defect category and confidence score of the PCB surface defect; the PCB surface defect detection model is obtained based on a YOLOx model, and comprises a main network layer, a feature fusion layer, a detection head and a prediction layer which are sequentially connected, wherein the main network layer adopts a ConvNeXt network for feature extraction, and particularly the ConvNeXt network is an image classification network, so that higher precision and higher feature extraction speed can be achieved;

In this embodiment, the PCB surface defect detection model further includes an image input layer disposed at an input end of the backbone network layer; the image input layer is used for inputting the PCB image to be detected and the PCB template image into the backbone network layer in pairs.

Aiming at the phenomena of missing detection and false detection existing in the existing YOLOx model, the embodiment further makes the following improvements: as shown in fig. 2, the backbone network layer includes a shallow feature extraction layer 1, a middle feature extraction layer 2, and a deep feature extraction layer 3;

the shallow feature extraction layer 1 is configured to perform shallow feature extraction on the to-be-detected PCB image and the PCB template image respectively to obtain to-be-detected PCB image features and PCB template image features, obtain feature differences between the to-be-detected PCB image features and the PCB template image features, perform feature extraction on the feature differences again to obtain a shallow feature map, and finally output the shallow feature map to the middle feature extraction layer 2;

the middle-layer feature extraction layer 2 is used for extracting middle-layer features of the shallow-layer feature map to obtain a middle-layer feature map;

the deep feature extraction layer 3 is used for carrying out deep feature extraction on the middle layer feature map to obtain a deep feature map.

In this embodiment, the shallow layer features are extracted from the to-be-detected PCB image and the PCB template image by using the shared network parameters, and then the feature difference is made, so that the obtained feature difference map can still be effective when there is translation, rotation or scaling between the to-be-detected PCB image and the PCB template image, and can help to eliminate the influence of translation and rotation between the to-be-detected PCB image and the PCB template image, and highlight the defects in the to-be-detected PCB image, thereby being beneficial to the PCB surface defect detection model to learn the defect features better, further effectively reducing false detection and omission rate of PCB defects, and improving the detection accuracy.

It should be further noted that the conventional ConvNeXt network includes 4 downsamples and 4 ConvNeXt Block layers, where the multiple of the downsamples is 4 times, 8 times, 16 times and 32 times, the number of channels of the corresponding ConvNeXt Block layers is 96, 192, 384 and 768, and the Convnext network in this embodiment repeatedly stacks 3 layers, 9 layers and 3 layers, and uses the previous 3 downsamples and the corresponding 3 ConvNeXt Block layers to perform feature extraction, and each downsampled and corresponding ConvNeXtBlock is the shallow layer feature extraction layer 1, the middle layer feature extraction layer 2 and the deep layer feature extraction layer 3.

In this embodiment, the feature fusion layer includes a spatial pyramid pooling layer 4, an FPN (Feature PyramidNetworks, feature pyramid network) layer, and a PAN (pixel aggregation network) layer sequentially connected to the backbone network layer;

and the input end of the space pyramid pooling layer 4 is connected with the output end of the deep feature extraction layer and is used for carrying out multiple receptive field fusion on the deep feature image so as to increase receptive fields and obtain feature vectors of the PCB image to be detected. It should be noted that the shallow layer feature map, the middle layer feature map and the deep layer feature map respectively have a small receptive field, a middle receptive field and a large receptive field, so that surface defects with different sizes of PCBs can be detected, and the method is applicable to the situation that the size difference of targets in the PCB image to be detected is large; when the space pyramid pooling layer 4 carries out multiple receptive field fusion on the deep feature images, pooling fusion is carried out according to fixed sizes 5, 9 and 13, so that the ConvNeXt network has certain detection capability on larger defects.

The FPN layer comprises a first convolution structure layer 5, a second convolution structure layer 6 and a third convolution structure layer 7 which are sequentially connected; the input end of the first convolution structure layer 5 is connected with the output end of the spatial pyramid pooling layer 4, the input end of the second convolution structure layer 6 is respectively connected with the output end of the middle layer feature extraction layer 2 and the output end of the first convolution structure layer 5, and the input end of the third convolution structure layer 7 is respectively connected with the output end of the shallow layer feature extraction layer 1 and the output end of the second convolution structure layer 6; the first convolution layer 5 and the second convolution layer 6, and the second convolution layer 6 and the third convolution layer 7 are connected by an upsampling layer.

The PAN layer comprises a fourth convolution structure layer 8 and a fifth convolution structure layer 9 which are sequentially connected, wherein the input end of the fourth convolution structure layer 8 is respectively connected with the output end of the third convolution structure layer 7 and the output end of the second convolution structure layer 6, and the input end of the fifth convolution structure layer is respectively connected with the output end of the first convolution structure layer 5 and the output end of the fourth convolution structure layer 8.

Specifically, the FPN layer is a feature pyramid from top to bottom, which is used to transfer deep strong semantic features, and enhance the whole pyramid, but only enhance semantic information, but not transfer positioning information. The PAN layer is aimed at the point, a bottom-up pyramid is added behind the FPN layer, the FPN layer is supplemented, and the shallow positioning features are transferred, so that the formed pyramid combines semantic information and has positioning information. In this embodiment, the feature fusion layer uses the lock structure of YOLOx, and performs feature fusion on the 3 feature maps (i.e., the shallow feature map, the middle feature map, and the deep feature map in this embodiment) of 160×160×96, 80×80×192, and 40×40×384, which are transmitted from the backbone network layer, respectively, so that the feature fusion layer has semantic information and positioning information, and then transmits the semantic information and the positioning information to the detection head.

In this embodiment, the detecting head includes a first detecting head 10, a second detecting head 11, and a third detecting head 12, where an input end of the first detecting head 10 is connected to an output end of the third convolution layer 7, an input end of the second detecting head 11 is connected to an output end of the fourth convolution layer 8, and an input end of the third detecting head 12 is connected to an output end of the fifth convolution layer 9.

Specifically, in the present embodiment, the input dimensions of the first detection head 10, the second detection head 11, and the third detection head 12 are respectively: 160×160×96, 80×80×192, and 40×40×384, in this embodiment, the detection heads are used to convert feature information into information of defect type, coordinates, and the like, and then 6+4+1-dimensional data is output by convolution so that the prediction layer performs PCB defect type, positioning, and confidence prediction, respectively, specifically, for each of the 3 detection heads (the first detection head 10, the second detection head 11, and the third detection head 12), there are 3 output results of 6, 4, and 1 channels, wherein the result of 6 channels is used for defect type information conversion, the result of 4 channels is used for defect positioning information conversion, and the result of 1 channels is used for defect confidence score conversion. In this embodiment, after the class, location and confidence of the surface defect of the PCB are obtained, loss (the Loss function mainly comprises three parts, namely, classification Loss, location Loss and confidence Loss) is calculated by comparing with real data, and then the gradient descent algorithm is used to perform back propagation to update network parameters.

In the PCB defect detection, small target detection is generally adopted in an industrial scene, so that further improvement on the small target defect detection is needed, and a detection head suitable for detecting the small target defect of the PCB is added on the basis of the improved PCB surface defect detection model. And (3) carrying out feature extraction on the backbone network layer, and selecting 3 feature layers with different sizes so as to adapt to target detection of 3 different scales. Specifically, the 3 feature layers are located at different positions of the backbone network layer, namely, the middle layer, the middle lower layer and the bottom layer, and when the input is (640, 640,3), the shapes of the 3 feature layers are respectively, at_1= (80,80,256), at_2= (40,40,512), at_3= (20,20,1024); in this embodiment, after 3 effective feature layers are obtained, the 3 effective feature layers may be used to construct a feature fusion layer of the FPN layer+the PAN layer.

The core of the PCB surface defect detection model in the embodiment is to perform feature fusion on a deep feature map with strong semantic features and a shallow feature map with strong edge and position information so as to improve detection accuracy.

The small target corresponds to the characteristic diagram with smaller receptive field, and for industrial PCB defect detection, the primary task is to improve the detection performance of the small target, so that a small target detection head is added, namely, the small target detection head performs up-sampling on the basis of the original 8-time down-sampling characteristic diagram and performs characteristic fusion with the 4-time down-sampling characteristic diagram, so that the position of the PCB defect and the small target are predicted better. Considering that the feature map sampled 32 times already contains too strong semantic information, and the feature difference map of the test image and the PCB template image is obtained before the feature map is already focused on the defect part, the strong semantic information of the feature difference map is not needed to be focused on again, and the defect detection problem of the PCB is not too great, so that the last feature extraction layer of the existing convnex network is deleted in the embodiment, the obtained backbone network layer only comprises a shallow feature extraction layer 1, a middle feature extraction layer 2 and a deep feature extraction layer 3, and an SPP module (namely a spatial pyramid pooling layer 6) in the tail of the CSPDarkNet is reserved after the deep feature extraction layer 3, so that a large feeling field can be still maintained after the highest feature layer is deleted, and the novel 3 detection heads are formed.

In this embodiment, GIoU is used as a performance evaluation index of the PCB surface defect detection model, and giou_loss is used as a positioning LOSS function of the PCB surface defect detection model; wherein, the performance evaluation index is:

；

the positioning loss function is:

GIoU_LOSS=1-GIoU。

the original YOLOx model uses binary cross entropy to determine classification and confidence loss functions, uses IoU to determine positioning loss functions, but YOLOx uses IoU to determine that the network positioning loss functions and performance evaluation indexes have gradient problems, so that improved YOLOx network positioning loss functions and performance evaluation indexes are determined according to GIoU.

Specifically, the performance evaluation index is the basis of the performance of a model on a data set, the loss function mainly guides the model to fit data distribution, and most of the loss function can be directly used as the evaluation index; the initial YOLOx uses IoU as a performance evaluation index of the network, ioU _loss is used as a positioning loss function of the network, and the initial YOLOx is used for regression of four points of a target detection frame as a whole; however, when the prediction frame and the target frame do not intersect, i.e., ioU (a, B) =0, A, B refers to the prediction frame and the target frame, respectively, and cannot reflect the distance between the prediction frame and the target frame, where the loss function is not predictable, and IoULoss cannot optimize the case where the two frames do not intersect. In order to avoid the problem, in this embodiment, the GIoU is used as a performance evaluation index of the PCB surface defect detection model, the giou_loss is used as a positioning LOSS function of the PCB surface defect detection model, and when the bounding box regression is performed in the model training process, the giou_loss is used for constraint, and when the LOSS function value gradually decreases to be stable, the model converges. The problem that gradient cannot be calculated when IoU is taken as a loss function is solved, and the minimum outer cover is added as a penalty term.

In this embodiment, the PCB surface defect detection model is trained by using the idea of migration learning.

In the embodiment, when the PCB surface defect detection model is trained, an initial PCB data set is acquired firstly, and then data enhancement processing is carried out on the initial PCB data set to obtain an enhanced PCB data set; the original image data samples in the initial PCB data set are of six defect types, namely, open circuit, short circuit, burr, notch, residual copper and pinhole, and as an example, the original image data samples are of 1702 pairs, the data are changed into 3020 pairs after being expanded, in this embodiment, when the data enhancement is performed, the original image data samples are labeled by using LabelIMg, and then the original image data samples are enhanced by using random combinations of multiple operations such as brightness adjustment, cutting, rotation, translation and mirroring based on the labeled pictures, so that the detection effect of the subsequent network model on the PCB defects is facilitated to be improved.

It should be further noted that, in the configured environment, the number of times of training the epochs (the number of times of participation of the data set in training, one Epoch means that all the data input networks are completed once for forward calculation and backward propagation) is set to 300, the batch-size is set to 8, the initial learning rate is set to 0.01, and the learning rate is adjusted to half of the original per 50 epochs (unified input image scale) in accordance with the strategy of reducing the learning rate in segments. If the loss function value is found to gradually decrease from the beginning to the final stable state in the training process, the model can be judged to be converged. Specifically, in this embodiment, the environment configuration is shown in table 1 below, and the experimental parameter settings are shown in table 2 below:

operating system	Ubuntu 18.04
		Processor and method for controlling the same	Intel(R) Xeon(R) Gold 6271C CPU @ 2.60GHz
Memory	32GB
		GPU	V100
Video memory	32GB
		Procedure	Python 3.7
Deep learning frame	Pytorch 1.7

TABLE 1

Parameters (parameters)	Parameter setting
		LearningRate of	0.01
Weight decay	0.0005
		Maximum number of iterations	75600
Batch	8
		Epochs	300

TABLE 2

In this embodiment, compared with the existing YOLOx model, the experimental performance of the PCB surface defect detection model is shown in the following table 3:

model	Backbone network layer	mAP/%	Frame rate/(f.s-1)
				Existing YOLOx model	CSPDarkNet	92.63	12.62
PCB surface defect detection model	ConvNext	98.45	26.16

TABLE 3 Table 3

As can be seen from table 3, in this embodiment, the mAP (overall average correct rate) and the frame rate of the PCB surface defect detection model are both larger than those of the conventional YOLOx model.

The PCB surface defect detection model in the embodiment is obtained by selecting a YOLOx model in a single-stage detection network type, the network structure can be optimized on the basis of ensuring the detection speed, and meanwhile, the detection precision is further improved. Specifically, the YOLOx model introduces an advanced anchor-free method and is provided with a dynamic label distribution function to improve the performance of the detector, and is obviously superior to the YOLOv5 model in terms of precision. Specifically, in this embodiment, a PCB surface defect detection model based on a YOLOx model is established, and a trunk feature extraction network CSPDarknet network originally set by the YOLOx model is replaced by a ConvNeXt network so as to perform feature extraction; through example detection, the embodiment not only avoids the problem of poor model generalization caused by the sensitivity of an anchor frame mechanism to super parameters by using the improved idea of the YOLOx network, but also can realize higher-precision PCB defect detection, greatly reduces the missing detection phenomenon of defect detection, and improves the detection speed.

Example 2:

the embodiment discloses a PCB surface defect detection system, which is used for realizing the PCB surface defect detection method in the embodiment 1; as shown in fig. 3, the PCB surface defect detection system includes an acquisition unit and a prediction unit; wherein, the liquid crystal display device comprises a liquid crystal display device,

Example 3:

on the basis of

embodiment

1 or 2, this embodiment discloses an electronic device, which may be a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like. An electronic device may be referred to as being for a terminal, portable terminal, desktop terminal, etc., the electronic device including:

a processor for executing the computer program instructions to perform the operations of the method for detecting surface defects of a PCB as described in any one of embodiment 1.

Example 4:

on the basis of any one of embodiments 1 to 3, this embodiment discloses a computer-readable storage medium for storing computer-readable computer program instructions configured to perform the operations of the PCB surface defect detection method as described in embodiment 1 when run.

It will be apparent to those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, or they may alternatively be implemented in program code executable by computing devices, such that they may be stored in a memory device for execution by the computing devices, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present invention, and not limiting thereof; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents. Such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A PCB surface defect detection method is characterized in that: comprising the following steps:

2. The method for detecting surface defects of a PCB according to claim 1, wherein: the PCB surface defect detection model further comprises an image input layer arranged at the input end of the main network layer; the image input layer is used for inputting the PCB image to be detected and the PCB template image into the backbone network layer in pairs.

3. The method for detecting surface defects of a PCB according to claim 1, wherein: the trunk network layer comprises a shallow layer feature extraction layer, a middle layer feature extraction layer and a deep layer feature extraction layer;

4. A method for detecting surface defects of a PCB according to claim 1 or 3, wherein: taking GIoU as a performance evaluation index of the PCB surface defect detection model, and taking GIoU_LOSS as a positioning LOSS function of the PCB surface defect detection model; wherein, the performance evaluation index is:

；

the positioning loss function is:

GIoU_LOSS=1-GIoU。

5. a method for detecting surface defects of a PCB according to claim 3, wherein: the feature fusion layer comprises a spatial pyramid pooling layer, an FPN layer and a PAN layer which are sequentially connected with the backbone network layer;

6. The method for detecting surface defects of a PCB according to claim 5, wherein: the detection head comprises a first detection head, a second detection head and a third detection head, wherein the input end of the first detection head is connected with the output end of the third convolution structure layer, the input end of the second detection head is connected with the output end of the fourth convolution structure layer, and the input end of the third detection head is connected with the output end of the fifth convolution structure layer.

7. The method for detecting surface defects of a PCB according to claim 1, wherein: and training the PCB surface defect detection model by utilizing the idea of transfer learning.

8. A PCB surface defect detection system, characterized in that: for implementing the PCB surface defect detection method according to any one of claims 1 to 7; the PCB surface defect detection system comprises an acquisition unit and a prediction unit; wherein, the liquid crystal display device comprises a liquid crystal display device,

9. An electronic device, characterized in that: comprising the following steps:

a processor for executing the computer program instructions to perform the operations of the PCB surface defect detection method as claimed in any one of claims 1 to 7.

10. A computer readable storage medium storing computer program instructions readable by a computer, characterized by: the computer program instructions are configured to perform the operations of the PCB surface defect detection method of any one of claims 1 to 7 when run.