CN116205199B

CN116205199B - Chip verification method, device, electronic equipment, storage medium and program product

Info

Publication number: CN116205199B
Application number: CN202310487434.8A
Authority: CN
Inventors: 田瑞冬; 宋卓; 陈健康
Original assignee: Alibaba Cloud Computing Ltd
Current assignee: Alibaba Cloud Computing Ltd
Priority date: 2023-05-04
Filing date: 2023-05-04
Publication date: 2023-07-18
Anticipated expiration: 2043-05-04
Also published as: CN116205199A

Abstract

The embodiment of the application provides a chip verification method, a chip verification device, electronic equipment, a computer storage medium and a computer program product. The chip verification method comprises the following steps: receiving a verification instruction for a chip; loading an operating system and creating a host bridge device in response to the verification instruction; and if the creation of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, starting the operating system, and verifying the chip according to the operating system. In the embodiment of the application, after receiving the verification instruction for the chip, when responding to the verification instruction, the host bridge device is determined to be established and the operating system is loaded to be completed, so that the operating system can be started, the processes of establishing the PCI bridge device and traversing and initializing the bus device under the PCI bridge device are omitted, the starting time of the operating system can be effectively reduced, and the verification efficiency is improved.

Description

Chip verification method, device, electronic equipment, storage medium and program product

Technical Field

Embodiments of the present application relate to the field of chip manufacturing, and in particular, to a chip verification method, a device, an electronic apparatus, a computer storage medium, and a computer program product.

Background

In the process of chip development, chip verification is an indispensable process, and in particular, various functions and interfaces of a chip are tested before and after chip streaming. Chip verification prior to production is particularly important because the chip cannot be changed once it is formally produced.

The verification of the chip includes verification of many functional characteristics, which can be completed based on a complete operating system (including a hardware part and a software part).

Thus, in the chip verification stage, a simulation platform, such as an FPGA (Field Programmable Gate Array ) simulation platform suitable for use in front of silicon, is typically used to simulate a designed chip and to start an operating system based on the simulated chip to test various functions and interfaces of the chip. However, the starting process of the operating system consumes a lot of time, and the operating system needs to be restarted after each chip modification to continuously verify the modified chip, so that the starting process of the operating system takes a long time, the chip verification efficiency is seriously affected, and the development progress of the chip is seriously affected.

In view of the foregoing, a new chip verification method is needed to reduce the time consumed in the start-up process of the operating system.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a check code generation scheme to at least partially solve the above-mentioned problems.

According to a first aspect of an embodiment of the present application, there is provided a chip verification method, including: receiving a verification instruction for a chip; in response to the verification instruction, loading an operating system and creating a host bridge device; if the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, starting the operating system, and verifying the chip according to the operating system.

According to a second aspect of embodiments of the present application, there is provided a chip authentication apparatus, including: the receiving module is used for receiving a verification instruction aiming at the chip; the starting module is used for responding to the verification instruction, loading an operating system and creating host bridge equipment; and the verification module is used for starting the operating system when the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, and verifying the chip according to the operating system.

According to a third aspect of embodiments of the present application, there is provided an electronic device, including: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store at least one executable instruction, where the executable instruction causes the processor to execute the instruction, and cause the processor to perform operations corresponding to the method according to the first aspect.

According to a fourth aspect of embodiments of the present application, there is provided a computer storage medium having stored thereon a computer program which, when executed by a processor, implements the method according to the first aspect.

According to a fifth aspect of embodiments of the present application, there is provided a computer program product comprising computer instructions for instructing a computing device to execute the method as described in the first aspect.

In the embodiment of the application, after receiving the verification instruction for the chip, when responding to the verification instruction, the host bridge device is determined to be established and the operating system is loaded to be completed, so that the operating system can be started, the processes of establishing the PCI bridge device and traversing and initializing the bus device under the PCI bridge device are omitted, the starting time of the operating system can be effectively reduced, and the verification efficiency is improved. Meanwhile, for the scene that the bus equipment still needs to be used, the enumeration of the bus equipment can be carried out again after the operating system is started. Efficiency and practicality are considered, and the chip verification period is shortened.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings may also be obtained according to these drawings for a person having ordinary skill in the art.

Fig. 1 is a schematic diagram of an exemplary system to which the chip authentication method of the embodiment of the present application is applied.

Fig. 2 is a schematic diagram of a PCI topology according to a first embodiment of the present application.

Fig. 3 is a flowchart illustrating steps of a chip verification method according to a first embodiment of the present application.

Fig. 4 is a schematic diagram of another PCI topology according to the first embodiment of the present application.

FIG. 5 is a comparison of the prior art and the operation system boot flow according to the first embodiment of the present application.

Fig. 6 is a flowchart illustrating steps of a chip verification method according to a second embodiment of the present application.

Fig. 7 is a block diagram of a chip verification device according to a third embodiment of the present application.

Fig. 8 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application.

Detailed Description

In order to better understand the technical solutions in the embodiments of the present application, the following descriptions will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the embodiments of the present application shall fall within the scope of protection of the embodiments of the present application.

Fig. 1 shows an exemplary system to which the chip authentication method of the embodiment of the present application is applied. As shown in fig. 1, the system 100 may include a cloud service 102, a communication network 104, and/or one or more user devices 106, which are illustrated in fig. 1 as a plurality of user devices.

Cloud server 102 may be any suitable device for storing information, data, programs, and/or any other suitable type of content, including, but not limited to, distributed storage system devices, server clusters, computing cloud server clusters, and the like. In some embodiments, cloud server 102 may perform any suitable functions. For example, in some embodiments, cloud service 102 may be configured to perform operations corresponding to a method of chip verification. As an alternative example, in some embodiments, the cloud service 102 may be used to run a simulation platform for chip verification to perform operations corresponding to the method of chip verification.

In some embodiments, the communication network 104 may be any suitable combination of one or more wired and/or wireless networks. For example, the communication network 104 can include any one or more of the following: the internet, an intranet, a wide area network (Wide Area Network, WAN), a local area network (Local Area Network, LAN), a wireless network, a digital subscriber line (Digital Subscriber Line, DSL) network, a frame relay network, an asynchronous transfer mode (Asynchronous Transfer Mode, ATM) network, a virtual private network (Virtual Private Network, VPN), and/or any other suitable communication network. The user device 106 can be connected to the communication network 104 via one or more communication links (e.g., communication link 112), and the communication network 104 can be linked to the cloud service 102 via one or more communication links (e.g., communication link 114). The communication link may be any communication link suitable for transferring data between the user device 106 and the cloud service 102, such as a network link, a dial-up link, a wireless link, a hardwired link, any other suitable communication link, or any suitable combination of such links.

The user device 106 may comprise any one or more user devices adapted to send instructions for chip verification, to present the results of chip verification, to send operating instructions for modifying the chip. In some embodiments, user device 106 may comprise any suitable type of device. For example, in some embodiments, user devices 106 may include mobile devices, tablet computers, laptop computers, desktop computers, wearable computers, game consoles, media players, vehicle entertainment systems, and/or any other suitable type of user device.

In order to clearly illustrate the solution provided by this embodiment, the topology structure related to this embodiment is first described below. Taking the PCI bus as an example, the PCI bus may include a host bridge device, a PCI bridge device, and a bus device.

The HOST bridge device, also called HOST bridge, can be HOST bridge device with PCI (Peripheral Component Interconnect, peripheral component interconnect standard) topology structure root, can complete the conversion from CPU address to PCI domain address, and is used for isolating the memory domain of the chip where the operating system is located from PCI bus domain and managing PCI bus domain.

PCI bridge devices may be mounted to host bridge devices for expansion of bus devices.

Referring to the PCI topology structure shown in FIG. 2, the chip is connected with a host bridge device, the host bridge device is connected with a Bus0, and the PCI bridge device is mounted under the host bridge device through the Bus0 and is connected with the Bus device through a Bus 1. The bus device may be a mouse, a keyboard, a screen, or the like, which may be connected to the chip via a bus.

In general, when chip verification is performed, an operating system is started first, and PCI enumeration is performed. PCI enumeration specifically may include: creating a main bridge device, creating a root bus0 under the main bridge device, creating a plurality of PCI bridge devices under the root bus0, scanning all bus devices under the PCI bridge devices, judging whether the bus devices are bus exchange devices or not when the bus devices are scanned, if so, returning to the previous step to continue scanning the next bus device, if not, allocating resources for the bus devices until the scanning of all the bus devices is completed, and starting an operating system. Wherein the bus switching device is an adapter device that can extend the PCI bus such that more devices are connected to one PCl bus. The bus switching device does not need to be initialized, and resources can not be allocated to the target bus device when the target bus device is the bus switching device so as to save resources.

The inventor finds that the existing operating system starting process is complicated in steps, and especially the process of scanning the bus equipment consumes a lot of time, so that the starting process of the operating system is longer. Embodiments of the present application are further described below with reference to the accompanying drawings of embodiments of the present application.

Based on the above system, the embodiments of the present application provide a chip verification method, which is described below through a plurality of embodiments.

As shown in fig. 3, the chip verification method provided in the embodiment of the present application includes the following steps.

S102: and receiving a verification instruction for the chip.

The verification instruction of the Chip is used for starting a simulation platform for Chip verification to enable the simulation platform to perform verification operation on the Chip, wherein the Chip is any Chip capable of running an operating System and generating a main bridge device, such as a CPU (Central Processing Unit ), a GPU (Graphics Processing Unit, graphics processor), an SOC (System on Chip) and the like. Verifying operations against a chip includes testing various functions and interfaces of the chip.

It should be noted that, the scheme provided in this embodiment may be used for the pre-silicon verification and the post-silicon verification of the chip, which are both within the protection scope of the present application.

S104: in response to the validation instruction, the operating system is loaded and the host bridge device is created.

After receiving the verification instruction for the chip, the simulation platform can respond to the verification instruction to create host bridge equipment and load an operating system so as to prepare for verification of the chip.

The specific schemes for creating the host bridge device and loading the operating system may refer to the related art, and will not be described herein.

S106: if the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, starting the operating system, and verifying the chip according to the operating system.

According to the scheme provided by the embodiment, the condition for starting the operating system can be completed for the creation of the host bridge device and the loading of the operating system is completed. After the operating system is started, the chip can be formally verified based on the operating system.

Compared with the process of generally starting the operating system to perform chip verification, the scheme provided by the embodiment can start the operating system after the creation of the host bridge device is completed and the loading of the operating system is completed, so that the process of creating the PCI bridge device and traversing the bus device under the PCI bridge device in PCI enumeration is omitted, and the starting time of the operating system is greatly reduced.

In the embodiment of the application, only the first step of PCI enumeration is performed, namely, the creation of the host bridge device, and then the PCI enumeration flow is suspended. After the operating system is loaded and the creation of the host bridge device is completed, the operating system can be started and enters a developer mode, and as the process of scanning the PCI bridge device in the PCI enumeration process is omitted, when the starting of the operating system is completed, as shown in fig. 4, a user can only see the host bridge device through a chip and cannot see specific bus devices.

Referring to FIG. 5, two flow diagrams for starting an operating system for chip verification are shown.

The left side of FIG. 5 shows a flow diagram of a typical boot operating system, which begins to boot after receiving a chip authentication request and may begin PCI enumeration. PCI enumeration specifically includes creating a host bridge device, creating a PCI bridge device, which may include a plurality of; and then, all bus devices under the PCI bridge device can be scanned, whether the bus devices under the PCI bridge device are bus switching devices or not is judged, if yes, the next PCI bridge device is continuously scanned, if not, the next PCI bridge device is indicated to be the bus device, and resources can be allocated to the next PCI bridge device. After scanning all PCI bridge devices, the start of the operating system can be completed.

The right side of fig. 5 shows a flowchart of an operating system booting provided in the embodiment of the present application, where the operating system starts booting after receiving a chip verification request, and may start PCI enumeration. PCI enumeration specifically includes creating a host bridge device. If the creation of the main bridge device is determined to be completed and the loading of the operating system is determined to be completed, the starting of the operating device can be completed.

After the starting of the operating system is completed, if the verification process needs the bus equipment, PCI enumeration can be continued, namely PCI bridge equipment is continuously established, all the bus equipment under the PCI bridge equipment is scanned, whether the bus equipment under the PCI bridge equipment is bus exchange equipment is judged, if yes, the next PCI bridge equipment is continuously scanned, if not, the next PCI bridge equipment is indicated, and resources can be allocated for the next PCI bridge equipment. If the verification process does not require a bus device, the rest PCI enumeration process can be skipped, and the verification of the chip by using the operating system can be directly started.

In comparison, the starting time of the operating system in the scheme provided by the embodiment is smaller than that of the operating system under the general condition, so that the chip test speed can be greatly improved.

Referring to fig. 6, a chip verification method provided in an embodiment of the present application is shown, which is specifically as follows.

S201: and receiving a verification instruction for the chip.

S202: in response to the validation instruction, the operating system is loaded and the host bridge device is created.

S203: if the creation of the host bridge device is determined to be completed and the loading of the operating system is determined to be completed, starting the operating system.

S204: after the starting of the operating system is completed, the operating system enables the bus module to perform initialization operation on the bus device based on the host bridge device.

In this embodiment of the present application, the bus module is a module in the operating system for scanning a bus device, and the bus module may be a program for initializing the bus device when calling the host bridge device, or may be hardware for executing the program; the bus device is preferably the bus device required for chip verification to reduce operations. The bus module performs initialization operation on the bus device, which may be scanning the bus device, allocating resources to the bus device, assigning related variables of the bus device to default values, setting the bus device to default states, making the bus device ready for use, and the like, where different bus devices may perform corresponding initialization operations, which are all within the protection scope of the present application.

S205: and verifying the chip according to the operating system and the initialized bus equipment.

The operation system can verify the related functions or parameters of the chip based on the initialized bus device, and the specific content of the chip verification can refer to related technologies, which are not described herein.

In the embodiment of the application, the initialization operation can be performed on the bus device after the starting of the operating system is completed, and because the host bridge device is already established in the starting process of the operating system, the PCI enumeration process can be continuously executed on the basis of the established host bridge device to initialize the bus device, so that the initialization process of the bus device is simplified.

In some alternative embodiments, causing, by the operating system, the bus module to initialize the bus device based on the host bridge device includes: receiving target bus equipment which needs to be initialized through an operating system; enabling the bus module to establish PCI bridge equipment corresponding to the target bus equipment based on the host bridge equipment; and scanning the target bus equipment under the PCI bridge equipment, and distributing resources for the target bus equipment so as to initialize the target bus equipment.

In this embodiment of the present application, an instruction sent by a user may be received through a data interface, and a target bus device that needs to be initialized may be determined according to the instruction, or a target bus device list preset in a memory may be read to determine a target bus device that needs to be initialized.

The PCI bridge device corresponding to the target bus device is PCI bridge device between the host bridge device and the target bus device, which is also called PCI bridge, and resources can be allocated to the scanned target bus device through the target bus device scanned by the PCI bridge device to initialize the target bus device.

The resources allocated for the target bus may include bus resources, which are bus numbers (ID numbers of buses) allocated to devices, memory (memory) resources, and the like. According to the method and the device for initializing the target bus, the target bus device can be scanned and allocated with resources through the corresponding PCI bridge device, so that the initialization process of the target bus is orderly and well, and the error probability is reduced.

In some alternative embodiments, scanning a target bus device under a PCI bridge device and allocating resources for the target bus device to perform an initialization operation on the target bus device, including: scanning a target bus device under the PCI bridge device; judging whether the scanned target bus equipment is bus switching equipment or not, if not, allocating resources for the target bus equipment so as to initialize the target bus equipment.

As a possible implementation manner, the chip verification method provided in the embodiment of the present application further includes: after the starting of the operating system is completed, judging whether bus equipment is needed when the chip is verified; if so, continuing to execute the step of initializing the bus device by the bus module based on the host bridge device through the operating system; if not, the bus device is not initialized, and the chip is verified by the operating system.

In the embodiment of the application, the chip verification process is performed, and some verification needs to be completed by calling the bus device, and at this time, which bus devices are needed can be determined according to the received verification instruction for the chip. If the chip verification does not need to use a specific bus device, the embodiment will not initialize the bus device, so as to save the time required in the verification process; if the chip verification process needs to use the bus device, the scheme provided by the embodiment can reinitialize the required bus device after the operating system is started, so as to meet the chip verification requirement.

In some alternative embodiments, verifying the chip according to the operating system includes: and running a test program for chip verification in the operating system to verify the chip. Moreover, the method provided by the embodiment of the application further comprises the following steps: receiving a modification operation for modifying the chip, and determining modification content corresponding to the modification operation; and receiving a restart operation of the operating system, and in response to the restart operation, performing the steps of loading the operating system and creating the host bridge device to effect the modified content.

In this embodiment of the present application, the test program is used to verify the chip, for example, to verify whether the function of the chip can be normally implemented, whether the computing capability of the chip reaches the expected effect, and so on. It should be understood that the chip is generally used to run an operating system when actually used, and then the chip verification may be performed by the operating system running in the chip.

In addition, in the embodiment of the application, the modification operation on the chip can be performed in the verification process, and the operating system is restarted after the modification is completed so that the modification on the chip is effective, and the verification on the modified chip is continued. When the chip defects are found through chip verification, the embodiment of the application can receive corresponding modification operation to modify the chip, is simple and convenient to operate and can save the chip development time.

As shown in fig. 7, an embodiment of the present application provides a chip verification device, which includes a receiving module, a starting module, and a verification module.

The receiving module is used for receiving a verification instruction aiming at the chip.

The starting module is used for responding to the verification instruction, loading an operating system and creating the host bridge device.

The verification module is used for starting the operating system when the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, and verifying the chip according to the operating system.

The chip verification device provided in the embodiment of the present application and the foregoing chip verification method embodiment are based on the same inventive concept, so that the same effect can be achieved, and the specific implementation process can be referred to the description in the foregoing chip verification method embodiment, and no further description is given here.

The embodiment of the application provides electronic equipment. The method comprises the following steps: referring to fig. 8, a schematic structural diagram of an electronic device according to a fifth embodiment of the present application is shown, and specific embodiments of the present application do not limit specific implementations of the electronic device.

As shown in fig. 8, the electronic device may include: a processor 502, a communication interface (Communications Interface) 504, a memory 506, and a communication bus 508.

Wherein:

processor 502, communication interface 504, and memory 506 communicate with each other via communication bus 508.

A communication interface 504 for communicating with other electronic devices or servers.

The processor 502 is configured to execute the program 510, and may specifically perform relevant steps in the above-described chip verification method embodiment.

In particular, program 510 may include program code including computer-operating instructions.

The processor 502 may be a CPU or a specific integrated circuit ASIC (Application Specific Integrated Circuit) or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors comprised by the smart device may be the same type of processor, such as one or more CPUs; but may also be different types of processors such as one or more CPUs and one or more ASICs.

A memory 506 for storing a program 510. Memory 506 may comprise high-speed RAM memory or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.

The program 510 may include a plurality of computer instructions, and the program 510 may specifically enable the processor 502 to perform operations corresponding to the chip verification method described in any one of the foregoing method embodiments through the plurality of computer instructions.

The specific implementation of each step in the program 510 may refer to the corresponding steps and corresponding descriptions in the units in the above method embodiments, and have corresponding beneficial effects, which are not described herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.

The present application also provides a computer storage medium having stored thereon a computer program which, when executed by a processor, implements the method described in any of the foregoing method embodiments. The computer storage media includes, but is not limited to: a compact disk read Only (Compact Disc Read-Only Memory, CD-ROM), random access Memory (Random Access Memory, RAM), floppy disk, hard disk, magneto-optical disk, or the like.

Embodiments of the present application also provide a computer program product including computer instructions that instruct a computing device to perform operations corresponding to any one of the chip verification methods in the method embodiments described above.

In addition, it should be noted that, the information related to the user (including, but not limited to, user equipment information, user personal information, etc.) and the data related to the embodiment of the present application (including, but not limited to, data for verifying the chip, data for analyzing, stored data, presented data, etc.) are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide a corresponding operation entry for the user to select authorization or rejection.

It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present application may be split into more components/steps, and two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the purposes of the embodiments of the present application.

The above-described methods according to embodiments of the present application may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the methods described herein may be processed by such software on a recording medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware such as an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or field programmable or gate array (Field Programmable Gate Array, FPGA). It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a Memory component (e.g., random access Memory (Random Access Memory, RAM), read-Only Memory (ROM), flash Memory, etc.) that can store or receive software or computer code that, when accessed and executed by the computer, processor, or hardware, performs the methods described herein. Furthermore, when a general purpose computer accesses code for implementing the methods illustrated herein, execution of the code converts the general purpose computer into a special purpose computer for performing the methods illustrated herein.

Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

The above embodiments are only for illustrating the embodiments of the present application, but not for limiting the embodiments of the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of the embodiments of the present application should be defined by the claims.

Claims

1. A chip authentication method comprising:

receiving a verification instruction for a chip;

loading an operating system and creating a host bridge device in response to the verification instruction;

if the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, starting the operating system, and verifying the chip according to the operating system;

wherein the verifying the chip according to the operating system includes:

after the starting of the operating system is completed, enabling a bus module to perform initializing operation on the bus equipment based on the host bridge equipment through the operating system; verifying the chip according to the operating system and the initialized bus equipment;

the enabling the bus module to initialize the bus device based on the host bridge device through the operating system comprises the following steps:

receiving target bus equipment which needs to be initialized through the operating system; enabling the bus module to establish PCI bridge equipment corresponding to the target bus equipment based on the host bridge equipment; and scanning the target bus equipment under the PCI bridge equipment, and distributing resources for the target bus equipment so as to initialize the target bus equipment.

2. The method of claim 1, wherein the scanning the target bus device under the PCI bridge device and allocating resources for the target bus device to perform an initialization operation on the target bus device comprises:

scanning the target bus device under the PCI bridge device;

judging whether the scanned target bus equipment is bus switching equipment or not, if not, allocating resources for the target bus equipment so as to initialize the target bus equipment.

3. The method of claim 1, wherein the method further comprises: after the starting of the operating system is completed, judging whether the bus equipment is needed when the chip is verified;

if so, continuing to execute the step of enabling a bus module to initialize the bus device based on the host bridge device through the operating system;

if not, the bus equipment is not initialized, and the chip is verified through the operating system.

4. The method of claim 1, wherein the verifying the chip according to the operating system comprises:

running a test program for chip verification in the operating system to verify the chip;

the method further comprises the steps of:

receiving a modification operation for modifying the chip, and determining modification content corresponding to the modification operation;

and receiving a restart operation of the operating system, and in response to the restart operation, executing the steps of loading the operating system and creating a host bridge device to validate the modified content.

5. A chip authentication apparatus comprising:

the receiving module is used for receiving a verification instruction aiming at the chip;

the starting module is used for responding to the verification instruction, loading an operating system and creating host bridge equipment;

the verification module is used for starting the operating system when the establishment of the host bridge equipment is determined to be completed and the loading of the operating system is determined to be completed, and verifying the chip according to the operating system;

wherein, the verification module is further configured to:

6. An electronic device, comprising: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus;

the memory is configured to store at least one executable instruction that causes the processor to perform operations corresponding to the method of any one of claims 1-4.

7. A computer storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-4.

8. A computer program product comprising computer instructions that instruct a computing device to perform operations corresponding to the method of any one of claims 1-4.