CN116204455B

CN116204455B - Cache management system, method, private network cache management system and equipment

Info

Publication number: CN116204455B
Application number: CN202310493466.9A
Authority: CN
Inventors: 王盟; 贾浩楠; 李陛毅; 张鹏宇; 洪国春; 姚怡东; 杨光
Original assignee: Alibaba Damo Institute Hangzhou Technology Co Ltd
Current assignee: Alibaba Damo Institute Hangzhou Technology Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-09-22
Anticipated expiration: 2043-04-28
Also published as: CN116204455A

Abstract

The embodiment of the application provides a cache management system, a cache management method, a private network cache management system and private network cache management equipment. The cache management system includes: the computing processing module comprises a cache resource for realizing data processing operation, wherein the last level of cache in the cache resource comprises a data direct-connection cache; the data surface function module is operated on the calculation processing module and is used for acquiring a data packet to be processed and processing the data packet by utilizing a cache resource; the cache management module is in communication connection with the data surface functional module and the calculation processing module and is used for acquiring data packet attributes corresponding to the data packets and data receiving attributes corresponding to the data surface functional module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache. In the embodiment, flexible adjustment and management operation of the cache resources in the computing processing module are effectively realized, and the condition of improper use of the cache resources is reduced.

Description

Cache management system, method, private network cache management system and equipment

Technical Field

The present application relates to the field of network technologies, and in particular, to a cache management system, a method, a private network cache management system, and an apparatus.

Background

Currently, for a single core processor (Central Processing Unit, abbreviated as CPU), the CPU may include a plurality of CPU cores, each of the CPU cores has a first Level Cache L1 and a second Level Cache L2, and all the CPU cores share a third Level Cache L3, where the L3 is also called a Last Level Cache (LLC), and the access sequence of the CPU processing data is as follows: l1- > L2- > L3- > memory. In recent years, a Data Direct I/O (DDIO) technology is added to the CPU architecture, so that when a Data packet is processed, the Data packet can be directly loaded from the network card to the LLC.

In the application scenario of data processing, efficient use of LLC can achieve high performance, however, because LLC resources are limited, if LLC is improperly used, access data of CPU is easy to leak from memory, thus greatly reducing network processing performance.

Disclosure of Invention

The embodiment of the application provides a cache management system, a cache management method, a private network cache management system and private network cache management equipment, which reduce the memory leakage condition caused by improper LLC use, thereby ensuring the network processing performance.

In a first aspect, an embodiment of the present application provides a cache management system, including:

The computing processing module comprises a cache resource for realizing data processing operation, wherein the last level of cache in the cache resource comprises a data direct-connection cache;

the data surface function module is operated on the calculation processing module and is used for acquiring a data packet to be processed and processing the data packet by utilizing the cache resource;

the cache management module is in communication connection with the data surface functional module and the calculation processing module and is used for determining data packet attributes corresponding to the data packets and data receiving attributes corresponding to the data surface functional module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

In a second aspect, an embodiment of the present application provides a private network cache management system, including:

the private network calculation processing module comprises a cache resource for realizing private network data processing operation, wherein the last level of cache in the cache resource comprises a data direct-connection cache;

the private network data plane function module is operated on the private network calculation processing module and is used for acquiring a private network data packet to be processed and processing the private network data packet by utilizing the cache resource;

The private network cache management module is in communication connection with the private network data surface function module and the private network calculation processing module and is used for determining data packet attributes corresponding to the private network data packets and data receiving attributes corresponding to the private network data surface function module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

In a third aspect, an embodiment of the present application provides a cache management method, including:

acquiring data packet attributes of a data plane functional module receiving data packets and data receiving attributes corresponding to the data plane functional module;

determining a cache resource for realizing data processing operation, wherein the cache resource comprises a data through cache, and the last level cache in the cache resource is used for realizing data processing operation, and the data plane function module runs on the computing processing module;

and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

In a fourth aspect, an embodiment of the present application provides a cache management apparatus, including:

the first acquisition module is used for acquiring the data packet attribute of the data packet received by the data plane functional module and the data receiving attribute corresponding to the data plane functional module;

The first determining module is used for determining cache resources for realizing data processing operation, wherein the cache resources comprise data through caches, and the data plane functional module runs on the computing processing module;

and the first processing module is used for carrying out buffer management based on the data packet attribute, the data receiving attribute and the data through buffer memory.

In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor; the memory is configured to store one or more computer instructions, where the one or more computer instructions, when executed by the processor, implement the cache management method shown in the third aspect.

In a sixth aspect, an embodiment of the present application provides a computer storage medium storing a computer program, where the computer program causes a computer to implement the cache management method shown in the third aspect.

In a seventh aspect, embodiments of the present application provide a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to perform the steps in the cache management method shown in the third aspect described above.

In an eighth aspect, an embodiment of the present invention provides a cache management method, which is applied to a cache management device, where the cache management device is deployed on a public cloud, and a load balancer is deployed on the public cloud, and the load balancer runs on a computing processor; the method comprises the following steps:

acquiring a data packet attribute of a data packet received by a load balancer and a data receiving attribute corresponding to the load balancer;

determining cache resources for realizing data processing operation, wherein the last level of cache in the cache resources comprises a data through cache, and the load balancer runs on the computing processor;

In a ninth aspect, an embodiment of the present invention provides a cache management device, where the cache management device is deployed on a public cloud, and a load balancer is deployed on the public cloud, and the load balancer runs on a computing processor; the device comprises:

the second acquisition module is used for acquiring the data packet attribute of the data packet received by the load balancer and the data receiving attribute corresponding to the load balancer;

A second determining module, configured to determine a cache resource included in a computing processor for implementing a data processing operation, where a last level of cache in the cache resource includes a data through cache, where the load balancer runs on the computing processor;

and the second processing module is used for carrying out buffer management based on the data packet attribute, the data receiving attribute and the data through buffer memory.

In a tenth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor; the memory is configured to store one or more computer instructions, where the one or more computer instructions, when executed by the processor, implement a cache management method as described in the eighth aspect.

In an eleventh aspect, an embodiment of the present application provides a computer storage medium storing a computer program, where the computer program causes a computer to implement the cache management method described in the eighth aspect.

In a twelfth aspect, embodiments of the present application provide a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to perform the steps in the cache management method shown in the eighth aspect described above.

According to the cache management system, the method, the private network cache management system and the equipment, the data packet attribute corresponding to the data packet and the data receiving attribute corresponding to the data plane function module are obtained through the cache management module, the through data cache included in the calculation processing module is determined, and then the cache management is carried out based on the data packet attribute, the data receiving attribute and the through data cache, so that flexible adjustment and management operation on cache resources in the calculation processing module are effectively realized, the situation of improper use of the cache resources is reduced, the problem of network processing performance reduction due to memory leakage is avoided, the network processing performance is guaranteed, the practicability of the method is improved, and the popularization and application of the market are facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a CPU cache architecture provided in the related art;

FIG. 2 is a schematic diagram of a cache management system according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a private network cache management system according to an embodiment of the present application;

fig. 4 is a schematic diagram of a cache management method according to an embodiment of the present application;

FIG. 5 is a flowchart of a cache management method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a third level cache according to an embodiment of the present application;

fig. 7 is a schematic flow chart of performing buffering management based on the data packet attribute, the data receiving attribute and the data direct-connection buffer according to the embodiment of the present application;

FIG. 8 is a flowchart illustrating another cache management method according to an embodiment of the present application;

FIG. 9 is a flowchart illustrating another cache management method according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a cache management method according to an embodiment of the present application;

FIG. 11 is a flowchart illustrating a method for cache management according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a cache management method according to an embodiment of the present application;

fig. 13 is a schematic diagram of a vehicle control method according to an embodiment of the present application;

Fig. 14 is a schematic diagram of a control method of a virtual reality device according to an embodiment of the present application;

FIG. 15 is a schematic structural diagram of a cache management device according to an embodiment of the present application;

FIG. 16 is a schematic structural diagram of an electronic device corresponding to the cache management apparatus provided in the embodiment shown in FIG. 15;

FIG. 17 is a schematic diagram of another cache management apparatus according to an embodiment of the present application;

FIG. 18 is a schematic structural diagram of an electronic device corresponding to the cache management apparatus provided in the embodiment shown in FIG. 17;

fig. 19 is a schematic structural view of a vehicle control device according to an embodiment of the present application;

fig. 20 is a schematic structural view of an electronic device corresponding to the vehicle control apparatus provided in the embodiment shown in fig. 19;

fig. 21 is a schematic structural diagram of a control device of a virtual reality device according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of an electronic device corresponding to the control device of the virtual reality device provided in the embodiment shown in fig. 21.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude that an additional identical element is present in a commodity or system comprising the element.

In addition, the sequence of steps in the method embodiments described below is only an example and is not strictly limited.

Definition of terms:

RAN: radio Access Network, radio access network.

DU: distributed units, are responsible for handling higher real-time functions, i.e. physical layer functions and other protocol functions required for real-time.

5GC: the 5G core,5G core network, is the core of the 5G mobile network and is responsible for management, control and forwarding.

CU: centralized Unit, responsible for handling non-real time wireless higher layer protocol functions.

UPF: user Plane Function, the user plane function is responsible for the related functions of routing and forwarding of the 5G core network user plane data packet.

NFV: network Function Virtualization network functions are virtualized in an effort to decouple software network functions from hardware.

NF: network Function, the Function in NFV that is responsible for handling Network packets.

DPDK: data Plane Development Kit, open source data plane development suite, can accelerate packet processing in user mode.

LLC: last Level Cache, last Level Cache, common CPU Cache is divided into three levels L1, L2 and L3, and L3 is LLC.

DDIO: data Direct I/O is a platform technology for Data Direct connection, and aims to enable a server to process Data of a network interface more quickly, improve system throughput, reduce delay and reduce energy consumption.

PCIE: PCI Express is a high-speed serial computer expansion bus standard.

PPS: packet Per Second number of packets processed per second.

CAT: cache Allocation Technology, a published cache allocation technology tool kit.

In order to facilitate understanding of the technical solutions provided by the embodiments of the present application by those skilled in the art, the following briefly describes related technologies: with the rapid development of communication technology, the application of the 5G network is more and more widespread, and in general, the 5G network may be divided into a Radio Access Network (RAN), a bearer network, and a core network (5 GC), where the RAN is used for user access and processing of radio signals, and specifically, the RAN may include a Centralized Unit (CU) and a Distributed Unit (DU). The 5GC core network is responsible for processing data from the RAN, and performs routing and forwarding related functions according to a packet request input by a user, where the 5GC core network includes a plurality of network elements, such as an access and mobility management function (AMF), a Session Management Function (SMF), a User Plane Function (UPF), and the like.

For a 5G network, when the network deployment is performed, a network function virtualization (Network Function Virtualization, abbreviated as NFV) architecture is adopted in the design and implementation of the 5G network, and the network element can be implemented in a software manner and run in a general x86 server. The DU and UPF are used as the data surface processing functions of the core and are mainly responsible for data surface processing and transmission. In recent years, a Network Function (NF) of a data plane widely adopts a data plane development kit (Data Plane Development Kit, DPDK) to accelerate packet processing and forwarding.

For an electronic device, the device may include two core processor (Central Processing Unit, abbreviated as CPU) chips, referring to fig. 1, each CPU chip corresponds to one CPU, for a single CPU, 24 CPU cores may be included, each core has an L1/L2 cache, all cores of the CPU chip share an L3 cache (i.e., the last level cache LLC), so that when the CPU processes data, the L1 cache is accessed first, if the L1 cache matches fail (i.e., the data is not in the L1 cache), the L2 cache is accessed, and so on. In summary, the data access sequence processed by the CPU is: l1 cache- > L2 cache- > L3 cache- > memory, which may be dynamic random access memory (Dynamic Random Access Memory, DRAM for short) or double rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR for short).

In recent years, in order to improve the quality and effect of Data processing, a Data Direct I/O (DDIO) technology is added to a CPU architecture, so that when a Data packet is processed, the Data packet can be directly loaded from a network card to an LLC, instead of being loaded from the network card to a memory, and the Data packet is processed and then loaded from the memory to the LLC.

Specifically, taking a 2.7GHz CPU as an example, when the CPU processes a packet, if the packet is acquired from the memory, 250 CPU operation cycles are required, and the access delay is 70 ns. Whereas if the data packet is directly obtained from the LLC, the CPU run time required to access the LLC is about 44-70, with an access latency of 13-20 nanoseconds. It can be seen that the memory access latency is about 4-6 times that of LLC. Therefore, the DDIO technology can effectively reduce the waiting time of the CPU caused by waiting for accessing the memory, so as to greatly accelerate the processing efficiency of the data packet, so that the NF based on the DPDK (e.g. DU in the RAN, UPF network element in 5GC, etc.) can process higher traffic, i.e. can obtain higher number of data packets processed per second (Packet Per Second, abbreviated as PPS).

However, in the above-mentioned CPU data processing manner, the problems of direct memory access (Direct Memory Access, abbreviated as DMA) leakage and cache contention are liable to occur, and specifically, in view of the problem of DMA leakage, in a high-speed data processing scenario, efficient use of LLC can achieve high performance, however, LLC resources are limited, if LLC is improperly used, for example: when the preconfigured reception descriptor (rx descriptor) is not suitable for the current scene, the access data of the CPU is easy to leak, thus greatly reducing the network processing performance.

In addition, like NF in NFV, UPF belongs to IO applications, except that: the UPF has a relatively complex logic implementation and a relatively large flow table (flow table), that is, a Packet Detection Rule (PDR) in the UPF, and the UPF performs a packet forwarding operation according to a five-tuple in the PDR. Thus, both the flow table and the data packet may occupy the LLC, for example, at 10G throughput, assuming 10k users, the flow table is 10k+; when the throughput reaches 100G, the flow table is 100deg.C+, which will occupy non-negligible LLC resources.

When the CPU does not process the data packet in the LLC in time (e.g., a flow table matching failure or other reasons), the CPU needs to wait for access to the memory result, and the data packet in this waiting time also reaches the LLC through the DDIO mechanism. In a high-speed (e.g., 100G) traffic scenario, if a flow table matching failure (i.e., miss) occurs frequently, the CPU latency increases, more accumulated packets in the LLC cannot be processed, and after more packets consume LLC resources, the packets in the LLC are replaced by the packets in the LLC, and the packets in the LLC enter the memory. As above, the phenomenon that packets arrive at the LLC and are forced into memory is called DMA leakage. After this occurs, the CPU acquires the packet from the LLC, and memory leakage (cache) occurs, which needs to be acquired from the memory, and in summary, DMA leakage may cause performance degradation, which is a significant decline in UPF throughput.

In addition, the core network also causes resource competition, in a large packet scenario (for example, the packet length is about 1500 bytes), the packet occupies a large space in the LLC, meanwhile, the UPF in the 5GC core network also maintains many flow tables and occupies resources in the LLC, so that the packet and the flow tables compete for use of LLC resources, thereby causing performance degradation.

In order to solve the above technical problems, the present embodiment provides a cache management system, a method, a private network cache management system, and a device, where the cache management system may be applied to a 5G core network or a base station RAN, and when the cache management system is applied to the 5G core network, the cache management method for the 5G core network may be implemented; when the cache management device is applied to the RAN, a cache management method aiming at the RAN can be realized. At this time, the cache management system may be executed in a cloud end, where a plurality of computing nodes (cloud servers) may be deployed, and each computing node has processing resources such as computation and storage. At the cloud, a service may be provided by multiple computing nodes, although one computing node may provide one or more services. The cloud may provide the service by providing a service interface to the outside, and the user invokes the service interface to use the corresponding service. The service interface includes a software development kit (Software Development Kit, abbreviated as SDK), an application program interface (Application Programming Interface, abbreviated as API), and the like.

Specifically, referring to fig. 2, the cache management system in this embodiment may include: the system comprises a calculation processing module, a data surface functional module and a cache management module:

the computing processing module comprises a cache resource for realizing data processing operation, wherein the last level of cache in the cache resource comprises a data through cache; the above-described calculation processing module may be implemented as at least one of: core processors (Central Processing Unit, CPU for short), graphics processors (Graphic Processing Unit, GPU for short), general-purpose graphics processors (General-Purpose Graphics Processing Unit, GPGPU for short), etc., and those skilled in the art can flexibly adjust and configure the computing processing module according to specific application scenarios or application requirements.

In addition, the cache resources included in the computing processing module may be multi-level cache resources, such as: the computing processing module may include a third-level cache resource, a fourth-level cache resource, a fifth-level cache resource, or the like, and for the cache resource included in the computing processing module, a last-level cache in the cache resource may include a data direct cache DDIO, where the data direct cache DDIO is used to implement a data forwarding operation through a platform technology of data direct.

The data surface function module is operated on the calculation processing module and is used for acquiring a data packet to be processed and processing the data packet by utilizing a cache resource; the above-mentioned data plane function module is used for being responsible for processing the function of the network data packet, in some examples, the corresponding data plane function module in different application scenarios may correspond to different implementation manners, for example, in the application scenario of the 5G core network, the data plane function module may be implemented as a UPF network element in the core network; in the application scenario of the RAN, the data plane function module may be implemented as a DU unit in the RAN; or in the application scenario of public cloud, the data plane function module can be implemented as a load balancer deployed on the public cloud, and the load balancer can implement load balancing operation, at this time, the cache management system and the load balancer can be deployed on the public cloud. In addition, for the data packets to be processed obtained by the data plane function module, different application scenarios may correspond to different types of data packets, for example: in the private network scenario, the data packet may be implemented as a private network data packet; in the context of a communication network, a data packet may be implemented as a communication data packet.

The cache management module is in communication connection with the data surface functional module and the calculation processing module and is used for acquiring data packet attributes corresponding to the data packets and data receiving attributes corresponding to the data surface functional module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

Specifically, in order to enable the cache management module to implement the cache management operation, a data packet attribute corresponding to the data packet and a data receiving attribute corresponding to the data plane function module may be acquired, in some examples, after the data plane function module acquires the data packet to be processed, the cache management module may acquire, by means of the data plane function module, the data packet attribute corresponding to the data packet, where the data packet attribute may include at least one of: the average size of the data packets received by the data plane functional module, the median size of the data packets received by the data plane functional module and the like; the data reception attribute corresponding to the data plane function module may include at least one of: an upper limit parameter for the number of data packets that the data plane function module can receive, a reception descriptor for identifying an upper limit for the number of data packets that the data plane function module can receive, and the like.

In addition, since the data caching operation is often related to the data through cache included in the calculation processing module, in order to enable the cache management operation, the data through cache included in the cache resource may be determined by the calculation processing module, and after the data packet attribute, the data receiving attribute, and the data through cache are acquired, the cache management operation may be performed based on the data packet attribute, the data receiving attribute, and the data through cache.

According to the cache management system provided by the embodiment, the data packet attribute corresponding to the data packet and the data receiving attribute corresponding to the data plane function module are obtained through the cache management module, the data direct-connection cache included in the calculation processing module is determined, and then the cache management is carried out based on the data packet attribute, the data receiving attribute and the data direct-connection cache, so that the flexible adjustment and management operation on the cache resources in the calculation processing module is effectively realized, the condition of improper use of the cache resources is reduced, the problem of network processing performance reduction caused by memory leakage is avoided, the network processing performance is guaranteed, and the practicability of the system is improved.

On the basis of the above embodiment, with continued reference to fig. 2, when the cache management module performs cache management based on the data packet attribute, the data receiving attribute and the data through cache, the cache management module is configured to perform analysis processing on the data packet attribute, the data receiving attribute and the data through cache to obtain management information; and performing cache management operation based on the management information.

In other examples, in order to ensure stable cache management operation, the cache management operation may be implemented by detecting whether there is a detection result of a cache use problem, where, when the cache management module performs cache management based on the packet attribute, the data receiving attribute, and the data through cache, the cache management module is configured to: detecting whether a cache use problem exists or not based on the data packet attribute, the data receiving attribute and the data direct-connection cache; if the cache using problem exists, determining a target data receiving attribute based on the data packet attribute and the data direct cache; updating the data reception attribute to the target data reception attribute.

In the process of processing the data packet by using the data plane function module, the use condition of the buffer memory can be embodied by the data packet attribute, the data receiving attribute and the data through buffer memory, so that after the data packet attribute, the data receiving attribute and the data through buffer memory are acquired, the data packet attribute, the data receiving attribute and the data through buffer memory can be analyzed and processed to detect whether the buffer memory use problem exists.

In some examples, the buffer management module stores a pre-trained neural network model for detecting whether a buffer usage problem exists, and after the data packet attribute, the data receiving attribute and the data through buffer are acquired, the data packet attribute, the data receiving attribute and the data through buffer are input into the neural network model to obtain a detection result output by the neural network model, where the detection result may include a detection result that the buffer usage problem exists or a detection result that the buffer usage problem does not exist.

In other examples, the cache management module may detect whether a cache usage problem exists through the neural network model, and may directly perform a detection operation based on the data packet attribute, the data receiving attribute, and the data pass-through cache, where, when the cache management module detects whether the cache usage problem exists based on the data packet attribute, the data receiving attribute, and the data pass-through cache, the cache management module is configured to: determining a received data quantity parameter based on the data packet attribute and the data receiving attribute; based on the received data amount parameter and the data through cache, whether a cache use problem exists is detected.

Wherein after the packet attributes and the data reception attributes are obtained, the packet attributes and the data reception attributes may be analyzed, so that a received data amount parameter may be determined, which may be determined by a product value between the packet attributes and the data reception attributes in some examples. For example 1, the packet attributes may include an average size of received packets, and the data reception attributes may include a reception descriptor for identifying an upper limit on the number of packets that the data plane function module can receive; at this time, when the cache management module determines the received data amount parameter based on the packet attribute and the data receiving attribute, the cache management module is configured to: obtaining a product value between the average size and the received descriptor; determining a received data quantity parameter based on the product value; in some examples, the product value may be determined as the received data amount parameter; or, determining the sum value or the product value between the product value and the preset parameter as the received data amount parameter.

For example 2, the packet attributes may include a median size of received packets, and the data reception attributes may include a reception descriptor for identifying an upper limit on the number of packets that the data plane function module can receive; at this time, when the cache management module determines the received data amount parameter based on the packet attribute and the data receiving attribute, the cache management module is configured to: acquiring a product value between the median size and the received descriptor; determining a received data quantity parameter based on the product value; in some examples, the product value may be determined as the received data amount parameter; or, determining the sum value or the product value between the product value and the preset parameter as the received data amount parameter.

After the received data quantity parameter and the data direct-connection buffer are obtained, the received data quantity parameter and the data direct-connection buffer can be analyzed and processed to detect whether a buffer use problem exists; in some examples, when the cache management module detects whether there is a cache usage problem based on the received data amount parameter and the data pass-through cache, the cache management module is configured to: determining the direct cache size of the data direct cache; when the received data quantity parameter is smaller than or equal to the size of the direct-connection cache, determining that no cache use problem exists; and when the received data quantity parameter is larger than the size of the direct-connection buffer, determining that the buffer use problem exists.

For example, the receive descriptor may be rxdescriptor, the average size may be packetsize, the through buffer size may be DDIOsize, and then the rxdescriptor may be analyzed and compared with the DDIOsize, whereWhen DDIOsize is used, the direct-connection buffer memory size can support and meet the whole size of the data packet to be processed, and then the current buffer memory use problem can be determined; when rxdescriptor is Packetsize > DDIOsize, the through buffer size cannot support or satisfy the overall size of the data packet to be processed, and thus the overall size of the data packet to be processed can be determined There is always a cache usage problem.

Specifically, when the detection result indicates that the cache use problem exists, in order to alleviate or avoid the problem of memory leakage, it is indicated that the obtained data receiving attribute capable of identifying the upper limit of the number of the data packets that can be received by the data plane functional module is not suitable for the current application scenario, so that the data packet attribute and the data direct cache can be analyzed and processed, and the target receiving descriptor can be determined.

In some examples, determining the target data reception attribute based on the packet attribute and the data pass-through cache may include: determining the direct cache size of the data direct cache; acquiring the ratio between the size of the direct buffer and the attribute (average size or median size) of the data packet; and determining a target data receiving attribute based on the ratio, wherein the target data receiving attribute is a positive integer less than or equal to the ratio.

For example, taking a receive descriptor as a data receiving attribute and an average size as a data packet attribute, a receive descriptor may be an rxdescriptor, an average size may be a packetsize, and a through buffer size may be a DDIOsize, where the rxdescriptor is smaller than or equal to the packetsize may effectively alleviate a memory leakage problem, and if the current rxdescriptor is not suitable for a current application scenario, a ratio between the through buffer size and the average size, that is, the DDIOsize/packetsize, may be obtained, and then a target receive descriptor may be determined based on the ratio, where the target receive descriptor is a positive integer smaller than or equal to the ratio, thereby effectively ensuring accuracy and reliability of determining the target receive descriptor.

It should be noted that the target reception descriptor may be determined not only in the above manner, but also in other manners, for example: a machine learning model or a neural network model for determining the target reception descriptor is trained in advance, and then the average size and the through buffer size can be analyzed and processed by using the machine learning model or the neural network model, so that the target reception descriptor and the like can be determined, as long as the accuracy and reliability of determining the target reception descriptor can be ensured.

In other examples, when the detection result indicates that there is no cache usage problem, the data processing operation at this time may be performed stably, so that the current receive descriptor may be kept unchanged.

In this embodiment, the cache management module detects whether a cache use problem exists based on the packet attribute, the data receiving attribute, and the data through cache; if the cache using problem exists, determining a target data receiving attribute based on the data packet attribute and the data direct cache; the data receiving attribute is updated to be the target data receiving attribute, so that the technical scheme for flexibly adjusting the data receiving attribute is effectively realized, and the adjusted data receiving attribute can effectively relieve the problem of memory leakage, thereby effectively improving the network processing performance and further improving the practicability of the system.

On the basis of any one of the foregoing embodiments, with continued reference to fig. 2, in order to further ensure the quality and effect of the cache management operation, the cache management system in this embodiment flexibly adjusts the size of the direct cache of the data, where, at this time, the cache management module in this embodiment is further configured to: in the process of processing the data packets, acquiring a first data packet loss ratio corresponding to the last level of buffer memory and/or a second data packet loss ratio corresponding to the data through buffer memory; the through buffer size is adjusted based on the first packet loss ratio and/or the second packet loss ratio.

The foregoing embodiments may include three implementation manners for flexibly adjusting the size of the through cache, which are specifically:

the implementation mode is as follows:

the cache management module is used for: acquiring a first data packet loss ratio corresponding to the last level of buffer memory in the process of processing the data packet; the through buffer size is adjusted based on the first packet loss ratio.

Wherein, in the process of processing the data packet, the first data packet loss ratio corresponding to the last level buffer may be acquired, and in some examples, when the buffer management module acquires the first data packet loss ratio corresponding to the last level buffer, the buffer management module is configured to: acquiring the total number of data access operations in a preset time period; counting the times of not matching the related data (namely, the miss condition occurs) through the last level of cache; and determining the ratio of the number of times of not matching the related data to the total number of times as a first data packet loss ratio.

Taking LLC as the last level of cache, since the first packet loss ratio can represent the usage of the computation processing cache used by the computation processing module (e.g., CPU, GPU, etc.) in LLC, the computation processing cache and the through cache form a complete LLC, so that the first packet loss ratio can also represent the usage of the through cache. Thus, after the first packet loss ratio is obtained, the through-buffer size may be adjusted based on the first packet loss ratio, which may include, in some examples: when the first data packet loss ratio is larger than a first preset threshold value, reducing the size of the through cache; and when the first data packet loss ratio is smaller than or equal to a first preset threshold value, increasing the size of the through cache.

Specifically, after the first data packet loss ratio is obtained, the first data packet loss ratio may be compared with a first preset threshold, and when the first data packet loss ratio is greater than the first preset threshold, this indicates that the first data packet loss ratio at this time is greater, and the use of the calculation processing buffer is relatively tense, and at this time, the size of the through buffer needs to be reduced, so that the calculation processing buffer is increased. Correspondingly, when the first data packet loss ratio is smaller than or equal to a first preset threshold value, the first data packet loss ratio is smaller, the use of the calculation processing buffer memory is looser, otherwise, the use of the data through buffer memory is more tense, and at the moment, the size of the through buffer memory needs to be increased, and meanwhile, the calculation processing buffer memory is reduced.

In other examples, the through buffer size may be adjusted not only directly through the first preset threshold and the first packet loss ratio, but also in other manners, where, when the buffer management module adjusts the through buffer size based on the first packet loss ratio, the buffer management module is configured to: acquiring historical data packet loss rate; and determining the change trend of the data packet loss ratio based on the historical data packet loss ratio and the first data packet loss ratio, and if the change trend of the data packet loss ratio is an ascending trend, indicating that the use of the calculation processing buffer memory is strained, at the moment, reducing the size of the through buffer memory and simultaneously increasing the calculation processing buffer memory. Correspondingly, if the trend of the data packet loss ratio is a decreasing trend, the calculation processing buffer memory is loosely used, and at this time, in order to further improve the quality and efficiency of data processing, the size of the through buffer memory can be increased, that is, the calculation processing buffer memory is reduced, so that flexible adjustment operation on the size of the through buffer memory based on the first data packet loss ratio is effectively realized.

The implementation mode II is as follows:

the cache management module is used for: acquiring a second data packet loss ratio corresponding to the data through cache in the process of processing the data packets; the through cache size is adjusted based on the second packet loss ratio.

Wherein, during processing of the data packet, a second data packet loss ratio corresponding to the data through buffer may be obtained, and in some examples, when the buffer management module obtains the second data packet loss ratio corresponding to the data through buffer, the buffer management module is configured to: acquiring the total number of data access operations in a preset time period; counting the times of the data pass through cache without matching the related data (namely, the miss condition occurs); and determining the ratio of the times of not matching the related data to the total times as a second data packet loss ratio.

Since the second data packet loss ratio can represent the usage of the data through buffer DDIO, after the second data packet loss ratio is obtained, the through buffer size may be adjusted based on the second data packet loss ratio, and in some examples, when the buffer management module adjusts the through buffer size based on the second data packet loss ratio, the buffer management module is configured to: when the second data packet loss ratio is larger than a second preset threshold value, increasing the size of the through cache; and when the second data packet loss ratio is smaller than or equal to a second preset threshold value, reducing the through cache size.

Specifically, after the second data packet loss ratio is obtained, the second data packet loss ratio may be compared with a second preset threshold, and when the second data packet loss ratio is greater than the second preset threshold, this indicates that the second data packet loss ratio at this time is greater, and the use of the through buffer area is relatively tense, and at this time, the through buffer size is increased, and meanwhile, the calculation processing buffer is reduced. Correspondingly, when the second data packet loss ratio is smaller than or equal to the second preset threshold, the second data packet loss ratio is smaller, the usage of the through buffer memory area is looser, otherwise, the usage of the calculation processing buffer memory is more tense, and at the moment, the size of the through buffer memory is reduced, and meanwhile, the calculation processing buffer memory is increased.

In other examples, the through buffer size may be adjusted not only directly by the second preset threshold and the second data packet loss ratio, but also in other manners, where, when the buffer management module adjusts the through buffer size based on the second data packet loss ratio, the buffer management module is configured to: acquiring historical data packet loss rate; and determining the change trend of the data packet loss ratio based on the historical data packet loss ratio and the second data packet loss ratio, and if the change trend of the data packet loss ratio is an ascending trend, indicating that the use of the through cache region is stressed, at the moment, increasing the size of the through cache and simultaneously reducing the calculation processing cache. Correspondingly, if the variation trend of the data packet loss ratio is a decreasing trend, the usage of the through buffer area is relatively loose, and at this time, in order to further improve the quality and efficiency of data processing, the size of the through buffer can be reduced, and meanwhile, the calculation processing buffer can be increased.

In still other examples, not only the size of the through buffer may be adjusted by the trend of the packet loss ratio, but also the size of the through buffer may be adjusted in combination with the memory bandwidth information, where, when the buffer management module adjusts the size of the through buffer based on the second packet loss ratio, the buffer management module is configured to: acquiring memory bandwidth information; and adjusting the size of the through cache based on the second data packet loss ratio and the memory bandwidth information.

When the data plane function module is used for carrying out data processing operation on the data packet, the memory bandwidth information corresponding to the data plane function module can be obtained, the memory bandwidth information can be determined by the memory bit width and the memory frequency, and specifically, the product value of the memory bandwidth information and the memory frequency can be the memory bandwidth information. After the memory bandwidth information is obtained, the through-cache size may be adjusted based on the kernel bandwidth information and the second packet loss ratio, and in some examples, when the cache management module adjusts the through-cache size based on the second packet loss ratio and the memory bandwidth information, the cache management module is configured to: the pre-trained machine learning model or neural network model is obtained, the memory bandwidth information and the second data packet loss ratio are input into the machine learning model or the neural network model, the adjustment information output by the machine learning model or the neural network model is obtained, and then the size of the through cache can be adjusted based on the adjustment information.

In other examples, the adjustment of the size of the through buffer may be implemented not only by a machine learning model or a neural network model, but also by a preset bandwidth threshold and a second preset threshold, where, when the buffer management module adjusts the size of the through buffer based on the second packet loss rate and the memory bandwidth usage information, the buffer management module is configured to: when the second data packet loss ratio is larger than a second preset threshold value or the memory bandwidth information is larger than a preset bandwidth threshold value, increasing the size of the through cache; and when the second data packet loss ratio is smaller than or equal to a second preset threshold value or the memory bandwidth information is smaller than or equal to the preset bandwidth threshold value, reducing the size of the through cache.

Because the memory bandwidth information is related to the supportable user traffic, in general, when the memory bandwidth information is larger, the supportable data traffic is larger; when the memory bandwidth information is smaller, the data flow which can be supported is smaller; therefore, after the second data packet loss rate and the memory bandwidth information are obtained, the second data packet loss rate and a second preset threshold value can be analyzed and compared, the memory bandwidth information and the preset bandwidth threshold value are analyzed and compared, and when the second data packet loss rate is greater than the second preset threshold value, the data through cache is used more tensely; when the second data packet loss ratio is smaller than or equal to a second preset threshold value, the data through cache is loosely used at the moment; when the memory bandwidth information is larger than the preset bandwidth threshold, the supportable flow is larger, and when the memory bandwidth information is smaller than or equal to the preset bandwidth threshold, the supportable flow is smaller.

As can be seen from the above, when the second data packet loss ratio is greater than the second preset threshold, or the memory bandwidth information is greater than the preset bandwidth threshold, the usage of the data through buffer is relatively tense, so that in order to alleviate the above situation, the size of the through buffer can be increased, and the CPU buffer is reduced at the same time; when the second data packet loss ratio is smaller than or equal to a second preset threshold value or the memory bandwidth information is smaller than or equal to a preset bandwidth threshold value, the usage of the data through buffer memory at the moment is loose, the size of the through buffer memory can be reduced, and the CPU buffer memory is increased in order to improve the quality and efficiency of data processing, so that flexible adjustment operation on the size of the through buffer memory based on the second data packet loss ratio is effectively realized.

And the implementation mode is three:

the cache management module is used for: in the process of processing the data packets, acquiring a first data packet loss ratio corresponding to the last level of buffer memory and a second data packet loss ratio corresponding to the data through buffer memory; the through buffer size is adjusted based on the first packet loss ratio and the second packet loss ratio.

The method for obtaining the first data packet loss ratio and the second data packet loss ratio is similar to the method for obtaining the first data packet loss ratio and the second data packet loss ratio in the first implementation manner, and specific reference may be made to the above description, and details are not repeated here.

After the first and second data packet loss rates are obtained, the through-buffer size may be adjusted based on the first and second data packet loss rates. In some examples, when the cache management module adjusts the through cache size based on the first packet loss ratio and the second packet loss ratio, the cache management module is to perform: the method comprises the steps of obtaining a pre-trained machine learning model or neural network model, inputting a first data packet loss ratio and a second data packet loss ratio into the machine learning model or the neural network model, obtaining adjustment information output by the machine learning model or the neural network model, and adjusting the size of the direct cache based on the adjustment information.

In other examples, the adjustment of the size of the through buffer may be implemented not only by a machine learning model or a neural network model, but also by a first preset threshold and a second preset threshold, where, when the buffer management module adjusts the size of the through buffer based on the first packet loss rate and the second packet loss rate, the buffer management module is configured to perform: when the first data packet loss ratio is smaller than a first preset threshold value or the second data packet loss ratio is larger than a second preset threshold value, increasing the size of the through buffer; when the first data packet loss ratio is larger than a first preset threshold value or the second data packet loss ratio is smaller than a second preset threshold value, reducing the size of the through cache; and when the first data packet loss ratio is larger than a first preset threshold value and the second data packet loss ratio is larger than a second preset threshold value, or the first data packet loss ratio is smaller than the first preset threshold value and the second data packet loss ratio is smaller than the second preset threshold value, keeping the size of the through buffer unchanged.

Specifically, the first data packet loss ratio can represent the use condition of the calculation processing buffer, the second data packet loss ratio can represent the use condition of the data through buffer, and the calculation processing buffer and the data through buffer form a complete third-level buffer, so after the first data packet loss ratio and the second data packet loss ratio are obtained, the first data packet loss ratio can be analyzed and compared with a first preset threshold value, the second data packet loss ratio can be analyzed and compared with a second preset threshold value, and when the first data packet loss ratio is smaller than the first preset threshold value or the second data packet loss ratio is smaller than the second preset threshold value, the use of the data through buffer is tense, and the use of the calculation processing buffer is looser.

When the first data packet loss ratio is greater than a first preset threshold value or the second data packet loss ratio is less than a second preset threshold value, the calculation processing buffer memory is relatively tense in use and relatively loose in use, so that the size of the direct buffer memory can be reduced, and meanwhile, the calculation processing buffer memory is increased. When the first data packet loss ratio is greater than a first preset threshold value and the second data packet loss ratio is greater than a second preset threshold value, or the first data packet loss ratio is less than the first preset threshold value and the second data packet loss ratio is less than the second preset threshold value, the current data processing state is in a preset steady state, and the size of the through cache can be kept unchanged at the moment, so that flexible adjustment operation on the size of the through cache is effectively realized.

It should be noted that the decreasing amplitude or increasing amplitude of the through buffer size or the calculation processing buffer may be preconfigured, and in order to ensure stable reliability of data processing, when the through buffer size or the calculation processing buffer is adjusted, a corresponding limit value is configured, for example: when the size of the through cache is reduced, a lower limit value (for example, 1/10, 1/15, 1/20 and the like) for limiting the size of the through cache is configured, so that the size of the through cache can be adjusted anyway, and the size of the through cache is at least larger than or equal to the lower limit value; similarly, in increasing the through cache size, an upper limit (e.g., 4/10, 4/11, or 4/12, etc.) for defining the through cache size is configured, so that the through cache size can be guaranteed to be smaller than or equal to the upper limit regardless of how the through cache size is adjusted.

In this embodiment, in the process of processing a data packet by the data plane functional module, the buffer management module obtains a first data packet loss ratio corresponding to the last level buffer and/or a second data packet loss ratio corresponding to the data through buffer, and then adjusts the size of the through buffer based on the first data packet loss ratio and/or the second data packet loss ratio, thereby effectively implementing flexible adjustment operation on the size of the through buffer, and further improving the practicality of the system.

On the basis of any one of the foregoing embodiments, referring to fig. 2, the cache management module in this embodiment may further adjust the size of the through cache based on a data scene corresponding to the data packet, where in this case, the cache management module in this embodiment may further be configured to: acquiring a data scene corresponding to the data packet in the process of processing the data packet; and adjusting the size of the direct cache based on the data scene.

In the process of processing the data packet by using the data plane function module, the data packets may be in different data scenes, because the data packets with different lengths may correspond to the different data scenes, and the data packets with different lengths can have different effects on the size of the through buffer, so, in order to flexibly adjust the size of the through buffer, the data scenes corresponding to the data packets may be acquired, where the data scenes may include a preset big packet data scene, a preset small packet data scene, and so on, in some examples, the data scenes corresponding to the data packets may be determined according to the average length of the data packets, and at this time, when the buffer management module acquires the data scenes corresponding to the data packets, the buffer management module is configured to perform: acquiring average lengths of data packets corresponding to all the data packets in a preset time period; determining a data scene corresponding to the data packet based on the average length of the data packet, and particularly determining the application scene as a large-packet data scene when the average length of the data packet is greater than or equal to a preset length; and when the average length of the data packets is smaller than the preset length, determining the application scene as a small packet data scene.

Because different data scenes can have different effects on the size of the through cache, in order to ensure the quality and effect of data processing, after the data scenes corresponding to the data packets are acquired, the size of the through cache can be adjusted based on the data scenes, in some examples, mapping relations between different data scenes and the adjustment strategies of the size of the through cache are pre-configured, after the data scenes are acquired, a target adjustment strategy corresponding to the data scenes can be determined based on the mapping relations, and then the size of the through cache can be adjusted based on the target adjustment strategy.

In other examples, when the cache management module resizes the pass-through cache based on the data scenario, the cache management module is to perform: the average length value of the data packets in the data scene is larger than a preset threshold value, which means that the data packets to be processed are larger at the moment, the pressure of the data direct-connection buffer memory is easy to increase, and at the moment, in order to ensure the quality and effect of data processing, the direct-connection buffer memory is increased in size, so that the buffer memory in the calculation processing module is reduced; when the average length value of the data packets in the data scene is smaller than or equal to a preset threshold value, the data packets to be processed at the moment are smaller, the buffer pressure in the calculation processing module is easy to increase, and at the moment, in order to ensure the quality and effect of data processing, the size of the direct buffer is reduced, so that the buffer in the calculation processing module is increased; therefore, the technical scheme that the size of the direct-connection cache can be flexibly adjusted based on different data scenes is effectively realized.

In this embodiment, in the process of processing a data packet, the buffer management module obtains a data scene corresponding to the data packet, and then adjusts the size of the through buffer based on the data scene, specifically, different adjustment operations can be performed on the size of the through buffer according to different average length values of the data packet, so that flexible adjustment of the size of the through buffer based on different data scenes is effectively realized, the practicability of the system is further improved, and the popularization and application of the market are facilitated.

Referring to fig. 3, this embodiment provides a private network cache management system, where the private network cache management system can perform management operation on cache resources in a private network computing processing module in a process of performing processing operation on a data packet by a data plane function module in a private network, and specifically, the private network cache management system in this embodiment may include:

the private network data surface function module is operated on the private network calculation processing module and is used for acquiring the private network data packet to be processed and processing the private network data packet by utilizing the cache resource;

The private network cache management module is in communication connection with the private network data surface function module and the private network calculation processing module and is used for determining the data packet attribute corresponding to the private network data packet and the data receiving attribute corresponding to the private network data surface function module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

The specific cache management process, the cache management principle and the cache management effect of the private network cache management system in this embodiment are similar to those of the cache management system in the foregoing embodiment, and specific reference may be made to the foregoing description, and details are not repeated herein.

Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the case where there is no conflict between the embodiments, the following embodiments and features in the embodiments may be combined with each other. In addition, the sequence of steps in the method embodiments described below is only an example and is not strictly limited.

Referring to fig. 4 to fig. 5, this embodiment provides a cache management method, where an execution body of the cache management method may be a cache management device, where the cache management device may be applied to a 5G core network or a base station RAN, and when the cache management device is applied to the 5G core network, the cache management method for the 5G core network may be implemented; when the cache management device is applied to the RAN, a cache management method aiming at the RAN can be realized. At this time, the cache management method may be executed in a cloud, where a plurality of computing nodes (cloud servers) may be deployed in the cloud, and each computing node has processing resources such as computation and storage. At the cloud, a service may be provided by multiple computing nodes, although one computing node may provide one or more services. The cloud may provide the service by providing a service interface to the outside, and the user invokes the service interface to use the corresponding service. The service interface includes a software development kit (Software Development Kit, abbreviated as SDK), an application program interface (Application Programming Interface, abbreviated as API), and the like.

Aiming at the scheme provided by the embodiment of the invention, the cloud can be provided with the cache management service interface, and the user invokes the cache management interface through the user terminal UE so as to trigger a request for invoking the cache management interface to the cloud. The cloud determines the computing node responding to the request, and specific processing operation of cache management is executed by using processing resources in the computing node.

The system platform where the cache management device is located may be deployed with a base station RAN or a part of a core network, in some examples, the cache management device may be deployed on the same system platform as the RAN, so that management operations may be performed for caches in the RAN, and the cache management device may be communicatively connected to the core network; alternatively, the buffer management device may be disposed on the same platform as the core network, so that management operations may be performed on a buffer in the core network, and the buffer management device may perform management operations on a buffer in the RAN, where the buffer may include at least one of the following buffer resource types: cache resources of a core processor (Central Processing Unit, CPU for short), cache resources of a graphics processor (Graphic Processing Unit, GPU for short), cache resources of a General-purpose graphics processor (General-Purpose Graphics Processing Unit, GPGPU for short) and the like, and one skilled in the art can flexibly adjust and configure the cache resources according to specific application scenarios or application requirements.

The base station RAN may be communicatively connected to one or more user terminals UE, where the user terminals UE may be any computing device with a certain data transmission capability, and in a specific implementation, the user terminals UE may be mobile phones, personal computers PC, tablet computers, setting application programs, etc. Furthermore, the basic structure of the user terminal UE may include: at least one processor. The number of processors depends on the configuration and type of the user terminal UE. The user terminal UE may also include a Memory, which may be volatile, such as a random access Memory (Random Access Memory, abbreviated as RAM), or non-volatile, such as a Read-Only Memory (ROM), a flash Memory, or the like, or may include both types. The memory typically stores an Operating System (OS), one or more application programs, program data, and the like. In addition to the processing unit and the memory, the user terminal UE comprises some basic configuration, such as a network card chip, an IO bus, a display component, and some peripheral devices. Alternatively, some peripheral devices may include, for example, a keyboard, a mouse, a stylus, a printer, and the like. Other peripheral devices are well known in the art and are not described in detail herein.

The cache management apparatus refers to a device that can provide a cache management operation in a network virtual environment, and generally refers to an apparatus that performs information planning and cache management operations using a network. In a physical implementation, the cache management apparatus may be any device capable of providing a computing service, responding to a system call instruction, and performing a cache management operation based on the cache management instruction, for example: may be a cluster server, a conventional server, a cloud host, a virtual center, etc. The cache management device mainly comprises a processor, a hard disk, a memory, a system bus and the like, and is similar to a general computer architecture.

In the embodiment described above, the cache management device and the computing processing module may be disposed in the same system platform, for example: the cache management device and the core processor CPU can be deployed on the same server or personal computer, wherein the CPU can be operated with a preset module in a base station or a preset module in a core network.

Specifically, the cache management method may include:

step S501: and acquiring the data packet attribute of the data packet received by the data plane functional module and the data receiving attribute corresponding to the data plane functional module.

Step S502: and determining a cache resource for realizing data processing operation, wherein the cache resource is included in the calculation processing module, and the last level of cache in the cache resource comprises a data through cache, wherein the data surface function module runs on the calculation processing module.

Step S503: and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

The specific implementation process and implementation effect of each step are described in detail below:

The data plane function module may be a module running on the computing processing module for implementing a certain preset function, and the data plane function module in different application scenarios may have different implementation forms, for example: in the application scenario of the 5G core network, the data plane function module may be implemented as a UPF network element in the core network, where the cache management device may be located on the same platform or in the same device as the UPF network element; in the application scenario of the RAN, the data plane function module may be implemented as a DU unit in the RAN, where the buffer management device may be located on the same platform or in the same device with the DU unit; or in an application scenario of public cloud, the data plane function module may be implemented as a load balancer belonging to the public cloud, where the load balancer can implement load balancing operation, and at this time, the cache management device and the load balancer may be both deployed on the public cloud.

The calculation processing module executed by the data plane function module can be specifically implemented as at least one of the following: core processors (Central Processing Unit, CPU for short), graphics processors (Graphic Processing Unit, GPU for short), general-purpose graphics processors (General-Purpose Graphics Processing Unit, GPGPU for short), etc., those skilled in the art can flexibly adjust and configure the data plane function modules according to specific application scenarios or application requirements.

For the computing processing module, a cache resource for implementing a data processing operation may be included in the computing processing module, where the cache resource may be implemented as a multi-level cache, for example: the computing processing module may include a third level buffer, a fourth level buffer, or a fifth level buffer, for example, where the computing processing module includes the third level buffer, and the buffer resource included in the computing processing module may include a third level buffer LLC, as shown in fig. 6, where the LLC may include a data through buffer for applying the data through technology and a non-through buffer for applying the CPU, that is, the data through buffer and the non-through buffer form a completed LLC, that is, the data through buffer is a part of the LLC in the CPU. For the data through cache and the non-through cache, the size of the data through cache is fixed, and the size of the non-through cache is larger than that of the data through cache, for example, the LLC has 10 cache areas, the data through cache can occupy 1 area, and the non-through cache can occupy 9 areas; alternatively, the data pass-through cache may occupy 2 parts of the area, the non-pass-through cache may occupy 8 parts of the area, and so on. Because the LLC cache area is always fixed, if the LLC is improperly used, the access data of the CPU is easy to be leaked, and the network processing performance is greatly reduced.

In order to avoid the above-mentioned problems and to enable flexible adjustment and management operations to be performed on the cache, in the process of performing data processing by using the data plane function module, the data packet attribute of the data plane function module for receiving the data packet and the data receiving attribute corresponding to the data plane function module may be obtained, where the data packet attribute may include at least one of the following: the data surface functional module receives the average size of the data packet and the median size of the data packet; the data reception attribute corresponding to the data plane function module may include at least one of: an upper limit parameter for the number of data packets that the data plane function module can receive, a reception descriptor for identifying an upper limit for the number of data packets that the data plane function module can receive, and the like. The packet attributes and the data receiving attributes may be obtained synchronously or asynchronously. The acquiring the data packet attribute of the data packet received by the data plane function module may include: acquiring all data packets received by a data plane function module within a preset time period (for example, 1min, 5min or 30s and the like); average value processing is carried out on the sizes of all the data packets to obtain the average size of the received data packets, and the average size is determined as the data packet attribute; or determining the median size corresponding to all the data packets, and determining the obtained median size as the data packet attribute.

In addition, for the data reception attribute, since the data reception attribute can identify the upper limit of the number of data packets that the data plane function module can receive, the data reception attribute is often related to the network architecture corresponding to the data plane function module, in some examples, the data reception attribute may be configured in advance based on the network architecture and stored in the preset area, and at this time, acquiring the data reception attribute for identifying the upper limit of the number of data packets that the data plane function module can receive may include: and the data receiving attribute for identifying the data upper limit of the data packet received by the data surface functional module can be obtained by accessing the preset area.

The computing processing module may include a buffer resource for implementing a data processing operation, where the buffer resource may be a multi-level buffer, a last level buffer in the multi-level buffer may include a data through buffer, for the data through buffer, since the data through buffer is a part of the last level buffer (e.g., a third level buffer LLC), the data through buffer may be acquired based on the last level buffer, and the size of the data through buffer may be a through buffer size, and in some examples, acquiring a through buffer size corresponding to the data through buffer may include: determining preset duty ratio information for limiting the size of the data through cache, wherein the preset duty ratio information is smaller than 1 and larger than 0; determining the size of a direct cache based on preset duty ratio information and the size of a cache area; specifically, determining the through cache size based on the preset duty cycle information and the cache area size may include: and determining the product value of the preset duty ratio information and the size of the cache area as the direct cache size.

Step S302: and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

After the packet attributes, the data receipt attributes, and the data pass-through buffer are obtained, a buffer management operation may be performed based on the packet attributes, the data receipt attributes, and the data pass-through buffer, and in some examples, the buffer management performed based on the packet attributes, the data receipt attributes, and the data pass-through buffer may include: acquiring a machine learning model for realizing cache management operation; the data packet attribute, the data receiving attribute and the data direct-connection cache are input into the machine learning model, cache management information output by the machine learning model is obtained, and cache management operation is performed based on the cache management information, so that flexible adjustment and management operation on cache resources (such as a third-level cache or a last-level cache) are effectively realized.

In still other examples, in order to improve the stability and reliability of the use of the method, the method in this embodiment may further include a technical solution for performing isolation deployment and isolation management on different types of cache areas included in the last level of cache, where in this case, the method in this embodiment may further include: obtaining a last level of cache in the cache resource; determining a computational processing buffer for use by the computational processing module based on the last level buffer and the data pass-through buffer; and carrying out isolation management on the data direct-connection cache and the calculation processing cache.

Specifically, taking the core processor as a calculation processing module and taking the last level of cache in the cache resources as the third level of cache as an example, at this time, the calculation processing cache can be implemented as a CPU cache, after the calculation processing module CPU and the network architecture are determined, the third level of cache can be obtained, as shown in fig. 6, since the data through cache is often part of the third level of cache and the CPU cache is another part of the third level of cache, after the third level of cache and the data through cache are obtained, the CPU cache for the CPU to use can be determined based on the third level of cache and the data through cache, and after the data through cache and the CPU cache are obtained, the data through cache and the CPU cache can be isolated and managed, so that the occurrence of DMA leakage caused by improper use of the CPU cache can be reduced, and the quality and efficiency of the data processing performance are further ensured.

According to the cache management method provided by the embodiment, the data packet attribute of the data packet received by the data plane function module and the data receiving attribute corresponding to the data plane function module are obtained; determining a cache resource for realizing data processing operation, wherein the cache resource comprises a data through cache, and the last level of cache in the cache resource is used for enabling the data surface function module to run on the computing processing module; based on the data packet attribute, the data receiving attribute and the data direct-connection cache, the cache resource in the calculation processing module is flexibly adjusted and managed, so that the improper use of the cache resource is reduced, and the problem of network processing performance reduction caused by memory leakage is avoided, thereby ensuring the network processing performance, improving the practicability of the method and being beneficial to popularization and application of markets.

On the basis of the foregoing embodiment, referring to fig. 7, the present embodiment provides a technical solution for implementing cache management by adjusting a data receiving attribute, and specifically, cache management based on a data packet attribute, a data receiving attribute, and a data through cache may include:

step S701: based on the data packet attribute, the data receiving attribute and the data through cache, whether a cache use problem exists is detected.

In the process of processing the data packet by using the data plane function module, the use condition of the buffer memory can be embodied by the data packet attribute, the data receiving attribute and the data through buffer memory, so that after the data packet attribute, the data receiving attribute and the data through buffer memory are acquired, the data packet attribute, the data receiving attribute and the data through buffer memory can be analyzed and processed to detect whether the buffer memory use problem exists. In some examples, based on the packet attributes, the data reception attributes, and the data pass-through cache may include: the method comprises the steps of obtaining a pre-trained neural network model for detecting whether a cache use problem exists, inputting data packet attributes, data receiving attributes and data direct-connection caches into the neural network model, and obtaining detection results output by the neural network model, wherein the detection results can comprise detection results of the cache use problem or detection results of no cache use problem.

In other examples, not only can the neural network model detect whether there is a problem of using the buffer, but also the detection operation can be directly performed based on the data packet attribute, the data receiving attribute and the data through buffer, and at this time, based on the data packet attribute, the data receiving attribute and the data through buffer, the detection of whether there is a problem of using the buffer may include: determining a received data quantity parameter based on the data packet attribute and the data receiving attribute; based on the received data amount parameter and the data through cache, whether a cache use problem exists is detected.

In some examples, the data packet attributes include an average size of received data packets, and the data reception attributes include a reception descriptor for identifying an upper limit on a number of data packets that the data plane function module is capable of receiving; at this time, determining the received data amount parameter based on the packet attribute and the data reception attribute may include: obtaining a product value between the average size and the received descriptor; based on the product value, a received data amount parameter is determined.

After the received data amount parameter and the data through buffer are determined, the data through buffer can be analyzed and processed, so that the through buffer size of the data through buffer can be determined, then the data received amount parameter and the through buffer size can be analyzed and compared, and whether the buffer use problem exists or not can be detected based on the analysis and comparison result. Specifically, when the received data amount parameter is smaller than or equal to the size of the direct cache, it can be determined that no cache use problem exists; and when the received data quantity parameter is larger than the size of the direct-connection buffer, determining that the buffer use problem exists.

For example, the receive descriptor may be rxdescriptor, the average size may be packetsize, the through buffer size may be DDIOsize, then the rxdescriptor may be analyzed and compared with the packetsize, and when rxdescriptor is less than DDIOsize, or rxdescriptor is less than packetsize=ddiosize, the through buffer size at this time can support and satisfy the overall size of the data packet to be processed, so that it may be determined that there is no buffer usage problem currently; when rxdescriptor is greater than DDIOsize, the through buffer size cannot support or satisfy the overall size of the data packet to be processed, so that it can be determined that a buffer usage problem currently exists.

Step S702: if the cache use problem exists, determining the target data receiving attribute based on the data packet attribute and the data through cache.

When the detection result indicates that the cache use problem exists, in order to alleviate or avoid the problem of memory leakage, the obtained receiving descriptor for identifying the upper limit of the number of the data packets which can be received by the data plane function module is not suitable for the current application scene, so that the data packet attribute and the data direct cache can be analyzed and processed, and the target data receiving attribute can be determined.

In some examples, determining the target data reception attribute based on the packet attribute and the data pass-through cache may include: acquiring the ratio between the data direct-connection cache and the data packet attribute; and determining a target data receiving attribute based on the ratio, wherein the target data receiving attribute is a positive integer less than or equal to the ratio. For example, when the data packet attribute is an average size, the size of the data through buffer area is a through buffer size, and the receiving descriptor is an example of the data receiving attribute, determining the target receiving descriptor based on the average size and the through buffer size may include: acquiring the ratio of the size of the direct cache to the average size; a target receive descriptor is determined based on the ratio, the target receive descriptor being a positive integer less than or equal to the ratio.

For example, the receive descriptor may be an rxdescriptor, the average size may be a packetsize, the through buffer size may be a DDIOsize, and since the rxdescriptor is smaller than or equal to the packetsize, the memory leakage problem may be effectively alleviated, if the current rxdescriptor is not suitable for the current application scenario, the ratio between the through buffer size and the average size, that is, the DDIOsize/packetsize, may be obtained, and then the target receive descriptor may be determined based on the ratio, where the target receive descriptor is a positive integer smaller than or equal to the ratio, so that the accuracy and reliability of determining the target receive descriptor are effectively ensured.

It should be noted that the target data receiving attribute may be determined not only in the above manner, but also in other manners by those skilled in the art, for example: the machine learning model or the neural network model for determining the target data receiving attribute is trained in advance, and then the data through cache and the data packet attribute can be analyzed and processed by using the machine learning model or the neural network model, so that the target data receiving attribute and the like can be determined, so long as the accuracy and the reliability of determining the target data receiving attribute can be ensured.

In other examples, when the detection result indicates that the cache use problem does not exist, the data processing operation at this time can be performed stably, so that the current data receiving attribute can be kept unchanged.

Step S703: updating the data reception attribute to the target data reception attribute.

Because the obtained target data receiving attribute is suitable for the current application scene and is often different from the data receiving attribute, after the target data receiving attribute is obtained, the data receiving attribute can be updated to the target data receiving attribute, so that the product value of the target data receiving attribute and the data packet attribute of the received data packet can be kept smaller than or equal to the direct cache size of the direct cache, thereby realizing cache management operation, avoiding the condition that the memory of the access data of the calculation processing module is easy to leak due to improper use of the cache, and further ensuring the network processing performance.

In this embodiment, based on the packet attribute, the data receiving attribute, and the data direct-connection buffer, whether a buffer usage problem exists is detected; if the cache using problem exists, determining a target data receiving attribute based on the data packet attribute and the data direct cache; the data receiving attribute is updated to be the target data receiving attribute, so that the technical scheme for flexibly adjusting the data receiving attribute is effectively realized, and the adjusted data receiving attribute can effectively relieve the problem of memory leakage, thereby effectively improving the network processing performance and further improving the practicability of the method.

On the basis of any one of the foregoing embodiments, referring to fig. 8, in order to further ensure the quality and effect of cache management, the size of the through cache may be flexibly adjusted, where the method in this embodiment may further include:

step S801: in the process of processing the data packets, a first data packet loss ratio corresponding to the last level buffer and/or a second data packet loss ratio corresponding to the data through buffer are obtained.

Step S802: the through buffer size is adjusted based on the first packet loss ratio and/or the second packet loss ratio.

Taking the third level buffer as the last level buffer and the CPU as the calculation processing module as an example, the above embodiment may include three implementation manners for flexibly adjusting the size of the through buffer, which is specifically:

the implementation mode is as follows: step S801a: and in the process of processing the data packets, acquiring a first data packet loss ratio corresponding to the third-level buffer.

Wherein, in processing the data packet, a first data packet loss ratio corresponding to the third level buffer may be obtained, and in some examples, obtaining the first data packet loss ratio corresponding to the third level buffer may include: acquiring the total number of data access operations in a preset time period; counting the times of not matching the related data (namely, the occurrence of a miss condition) through the third-level cache; and determining the ratio of the number of times of not matching the related data to the total number of times as a first data packet loss ratio.

Step S802a: the through buffer size is adjusted based on the first packet loss ratio.

The first data packet loss ratio can represent the use condition of the CPU buffer memory for the CPU in the LLC, and the CPU buffer memory and the direct buffer memory form a complete LLC, so that the first data packet loss ratio can also represent the use condition of the direct buffer memory. Thus, after the first packet loss ratio is obtained, the through-buffer size may be adjusted based on the first packet loss ratio, which may include, in some examples: when the first data packet loss ratio is larger than a first preset threshold value, reducing the size of the through cache; and when the first data packet loss ratio is smaller than or equal to a first preset threshold value, increasing the size of the through cache.

Specifically, after the first data packet loss ratio is obtained, the first data packet loss ratio may be compared with a first preset threshold, and when the first data packet loss ratio is greater than the first preset threshold, this indicates that the first data packet loss ratio at this time is greater, and the use of the CPU cache is relatively tense, and at this time, the size of the through cache needs to be reduced, so that the CPU cache is increased. Correspondingly, when the first data packet loss ratio is smaller than or equal to a first preset threshold value, the first data packet loss ratio is smaller, the CPU cache is more loosely used, otherwise, the data through cache is more tense, and at the moment, the size of the through cache needs to be increased, and meanwhile, the CPU cache is reduced.

In other examples, not only the through buffer size may be directly adjusted by the first preset threshold and the first packet loss ratio, but also the through buffer size may be adjusted in other manners, where adjusting the through buffer size based on the first packet loss ratio may include: acquiring historical data packet loss rate; and determining the change trend of the data packet loss ratio based on the historical data packet loss ratio and the first data packet loss ratio, and if the change trend of the data packet loss ratio is an ascending trend, indicating that the use of the CPU cache is strained, at the moment, reducing the size of the through cache and simultaneously increasing the CPU cache. Correspondingly, if the variation trend of the data packet loss ratio is a decreasing trend, the CPU cache is loosely used, and at this time, in order to further improve the quality and efficiency of data processing, the size of the through cache may be increased, that is, the CPU cache may be decreased, so that flexible adjustment operation on the size of the through cache based on the first data packet loss ratio is effectively realized.

The implementation mode II is as follows: step S801b: and in the process of processing the data packets, acquiring a second data packet loss ratio corresponding to the data through cache.

Wherein during processing of the data packets, a second data packet loss ratio corresponding to the data pass-through buffer may be obtained, and in some examples, obtaining the second data packet loss ratio corresponding to the data pass-through buffer may include: acquiring the total number of data access operations in a preset time period; counting the times of the data pass through cache without matching the related data (namely, the miss condition occurs); and determining the ratio of the times of not matching the related data to the total times as a second data packet loss ratio.

Step S802b: the through cache size is adjusted based on the second packet loss ratio.

Since the second data packet loss ratio may represent a usage of the data pass-through buffer DDIO, after the second data packet loss ratio is obtained, the pass-through buffer size may be adjusted based on the second data packet loss ratio, and in some examples, adjusting the pass-through buffer size based on the second data packet loss ratio may include: when the second data packet loss ratio is larger than a second preset threshold value, increasing the size of the through cache; and when the second data packet loss ratio is smaller than or equal to a second preset threshold value, reducing the through cache size.

Specifically, after the second data packet loss rate is obtained, the second data packet loss rate may be compared with a second preset threshold, and when the second data packet loss rate is greater than the second preset threshold, this indicates that the second data packet loss rate at this time is greater, and the usage of the through buffer area is relatively tense, and at this time, the through buffer size is increased, and at the same time, the CPU buffer is reduced. Correspondingly, when the second data packet loss ratio is smaller than or equal to the second preset threshold value, the second data packet loss ratio is smaller, the usage of the through cache area is looser, otherwise, the usage of the CPU cache is more tense, and at the moment, the through cache size is reduced, and meanwhile, the CPU cache is increased.

In other examples, not only the through-buffer size may be directly adjusted by the second preset threshold and the second packet loss ratio, but also the through-buffer size may be adjusted in other manners, where adjusting the through-buffer size based on the second packet loss ratio may include: acquiring historical data packet loss rate; and determining the change trend of the data packet loss rate based on the historical data packet loss rate and the second data packet loss rate, and if the change trend of the data packet loss rate is an ascending trend, indicating that the use of the through cache region is stressed, at the moment, increasing the size of the through cache and simultaneously enabling the CPU cache to be reduced. Correspondingly, if the variation trend of the data packet loss ratio is a decreasing trend, the usage of the through buffer area is relatively loose, and at this time, in order to further improve the quality and efficiency of data processing, the size of the through buffer can be reduced, and meanwhile, the CPU buffer is increased.

In still other examples, not only the through-buffer size may be adjusted by a trend of the packet loss ratio, but also the through-buffer size may be adjusted in combination with the memory bandwidth information, where adjusting the through-buffer size based on the second packet loss ratio may include: acquiring memory bandwidth information; and adjusting the size of the through cache based on the second data packet loss ratio and the memory bandwidth information.

When the preset module is used for performing data processing operation on the data packet, the memory bandwidth information corresponding to the preset module can be obtained, the memory bandwidth information can be determined through the memory bit width and the memory frequency, and specifically, the product value of the memory bandwidth information and the memory frequency can be the memory bandwidth information. After the memory bandwidth information is obtained, the through-buffer size may be adjusted based on the core bandwidth information and the second packet loss ratio, and in some examples, adjusting the through-buffer size based on the second packet loss ratio and the memory bandwidth information may include: the pre-trained machine learning model or neural network model is obtained, the memory bandwidth information and the second data packet loss ratio are input into the machine learning model or the neural network model, the adjustment information output by the machine learning model or the neural network model is obtained, and then the size of the through cache can be adjusted based on the adjustment information.

In other examples, the adjusting the size of the through buffer may be implemented not only by a machine learning model or a neural network model, but also by a preset bandwidth threshold and a second preset threshold, where the adjusting the size of the through buffer based on the second packet loss ratio and the memory bandwidth usage information may include: when the second data packet loss ratio is larger than a second preset threshold value or the memory bandwidth information is larger than a preset bandwidth threshold value, increasing the size of the through cache; and when the second data packet loss ratio is smaller than or equal to a second preset threshold value or the memory bandwidth information is smaller than or equal to the preset bandwidth threshold value, reducing the size of the through cache.

And the implementation mode is three: step S801c: in the process of processing the data packets, a first data packet loss ratio corresponding to the third-stage buffer memory and a second data packet loss ratio corresponding to the data through buffer memory are obtained.

The method for obtaining the first data packet loss ratio and the second data packet loss ratio is similar to the method for obtaining the first data packet loss ratio and the second data packet loss ratio in steps S801a and S801b, and the description thereof will be omitted herein.

Step S802c: the through buffer size is adjusted based on the first packet loss ratio and the second packet loss ratio.

After the first and second data packet loss rates are obtained, the through-buffer size may be adjusted based on the first and second data packet loss rates. In some examples, adjusting the pass-through buffer size based on the first packet loss ratio and the second packet loss ratio may include: the method comprises the steps of obtaining a pre-trained machine learning model or neural network model, inputting a first data packet loss ratio and a second data packet loss ratio into the machine learning model or the neural network model, obtaining adjustment information output by the machine learning model or the neural network model, and adjusting the size of the direct cache based on the adjustment information.

In other examples, the adjusting the size of the through buffer may be implemented not only by a machine learning model or a neural network model, but also by a first preset threshold and a second preset threshold, where the adjusting the size of the through buffer based on the first packet loss ratio and the second packet loss ratio may include: when the first data packet loss ratio is smaller than a first preset threshold value or the second data packet loss ratio is larger than a second preset threshold value, increasing the size of the through buffer; when the first data packet loss ratio is larger than a first preset threshold value or the second data packet loss ratio is smaller than a second preset threshold value, reducing the size of the through cache; and when the first data packet loss ratio is larger than a first preset threshold value and the second data packet loss ratio is larger than a second preset threshold value, or the first data packet loss ratio is smaller than the first preset threshold value and the second data packet loss ratio is smaller than the second preset threshold value, keeping the size of the through buffer unchanged.

Specifically, the first data packet loss ratio can represent the use condition of the CPU cache, the second data packet loss ratio can represent the use condition of the data through cache, and the CPU cache and the data through cache form a complete third-level cache, so after the first data packet loss ratio and the second data packet loss ratio are obtained, the first data packet loss ratio can be compared with a first preset threshold value in an analysis manner, the second data packet loss ratio is compared with a second preset threshold value in an analysis manner, and when the first data packet loss ratio is smaller than the first preset threshold value or the second data packet loss ratio is smaller than the second preset threshold value, the use of the data through cache is relatively tension, and the use of the CPU cache is relatively loose.

When the first data packet loss ratio is larger than a first preset threshold value or the second data packet loss ratio is smaller than a second preset threshold value, the CPU cache is relatively tense in use and relatively loose in use, and the size of the direct cache can be reduced, and meanwhile, the CPU cache is increased. When the first data packet loss ratio is greater than a first preset threshold value and the second data packet loss ratio is greater than a second preset threshold value, or the first data packet loss ratio is less than the first preset threshold value and the second data packet loss ratio is less than the second preset threshold value, the current data processing state is in a preset steady state, and the size of the through cache can be kept unchanged at the moment, so that flexible adjustment operation on the size of the through cache is effectively realized.

It should be noted that the decrease or increase of the size of the through buffer or the CPU buffer may be preconfigured, and in order to ensure stable reliability of data processing, when the size of the through buffer or the CPU buffer is adjusted, a corresponding limit value is configured, for example: when the size of the through cache is reduced, a lower limit value (for example, 1/10, 1/15, 1/20 and the like) for limiting the size of the through cache is configured, so that the size of the through cache can be adjusted anyway, and the size of the through cache is at least larger than or equal to the lower limit value; similarly, in increasing the through cache size, an upper limit (e.g., 4/10, 4/11, or 4/12, etc.) for defining the through cache size is configured, so that the through cache size can be guaranteed to be smaller than or equal to the upper limit regardless of how the through cache size is adjusted.

In this embodiment, in the process of processing a data packet, a first data packet loss ratio corresponding to the third-level buffer and/or a second data packet loss ratio corresponding to the data through buffer are obtained, and then the size of the through buffer is adjusted based on the first data packet loss ratio and/or the second data packet loss ratio, so that flexible adjustment operation on the size of the through buffer is effectively realized, and the practicability of the method is further improved.

On the basis of any one of the foregoing embodiments, referring to fig. 9, the method in this embodiment may further adjust the size of the through buffer based on the data scene corresponding to the data packet, where the method in this embodiment may further include:

step S901: and in the process of processing the data packet, acquiring a data scene corresponding to the data packet.

In the process of processing the data packet by using the data plane function module, the data packet may be in different application scenarios, and since the data packets with different lengths may correspond to the different application scenarios, and the data packets with different lengths may have different effects on the size of the through buffer, in order to flexibly adjust the size of the through buffer, the data scenario corresponding to the data packet may be acquired, where the application scenario may include a preset big packet data scenario, a preset small packet data scenario, and so on, in some examples, the data scenario corresponding to the data packet may be determined according to the average length of the data packet, and at this time, acquiring the data scenario corresponding to the data packet may include: acquiring average lengths of data packets corresponding to all the data packets in a preset time period; determining a data scene corresponding to the data packet based on the average length of the data packet, and particularly, determining the data scene as a large-packet data scene when the average length of the data packet is greater than or equal to a preset length; and when the average length of the data packets is smaller than the preset length, determining the application scene as a small packet data scene.

Step S902: and adjusting the size of the direct cache based on the data scene.

In other examples, resizing the pass-through cache based on the data scene may include: the average length value of the data packets in the data scene is larger than a preset threshold value, which means that the data packets to be processed are larger at the moment, the pressure of the data direct-connection buffer memory is easy to increase, and at the moment, in order to ensure the quality and effect of data processing, the direct-connection buffer memory is increased in size, so that the CPU buffer memory is reduced; when the average length value of the data packets in the data scene is smaller than or equal to a preset threshold value, the data packets to be processed at the moment are smaller, the pressure of the CPU cache is easy to increase, and at the moment, in order to ensure the quality and effect of data processing, the size of the through cache is reduced, so that the CPU cache is increased; therefore, the technical scheme that the size of the direct-connection cache can be flexibly adjusted based on different data scenes is effectively realized.

In the embodiment, in the process of processing the data packet, the data scene corresponding to the data packet is acquired, and then the size of the direct-connection buffer memory is adjusted based on the data scene, specifically, different adjustment operations can be performed on the size of the direct-connection buffer memory according to different average length values of the data packet, so that the flexible adjustment of the size of the direct-connection buffer memory based on different data scenes is effectively realized, the practicability of the method is further improved, and the popularization and application of the market are facilitated.

In specific application, taking a UPF network element in a 5G core network as a preset module as an example, the application embodiment provides a CPU cache management method for an application scene of the 5G core network, which can manage and schedule the use of CPU cache resources in an operation environment of the 5G core network, solve the problems of memory leakage and performance and competition of cache resources in the core network caused by improper use of caches in the 5G core network, further ensure that the core network is not interfered by other applications, and promote performance indexes such as throughput, time delay and the like of the core network. The CPU cache management method is mainly oriented to the performance guarantee and promotion of the 5G core network, a CPU cache management and scheduling platform is provided for the enhancement of the 5G core network, namely, an execution main body of the CPU cache management method can be the CPU cache management platform, the CPU cache management platform and UPF network elements can be located in the same system platform, and specifically, in order to solve the problems and challenges, the application embodiment provides two sub-methods:

(1) By analyzing a cache utilization mechanism in the core network, recommendation of cache related parameter indexes (receiving descriptors rx descriptors) is given, and proper cache parameter selection greatly improves the throughput performance of the core network;

(2) And a buffer resource management and allocation mechanism of the core network effectively manages buffer resources used by state information such as data packets, flow tables and the like, maximizes the utilization of the buffer resources, effectively relieves the competition condition of the buffer resources and improves the throughput performance of the core network.

The above sub-method (1) can determine whether the selection of the current cache related parameters is scientific, specifically can determine whether the currently selected reception descriptor rx descriptor for identifying the number of data packets that the UPF network element can receive from the physical network card device is reasonable, and specifically may include the following steps:

step 11: acquiring a current receiving descriptor rx descriptor;

the receiving descriptor is preconfigured by the developer of the core network, so the current receiving descriptor can be obtained through communication with the developer of the core network.

Step 12: and acquiring the average size packet size of the data packet received by the UPF and the direct buffer size DDIO size corresponding to the data direct buffer.

Step 13: and judging the size relation between the rx descriptor size and the DDIO size.

Step 14: at rx descriptor sizeWhen DDIO size is adopted, the problem of DMA leakage can be effectively relieved, so that the current rx descriptor can be determined to be moderate for the current application scene; when rx descriptor size > DDIO size, DMA leakage is easy to occur, performance is reduced, and therefore selection of the rx descriptor can be determined to be relatively unscientific.

Step 15: when the selection of the rx descriptor is determined to be less scientific, a new receiving descriptor rx descriptor1 can be determined through DDIO size and packet size, and then the rx descriptor is replaced by the rx descriptor1, wherein the rx descriptor1 can be a maximum integer value or any integer value which is less than or equal to DDIO size/packet size.

While executing the sub-method (1), the sub-method (2) may be executed, so that the DDIO size may be dynamically adjusted according to indexes such as a second data packet loss ratio DDIO miss and a memory bandwidth corresponding to the data through cache, and the rx descriptor and the average size of the data packet may be matched through the dynamically adjusted DDIO size, so as to dynamically solve the problem of DMA leakage, and specifically, referring to fig. 10, the CPU cache management platform may include a cache index obtaining module and a cache index management and control module, where:

The buffer index obtaining module is configured to collect or obtain multiple indexes of the 5G core network during operation, as management and control input, where the multiple indexes may include memory bandwidth information (memory bandwidth usage situation), a first data packet loss ratio LLC miss corresponding to the third level buffer, and a second data packet loss ratio DDIO miss corresponding to the data through buffer, where the memory bandwidth information may identify how much information is interacted between the LLC and the main memory, and may indicate a DMA leakage situation to a certain extent.

Specifically, the memory bandwidth information may be determined based on the network operation state and the data processing state, and the LLC miss and DDIO miss may be obtained by detecting through a preset detection tool, for example: LLC miss can be obtained through detection by a preset system performance analysis tool perf, wherein perf is a performance analysis tool capable of performing hot spot search of a function level and an instruction level and can be used for analyzing the CPU occupancy rate of a hot spot function in a program so as to position a performance bottleneck; DDIO mass can be detected by a preset performance detector (performance countermonitor, PCM for short).

The cache index management and control module is used for detecting the core network operation environment according to the obtained indexes so as to detect whether the cache resource use problem exists, whether the internal cache competition exists or not and the like. In addition, the cache index management and control module makes a decision according to the detection information, and then uses a cache allocation technology (Cache Allocation Technology, abbreviated as CAT) to manage the use of the cache resources, specifically, a specific process of detecting and managing the cache resources based on a plurality of indexes may include the following steps:

step 21: comparing LLC miss with a first preset threshold, comparing DDIO miss with a second preset threshold, and comparing memory bandwidth information with a preset bandwidth threshold;

step 22: when LLC miss is smaller than or equal to a first preset threshold value, or DDIO miss is larger than a second preset threshold value, or the memory bandwidth information is larger than a preset bandwidth threshold value, increasing the size of the direct cache;

step 23: when LLC miss is larger than a first preset threshold value, or DDIO miss is smaller than or equal to a second preset threshold value, or the memory bandwidth information is smaller than or equal to a preset bandwidth threshold value, reducing the size of the direct cache;

step 24: and when the first data packet loss ratio is larger than a first preset threshold value and the second data packet loss ratio is larger than a second preset threshold value, or the first data packet loss ratio is smaller than the first preset threshold value and the second data packet loss ratio is smaller than the second preset threshold value, keeping the size of the through buffer unchanged.

It should be noted that, in some examples, a person skilled in the art may not only adjust the cache resources during the operation of the core network through LLC miss, DDIO miss and memory bandwidth information, but also make a management allocation decision of the cache resources according to different scenarios, in a preset packet application scenario, since DDIO has fewer available caches, for example: DDIO may be 10% of LLC, and at this time, the number of DDIO accommodating data packets is small, which may cause significant degradation in throughput, so that in order to avoid the above situation, the default duty ratio of DDIO with respect to LLC may be increased, for example: the DDIO can be adjusted to 20% of LLC, so that the pressure of the DDIO can be effectively relieved, and the overall performance of data processing is improved; correspondingly, in the preset packet application scenario, because the available buffer memory of DDIO is larger, for example: DDIO may be 40% of LLC, and since most of the cache area of DDIO is not applied, the utilization of the cache area may be caused, and in order to avoid the above situation, the default duty ratio of DDIO with respect to LLC may be reduced, for example: the DDIO can be adjusted to 10% or 20% of LLC, so that the utilization rate of the cache area can be effectively improved.

In addition, for the LLC, since the LLC may be a third level cache, the LLC may be divided into multiple cache areas by default, DDIO may be at least one of the multiple cache areas, and other cache areas are used for the CPU to apply, that is, DDIO and CPU cache form a complete LLC, for example: when LLC is divided into 10 cache areas, DDIO can be 1 cache area in the LLC, and CPU cache can be 9 other cache areas; or when the LLC is divided into 11 cache areas, the DDIO can be 1 cache area, the CPU cache can be another 10 cache areas, and in order to improve the quality and efficiency of data processing, the isolation management operation can be performed on the CPU cache and the DDIO.

According to the technical scheme provided by the application embodiment, through analysis of the cache use mechanism in the core network, recommendation of cache related parameter indexes can be given, and the problem of DMA leakage can be effectively solved through proper cache parameter selection, so that the throughput performance of the core network is greatly improved; in addition, by managing the indexes of occupying the cache such as the data packet and the state information in the core network, the cache resources used by the state information such as the data packet and the flow table are effectively managed, and the maximization of the utilization of the cache resources is effectively realized, so that the competition condition of the cache resources can be relieved, the throughput performance of the core network can be improved, the practicability of the technical scheme is further improved, and the popularization and the application of the market are facilitated.

Referring to fig. 11-12, this embodiment provides a cache management method, which may be applied to a cache management device, where the cache management device is deployed on a public cloud, and a load balancer for implementing load balancing operation is deployed on the public cloud, and the load balancer runs on a core processor CPU; at this time, the method in the present embodiment may include:

step S1101: acquiring a data packet attribute of a data packet received by a load balancer and a data receiving attribute corresponding to the load balancer;

Step S1102: determining a cache resource for realizing data processing operation, wherein the cache resource comprises a data through cache, and a load balancer runs on the computing processor;

step S1103: and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

The specific implementation manner and implementation effect of step S1101 to step S1103 in this embodiment are similar to those of step S501 to step S503 in the above embodiment, and specific reference may be made to the above description, and details are not repeated here.

It should be noted that the method in this embodiment may further include the method in the embodiment shown in fig. 5 to 10, and reference is made to the related description of the embodiment shown in fig. 5 to 10 for a part of this embodiment that is not described in detail. The implementation process and the technical effect of this technical solution are described in the embodiments shown in fig. 5 to 10, and are not described herein.

Referring to fig. 13, the present embodiment provides a vehicle control method applied to a vehicle control apparatus disposed on the same system platform as a cache management apparatus, the vehicle control method including:

Step S1301: the method comprises the steps of obtaining a cache adjustment instruction sent by a cache management device, wherein the cache adjustment instruction is determined through a data packet attribute, a data receiving attribute and a data direct cache, the data packet attribute is used for identifying the attribute of a data packet which can be received by a vehicle control device, the data receiving attribute is used for identifying the upper limit of the number of the data packet which can be received by the vehicle control device, and the data direct cache is a part of the last-stage cache in a calculation processing module in the vehicle control device;

the specific implementation manner and implementation effect of the step S1301 in this embodiment are similar to those of the step S501 to the step S503 in the embodiment, and reference may be made to the above description for details, which are not repeated here.

Step S1302: and carrying out cache management on a calculation processing module (such as a CPU module) in the vehicle control device based on the cache adjustment instruction so as to ensure stable control on the vehicle to be controlled.

After the cache adjustment instruction is acquired, the cache management operation can be performed on the calculation processing module in the vehicle control device based on the cache adjustment instruction, so that the vehicle to be controlled can be stably controlled and operated through the vehicle control device, and the practicability of the method is ensured.

Specifically, in the running process of the vehicle to be controlled (unmanned vehicle or manned vehicle), the vehicle to be controlled can be controlled by the vehicle control device, in order to realize accurate and effective control of the vehicle to be controlled, the vehicle control device needs to perform stable data processing operation, in order to ensure the stable reliability of the operation of the vehicle control device, the cache resources in the vehicle control device can be flexibly adjusted according to different application scenes, and thus, when the vehicle to be controlled is controlled based on the vehicle control device, the safety and the reliability of the control of the vehicle to be controlled can be ensured. Specifically, the vehicle control device may generate control information corresponding to the vehicle to be controlled, where the control information may include: vehicle speed information, vehicle driving path information, vehicle parking space information, and the like to perform stable and efficient control operations of the vehicle to be controlled based on the control information, for example, a lane on which the vehicle to be controlled is traveling may be controlled based on the control information of the driving path in the control information, that is, the vehicle to be controlled may be controlled to be switched from lane 1 to lane 2 based on the control information.

In some examples, in order to improve stability and reliability of controlling the vehicle, the vehicle to be controlled may be provided with a sensor, and the sensor may rapidly acquire the operation state data corresponding to the vehicle to be controlled, where the operation state data corresponding to the vehicle to be controlled may include at least one of the following: the method comprises the steps of current speed, running direction and environment information of a vehicle, wherein the environment information comprises distribution positions of surrounding objects, speed of the vehicle in front of the vehicle and road speed limit of a road on which the vehicle is located. In some examples, the sensors may include an image acquisition sensor, a radar sensor, and a global positioning system GPS, and in particular, the operational status data corresponding to the vehicle to be controlled is determined by the image acquisition sensor, the radar sensor, and the global positioning system GPS.

It is to be noted that, as for the vehicle control device, the vehicle control device may be provided on the vehicle, or the vehicle control device may be provided independently of the vehicle, in which case the vehicle control device may be communicatively connected to the vehicle CPU.

In addition, the vehicle control device may be adjusted according to different vehicles, that is, the algorithm modules included in the vehicle control device may be different according to different vehicle types, and at this time, the vehicle control device may implement not only the control operation of the automatic driving of the vehicle but also other operations. For example, different vehicle control devices may be involved for logistics vehicles, public service vehicles, medical service vehicles, terminal service vehicles. The algorithm modules included in the vehicle control apparatus are respectively illustrated below for these four autonomous vehicles:

wherein, logistics vehicles refer to vehicles used in logistics scenes, such as: can be a logistics vehicle with an automatic sorting function, a logistics vehicle with a refrigerating and heat-preserving function and a logistics vehicle with a measuring function. These logistics vehicles may involve different algorithm modules.

For example, for a logistics vehicle, an automated sorting device may be provided which can automatically pick up and transport, sort and store goods after the logistics vehicle arrives at the destination. This involves an algorithm module for sorting of goods, which mainly implements logic control of goods taking out, handling, sorting and storing.

For another example, for a cold chain logistics scene, the logistics vehicle can be further provided with a refrigeration and heat preservation device, and the refrigeration and heat preservation device can realize refrigeration or heat preservation of transported fruits, vegetables, aquatic products, frozen foods and other perishable foods, so that the fruits, vegetables, aquatic products, frozen foods and other perishable foods are in a proper temperature environment, and the problem of long-distance transportation of perishable foods is solved. The algorithm module is mainly used for dynamically and adaptively calculating proper temperature of cold food or heat preservation according to information such as food (or article) properties, perishability, transportation time, current seasons, weather and the like, and automatically adjusting the cold food or heat preservation device according to the proper temperature, so that transportation personnel do not need to manually adjust the temperature when different foods or articles are transported by a vehicle, the transportation personnel are liberated from complicated temperature regulation and control, and the efficiency of cold food or heat preservation transportation is improved.

For example, in most logistics scenes, the charge is carried out according to the volume and/or weight of the packages, the number of the logistics packages is very large, and the volume and/or weight of the packages are simply measured by an express delivery person, so that the efficiency is very low, and the labor cost is high. Therefore, in some logistics vehicles, a measuring device is additionally arranged, so that the volume and/or the weight of the logistics package can be automatically measured, and the cost of the logistics package can be calculated. This involves an algorithm module for logistic parcel measurement which is primarily used to identify the type of logistic parcel, determine the way in which the logistic parcel is measured, such as whether a volumetric measurement or a weight measurement is made or a combination of volumetric and weight measurements are made simultaneously, and can perform volumetric and/or weight measurements based on the determined way of measurement, and perform cost calculations based on the measurement results.

The public service vehicle is a vehicle that provides a certain public service, for example: can be a fire truck, a deicing vehicle, a watering vehicle, a snow shovel, a garbage disposal vehicle, a traffic guidance vehicle and the like. These public service vehicles may involve different algorithm modules.

For example, for an automatically driven fire engine, the main task is to perform a reasonable fire extinguishing task for a fire scene, which involves an algorithm module for the fire extinguishing task, and the algorithm module at least needs to implement logic of fire condition identification, fire extinguishing scheme planning, automatic control of a fire extinguishing device and the like.

For another example, for deicing vehicles, the main task is to remove ice and snow on the road surface, which involves an algorithm module for deicing that at least needs to implement logic for identifying ice and snow conditions on the road surface, making deicing schemes based on the ice and snow conditions, such as which road segments need to be defrosted, which road segments need not be defrosted, whether salt spraying mode, salt spraying gram number, etc. are used, and automatic control of the deicing device in case of determining the deicing scheme.

The medical service vehicle is an automatic driving vehicle capable of providing one or more medical services, and the vehicle can provide medical services such as disinfection, temperature measurement, medicine preparation, isolation and the like, and the medical service vehicle relates to algorithm modules for providing various self-service medical services, wherein the algorithm modules mainly realize the identification of disinfection requirements and the control of disinfection devices so as to enable the disinfection devices to disinfect patients or identify the positions of the patients, control the temperature measurement devices to automatically measure the temperature of the patients at the positions of the forehead and the like of the patients, or realize the judgment of symptoms, give medicine according to the judgment result and need to realize the identification of medicines/medicine containers, control the medicine taking mechanical arm so as to enable the medicine taking mechanical arm to take medicines for the patients according to the medicine prescription, and the like.

The terminal service vehicle refers to a self-service type automatic driving vehicle capable of replacing some terminal equipment to provide certain convenience services for users, for example, the vehicle can provide printing, attendance checking, scanning, unlocking, payment, retail and other services for the users.

For example, in some application scenarios, users often need to go to a particular location to print or scan a document, which is time consuming and laborious. Therefore, there is a terminal service vehicle capable of providing a printing/scanning service for a user, the service vehicles can be interconnected with a user terminal device, the user sends a printing command through the terminal device, the service vehicle responds to the printing command, automatically prints a document required by the user and can automatically send the printed document to a user position, the user does not need to go to a printer for queuing, and the printing efficiency can be greatly improved. Or, the user can respond to the scanning instruction sent by the terminal equipment and move to the user position, and the user can finish scanning on the scanning tool of the service vehicle for placing the document to be scanned, so that queuing at a printer/scanner is not needed, and time and labor are saved. This involves an algorithm module providing print/scan services that at least needs to identify interconnections with the user terminal device, responses to print/scan instructions, positioning of user location, travel control, etc.

For another example, as new retail scenarios develop, more and more electronic commerce uses self-service vending machines to sell goods to various office buildings and public areas, but the self-service vending machines are placed in fixed positions and are not movable, and users need to go to the self-service vending machines before they can purchase the required goods, so that convenience is still poor. The self-service driving vehicles capable of providing retail services are arranged, the service vehicles can bear goods to automatically move, corresponding self-service shopping APP or shopping portals can be provided, a user can place an order to the self-service driving vehicles providing retail services through the APP or shopping portals by means of terminals such as mobile phones, the order comprises names, quantity and user positions of goods to be purchased, after receiving an order placing request, the vehicles can determine whether the current remaining goods have the goods purchased by the user and whether the quantity is enough, and under the condition that the goods purchased by the user are determined to be enough, the goods can be carried to the user positions automatically, and the goods are provided for the user, so that the convenience of shopping of the user is further improved, the user time is saved, and the user can use the time for more important things. This involves the algorithm modules providing retail services that implement mainly logic for responding to user order requests, order processing, merchandise information maintenance, user location positioning, payment management, etc.

Referring to fig. 14, this embodiment provides a control method of a virtual reality device, where the control method of the virtual reality device may be applied to a control apparatus of the virtual reality device, and the control apparatus of the virtual reality device and a cache management apparatus are disposed on the same system platform, and the control method of the virtual reality device may include:

step S1401: the method comprises the steps of obtaining a cache adjustment instruction sent by a cache management device, wherein the cache adjustment instruction is determined through a data packet attribute, a data receiving attribute and a data direct cache, the data packet attribute is used for identifying the attribute of a data packet which can be received by virtual reality equipment, the data receiving attribute is used for identifying the upper limit of the number of the data packet which can be received by the virtual reality equipment, and the data direct cache is a part of the last-stage cache in a calculation processing module in the virtual reality equipment;

Step S1402: and carrying out cache management on a calculation processing module in the virtual reality equipment based on the cache adjustment instruction so as to ensure stable control on the virtual reality equipment.

Referring to fig. 15, the present embodiment provides a cache management apparatus for executing the cache management method shown in fig. 5, which may specifically include:

a first obtaining module 11, configured to obtain a packet attribute of a packet received by the data plane function module and a data receiving attribute corresponding to the data plane function module;

a first determining module 12, configured to determine a cache resource included in the computing processing module for implementing a data processing operation, where a last level cache in the cache resource includes a data through cache, where a data plane function module runs on the computing processing module;

The first processing module 13 is configured to perform buffer management based on the packet attribute, the data receiving attribute, and the data through buffer.

The cache management apparatus shown in fig. 15 may perform the method of the embodiment shown in fig. 5 to 10, and reference is made to the relevant description of the embodiment shown in fig. 5 to 10 for a part not described in detail in this embodiment. The implementation process and the technical effect of this technical solution are described in the embodiments shown in fig. 5 to 10, and are not described herein.

In one possible design, the structure of the cache management apparatus shown in fig. 15 may be implemented as an electronic device. Referring to fig. 16, the cache management apparatus in this embodiment may be implemented as an electronic device, and specifically, the electronic device may include: a first processor 21 and a first memory 22. The first memory 22 is used for storing a program for executing the cache management method provided in the embodiment shown in fig. 5 described above for the corresponding electronic device, and the first processor 21 is configured to execute the program stored in the first memory 22.

The program comprises one or more computer instructions, wherein the one or more computer instructions, when executed by the first processor 21, are capable of performing the steps of: acquiring data packet attributes of the data packet received by the data plane functional module and data receiving attributes corresponding to the data plane functional module; determining a cache resource for realizing data processing operation, wherein the cache resource comprises a data through cache, and the last level of cache in the cache resource is used for enabling the data surface function module to run on the computing processing module; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

Further, the first processor 21 is further configured to perform all or part of the steps in the embodiment shown in fig. 5. The electronic device may further include a first communication interface 23 in a structure for the electronic device to communicate with other devices or a communication network.

In addition, the present embodiment provides a computer storage medium for storing computer software instructions for an electronic device, which includes a program for executing the cache management method in the embodiment of the method shown in fig. 5.

Furthermore, the present embodiment provides a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to perform the cache management method of the method embodiment shown in fig. 5.

Referring to fig. 17, the present embodiment provides a cache management device, where the cache management device is deployed on a public cloud, and a load balancer is deployed on the public cloud, and the load balancer runs on a core processor CPU; the cache management apparatus is configured to perform the cache management method shown in fig. 11, and specifically, the cache management apparatus may include:

a second obtaining module 31, configured to obtain a packet attribute of a packet received by the load balancer and a data receiving attribute corresponding to the load balancer;

A second determining module 32, configured to determine a cache resource included in the computing processor for implementing a data processing operation, where a last level cache in the cache resource includes a data through cache, and where the load balancer runs on the computing processor;

the second processing module 33 is configured to perform buffer management based on the packet attribute, the data receiving attribute, and the data through buffer.

The cache management apparatus shown in fig. 17 may perform the method of the embodiment shown in fig. 11, and reference is made to the related description of the embodiment shown in fig. 11 for a part of this embodiment that is not described in detail. The implementation process and the technical effect of this technical solution are described in the embodiment shown in fig. 11, and are not described herein.

In one possible design, the structure of the cache management apparatus shown in fig. 17 may be implemented as an electronic device. Referring to fig. 18, the cache management apparatus in this embodiment may be implemented as an electronic device, and specifically, the electronic device may include: a second processor 41 and a second memory 42. The second memory 42 is used for storing a program for executing the cache management method provided in the embodiment shown in fig. 11 described above for the corresponding electronic device, and the second processor 41 is configured to execute the program stored in the second memory 42.

The program comprises one or more computer instructions, wherein the one or more computer instructions, when executed by the second processor 41, are capable of performing the steps of: acquiring a data packet attribute of a data packet received by a load balancer and a data receiving attribute corresponding to the load balancer; determining a cache resource for realizing data processing operation, wherein the cache resource comprises a data through cache, and a load balancer runs on the computing processor; and performing cache management based on the data packet attribute, the data receiving attribute and the data through cache.

Further, the second processor 41 is further configured to perform all or part of the steps in the embodiment shown in fig. 11. The electronic device may further include a second communication interface 43 in the structure of the electronic device, for communicating with other devices or a communication network.

In addition, the present embodiment provides a computer storage medium for storing computer software instructions for an electronic device, which includes a program for executing the cache management method in the embodiment of the method shown in fig. 11.

Furthermore, the present embodiment provides a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to perform the cache management method of the method embodiment shown in fig. 11.

Referring to fig. 19, the present embodiment provides a vehicle control device, which is disposed on the same system platform as the cache management device, and is configured to execute the vehicle control method shown in fig. 13, and specifically, the vehicle control device may include:

a third obtaining module 51, configured to obtain a cache adjustment instruction sent by the cache management device, where the cache adjustment instruction is determined by a data packet attribute, a data reception attribute, and a data direct cache, where the data packet attribute is used to identify an attribute of a data packet that can be received by the vehicle control device, the data reception attribute is used to identify an upper limit of a number of data packets that can be received by the vehicle control device, and the data direct cache is a part of a last level cache in the computing processing module in the vehicle control device;

and a third processing module 52, configured to perform cache management on a computing processing module (e.g., a CPU module) in the vehicle control device based on the cache adjustment instruction, so as to ensure stable control of the vehicle to be controlled.

The vehicle control apparatus shown in fig. 19 may perform the method of the embodiment shown in fig. 13, and reference is made to the description of the embodiment shown in fig. 13 for a part not described in detail in this embodiment. The implementation process and the technical effect of this technical solution are described in the embodiment shown in fig. 13, and are not described herein.

In one possible design, the structure of the vehicle control apparatus shown in fig. 19 may be implemented as an electronic device. Referring to fig. 20, the vehicle control apparatus for implementing the vehicle control method in this embodiment may be implemented as an electronic device, and specifically, the electronic device may include: a third processor 61 and a third memory 62. Wherein the third memory 62 is for storing a program for the corresponding electronic device to execute the vehicle control method provided in the embodiment shown in fig. 13 described above, and the third processor 61 is configured to execute the program stored in the third memory 62.

The program comprises one or more computer instructions, wherein the one or more computer instructions, when executed by the third processor 61, are capable of performing the steps of: the method comprises the steps of obtaining a cache adjustment instruction sent by a cache management device, wherein the cache adjustment instruction is determined through a data packet attribute, a data receiving attribute and a data direct cache, the data packet attribute is used for identifying the attribute of a data packet which can be received by a vehicle control device, the data receiving attribute is used for identifying the upper limit of the number of the data packet which can be received by the vehicle control device, and the data direct cache is a part of the last-stage cache in a calculation processing module in the vehicle control device; and carrying out cache management on a calculation processing module (such as a CPU module) in the vehicle control device based on the cache adjustment instruction so as to ensure stable control on the vehicle to be controlled.

Further, the third processor 61 is further configured to perform all or part of the steps in the embodiment shown in fig. 13. The electronic device may further include a third communication interface 63 in the structure for the electronic device to communicate with other devices or a communication network.

In addition, the present embodiment provides a computer storage medium for storing computer software instructions for an electronic device, which contains a program for executing the vehicle control method in the embodiment of the method shown in fig. 13.

Furthermore, the present embodiment provides a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to execute the vehicle control method in the method embodiment shown in fig. 13.

Referring to fig. 21, this embodiment provides a control apparatus for a virtual reality device, where the control apparatus for a virtual reality device and a cache management apparatus are disposed on the same system platform, and the control apparatus for a virtual reality device is configured to execute the control method for a virtual reality device shown in fig. 14, and specifically the control apparatus for a virtual reality device may include:

a fourth obtaining module 71, configured to obtain a cache adjustment instruction sent by the cache management device, where the cache adjustment instruction is determined by a data packet attribute, a data receiving attribute, and a data direct cache, where the data packet attribute is used to identify an attribute of a data packet that can be received by the virtual reality device, the data receiving attribute is used to identify an upper limit of a number of data packets that can be received by the virtual reality device, and the data direct cache is a part of a last level cache in the computing processing module in the virtual reality device;

The fourth processing module 72 is configured to perform cache management on the computing processing module in the virtual reality device based on the cache adjustment instruction, so as to ensure stable control over the virtual reality device.

The control device of the virtual reality apparatus shown in fig. 21 may perform the method of the embodiment shown in fig. 14, and reference is made to the related description of the embodiment shown in fig. 14 for a part not described in detail in this embodiment. The implementation process and the technical effect of this technical solution are described in the embodiment shown in fig. 14, and are not described herein.

In one possible design, the control device of the virtual reality device shown in fig. 21 may be implemented as an electronic device. Referring to fig. 22, a control apparatus of a virtual reality device used in a control method of a virtual reality device in this embodiment may be implemented as an electronic device, and specifically, the electronic device may include: a fourth processor 81 and a fourth memory 82. The fourth memory 82 is used for storing a program for executing the control method of the virtual reality device provided in the embodiment shown in fig. 14, which is described above, by the corresponding electronic device, and the fourth processor 81 is configured to execute the program stored in the fourth memory 82.

The program comprises one or more computer instructions, wherein the one or more computer instructions, when executed by the fourth processor 81, are capable of performing the steps of: the method comprises the steps of obtaining a cache adjustment instruction sent by a cache management device, wherein the cache adjustment instruction is determined through a data packet attribute, a data receiving attribute and a data direct cache, the data packet attribute is used for identifying the attribute of a data packet which can be received by virtual reality equipment, the data receiving attribute is used for identifying the upper limit of the number of the data packet which can be received by the virtual reality equipment, and the data direct cache is a part of the last-stage cache in a calculation processing module in the virtual reality equipment; and carrying out cache management on a calculation processing module in the virtual reality equipment based on the cache adjustment instruction so as to ensure stable control on the virtual reality equipment.

Further, the fourth processor 81 is further configured to perform all or part of the steps in the embodiment shown in fig. 14. The electronic device may further include a fourth communication interface 83 in the structure for the electronic device to communicate with other devices or a communication network.

The present embodiment provides a computer storage medium storing computer software instructions for an electronic device, which includes a program for executing the control method of the virtual reality device in the method embodiment shown in fig. 14.

The present embodiment provides a computer program product comprising: a computer program which, when executed by a processor of an electronic device, causes the processor to perform the method of controlling a virtual reality device in the method embodiment shown in fig. 14.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide corresponding operation entries for the user to select authorization or rejection.

The apparatus embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by adding necessary general purpose hardware platforms, or may be implemented by a combination of hardware and software. Based on such understanding, the foregoing aspects, in essence and portions contributing to the art, may be embodied in the form of a computer program product, which may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement data storage by any method or technology. The data may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store data that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A cache management system, comprising:

the cache management module is in communication connection with the data surface functional module and the calculation processing module and is used for acquiring data packet attributes corresponding to the data packets and data receiving attributes corresponding to the data surface functional module; performing cache management based on the data packet attribute, the data receiving attribute and the data direct cache;

the cache management module is further used for acquiring a data scene corresponding to the data packet in the process of processing the data packet; and adjusting the direct cache size of the data direct cache based on the data scene.

2. The system of claim 1, wherein when the cache management module performs cache management based on the packet attributes, the data reception attributes, and the data pass-through cache, the cache management module is configured to:

Detecting whether a cache use problem exists or not based on the data packet attribute, the data receiving attribute and the data direct cache;

if the cache using problem exists, determining a target data receiving attribute based on the data packet attribute and the data direct-connection cache;

and updating the data receiving attribute to the target data receiving attribute.

3. The system of claim 2, wherein when the cache management module detects whether there is a cache usage problem based on the packet attributes, the data reception attributes, and the data pass-through cache, the cache management module is configured to:

determining a received data amount parameter based on the data packet attribute and the data reception attribute;

and detecting whether a cache use problem exists or not based on the received data quantity parameter and the data direct-connection cache.

4. The system of claim 3, wherein the packet attributes comprise an average size of received packets, the data reception attributes comprising a reception descriptor for identifying an upper limit on a number of packets that the data plane function module is capable of receiving;

when the cache management module determines a received data amount parameter based on the data packet attribute and the data receiving attribute, the cache management module is configured to:

Obtaining a product value between the average size and the receive descriptor;

and determining the received data amount parameter based on the product value.

5. The system of claim 3, wherein when the cache management module detects whether there is a cache usage problem based on the received data amount parameter and the data pass-through cache, the cache management module is to:

determining the direct cache size of the data direct cache;

when the received data quantity parameter is smaller than or equal to the direct cache size, determining that no cache use problem exists;

and when the received data quantity parameter is larger than the direct-connection cache size, determining that a cache use problem exists.

6. The system of any of claims 1-5, wherein the cache management module is further to:

in the process of processing the data packets, acquiring a first data packet loss ratio corresponding to the last level of buffer memory and/or a second data packet loss ratio corresponding to the data through buffer memory;

and adjusting the size of the through cache based on the first data packet loss ratio and/or the second data packet loss ratio.

7. The system of claim 6, wherein when the cache management module adjusts the through cache size based on the second packet loss ratio, the cache management module is to:

acquiring memory bandwidth information;

and adjusting the size of the through cache based on the second data packet loss ratio and the memory bandwidth information.

8. The system of claim 7, wherein when the cache management module adjusts the through cache size based on the second packet loss ratio and the memory bandwidth information, the cache management module is to:

when the second data packet loss ratio is greater than a second preset threshold value or the memory bandwidth information is greater than a preset bandwidth threshold value, increasing the size of the through cache;

and when the second data packet loss ratio is smaller than or equal to a second preset threshold value or the memory bandwidth information is smaller than or equal to the preset threshold value, reducing the size of the direct-connection buffer.

9. The system of claim 6, wherein when the cache management module adjusts the pass-through cache size based on the first packet loss ratio and the second packet loss ratio, the cache management module is to:

When the first data packet loss ratio is smaller than a first preset threshold value or the second data packet loss ratio is larger than a second preset threshold value, increasing the size of the through cache;

when the first data packet loss ratio is greater than a first preset threshold or the second data packet loss ratio is less than a second preset threshold, reducing the size of the through cache;

and when the first data packet loss ratio is larger than a first preset threshold value and the second data packet loss ratio is larger than a second preset threshold value, or the first data packet loss ratio is smaller than the first preset threshold value and the second data packet loss ratio is smaller than the second preset threshold value, keeping the size of the through buffer unchanged.

10. A private network cache management system, comprising:

The private network cache management module is in communication connection with the private network data surface function module and the private network calculation processing module and is used for determining data packet attributes corresponding to the private network data packets and data receiving attributes corresponding to the private network data surface function module; performing cache management based on the data packet attribute, the data receiving attribute and the data direct cache;

the private network cache management module is further used for acquiring a data scene corresponding to the private network data packet in the process of processing the private network data packet; and adjusting the direct cache size of the data direct cache based on the data scene.

11. A cache management method, comprising:

performing cache management based on the data packet attribute, the data receiving attribute and the data direct cache;

The method further comprises the steps of:

acquiring a data scene corresponding to a data packet in the process of processing the data packet;

and adjusting the direct cache size of the data direct cache based on the data scene.

12. The cache management method is characterized by being applied to a cache management device, wherein the cache management device is deployed on a public cloud, a load balancer is deployed on the public cloud, and the load balancer operates on a computing processor; the method comprises the following steps:

the method further comprises the steps of:

13. An electronic device, comprising: a memory, a processor; wherein the memory is configured to store one or more computer instructions, wherein the one or more computer instructions, when executed by the processor, implement the method of claim 11 or 12.