CN116193869A - Self-assembled monolayer integrated chip based on-chip nanoparticle structure - Google Patents

Abstract

The invention relates to a self-assembled monolayer integrated chip based on an on-chip nanoparticle structure, which comprises a silicon substrate, a silicon dioxide insulating layer, an organic glass layer, a bottom electrode, a molecular layer, nanoparticles and a top electrode, wherein the silicon dioxide insulating layer is arranged on the silicon substrate; a silicon dioxide insulating layer grows on the surface of the silicon substrate, and the organic glass layer is laid on the silicon dioxide insulating layer; the bottom electrode is arranged in the organic glass layer and is in contact with the silicon dioxide insulating layer; the molecular layer is arranged between the bottom electrode and the organic glass layer; the lower part of the nano particles passes through the organic glass layer and then contacts with the molecular layer, and the upper part of the nano particles is exposed outside the organic glass layer; the top electrode is disposed on an upper surface of the organic glass layer and is in contact with an upper portion of the nanoparticle.

Description

Self-assembled monolayer integrated chip based on-chip nanoparticle structure

Technical Field

The invention relates to the field of integrated chips, in particular to a self-assembled monolayer integrated chip based on an on-chip nanoparticle structure.

Background

However, with the improvement of the integration level of the transistor, the process of the chip starts to enter the quantum field, and the problems of short channel effect, hot carrier injection and the like become the problem of further shrinking the current process. The development goal of the molecular electronics is to construct a functional electronic device with molecular scale by taking molecules as basic units in a molecular engineering mode to replace a silicon-based semiconductor device, so that the scale limit of the traditional semiconductor technology is overcome, the development goal is a development direction with great potential for miniaturization of the electronic device in the future, and along with the development of the molecular electronics, various multifunctional molecular devices such as molecular diodes, molecular transistors, molecular switches and the like are reported, and the great potential of the molecular device is shown.

In the research of molecular electronics, self-assembled monolayers (Self-assembled Monolayer, SAM) are an important research technique for constructing molecular devices due to their highly ordered structure and strong stability. The formation principle of SAM is that organic molecules in gas or solution form a micro-nano structure with molecular scale, which is thermodynamically stable and orderly arranged, on the surface of metal and oxide thereof by the action forces of chemical bond, van der Waals force, electrostatic force and the like.

At present, three main application technical schemes for researching a molecular layer and constructing a molecular layer device at home and abroad are provided: cross metal line technology, metal deposition, and liquid Gallium Indium (EGaIn) as SAM top electrode. Metal atoms are relatively easily deposited at defective locations in the monolayer and can easily cause shorting of the entire monolayer device. The liquid Gallium Indium alloy (EGaIn) is used as a SAM top electrode to construct a molecular layer device, and has the following advantages: (1) The liquid gallium indium alloy has low contact resistance, no toxicity and volatility, and no harm to human body; (2) The liquid gallium indium alloy surface has a natural oxide layer, has stronger mechanical stability, and is beneficial to controlling the contact area between the top electrode and the monomolecular layer; (3) The liquid gallium indium alloy is not easy to react with the metal substrate to form alloy, and the short circuit phenomenon of the monolayer device in the test process can be reduced.

At present, two main technical schemes are adopted based on gallium indium alloy as a SAM top electrode, and one scheme is that an ultraviolet light curing adhesive is adopted to support a molecular junction formed by an EGaIn microelectrode, the SAM and a bottom electrode. And secondly, preparing a micron-sized micro-channel template on a PDMS material through a micro-nano processing technology, so as to prepare a series of electrode micro-channel arrays, filling EGaIn into the micro-channels by using external acting force and stabilizing the EGaIn, and constructing a tunneling junction array based on SAM. However, due to the micro-channel resistance, the method is difficult to continue to advance to the nano-scale with practical application significance in principle, and the characteristic that EGaIn is opaque per se makes a molecular layer device greatly limited in the photoelectric field with great potential. Therefore, the problems of low yield of molecular layer devices, large difference between devices and the like exist at present.

It is an object of the present invention to design a self-assembled monolayer integrated chip based on-chip nanoparticle structures, which addresses the problems of the prior art described above.

Disclosure of Invention

The present invention is directed to providing a self-assembled monolayer integrated chip based on-chip nanoparticle structures that is effective in solving at least one of the problems of the prior art.

The technical scheme of the invention is as follows:

the self-assembled monolayer integrated chip based on the on-chip nanoparticle structure comprises a silicon substrate, a silicon dioxide insulating layer, an organic glass layer, a bottom electrode, a molecular layer, nanoparticles and a top electrode;

a silicon dioxide insulating layer grows on the surface of the silicon substrate, and the organic glass layer is laid on the silicon dioxide insulating layer; the bottom electrode is arranged in the organic glass layer and is in contact with the silicon dioxide insulating layer; the molecular layer is arranged between the bottom electrode and the organic glass layer; the lower part of the nano particles passes through the organic glass layer and then contacts with the molecular layer, and the upper part of the nano particles is exposed outside the organic glass layer; the top electrode is disposed on an upper surface of the organic glass layer and is in contact with an upper portion of the nanoparticle.

Further, the bottom electrode is used as a drain electrode of the self-assembled monolayer integrated chip, the top electrode is used as a source electrode of the self-assembled monolayer integrated chip, and the molecular layer is used as a dielectric layer of the self-assembled monolayer integrated chip.

Further, the molecular layer contains molecules with destructive quantum interference effects.

Further, by changing the potential difference between the source electrode and the drain electrode, the conduction mode is switched into molecular auxiliary tunneling or electron direct tunneling, so that the conductance of the self-assembled monolayer integrated chip is changed, and the connection or disconnection between the source electrode and the drain electrode is controlled.

Further, the self-assembled monolayer integrated chip is prepared by the following method:

cleaning and drying a silicon oxide wafer to obtain a silicon substrate covered with a silicon dioxide insulating layer;

spin-coating photoresist on the upper surface of the silicon dioxide insulating layer and drying;

performing mask photoetching and developing on the photoresist, so as to develop a bottom electrode pattern corresponding to the first mask template on the photoresist;

growing a chromium layer on the area of the upper surface of the silicon dioxide insulating layer, which corresponds to the bottom electrode pattern, by adopting electron beam evaporation, then growing a gold film on the upper surface of the chromium layer by adopting electron beam evaporation, and washing off photoresist to obtain a bottom electrode, which corresponds to the bottom electrode pattern;

immersing the silicon substrate with the bottom electrode in a molecular solution containing destructive quantum interference effects, so that the outer surface of the bottom electrode self-assembles the molecular layer;

dripping gold nanoparticle solution on the molecular layer to enable gold nanoparticles to be deposited on the outer surface of the molecular layer;

coating PMMA on the upper surface of the silicon substrate to cover the gold nanoparticles, and etching the PMMA to expose the upper parts of the gold nanoparticles to prepare the organic glass layer;

and covering the upper surface of the organic glass layer by a second mask template, wherein the second mask template is provided with a top electrode pattern, and growing a gold film on the upper surface of the organic glass layer by adopting electron beam evaporation to obtain the top electrode.

Further, the bottom electrode pattern includes device regions in the shape of parallel lines staggered and disposed in gaps, and the top electrode pattern is in the shape of a transverse line passing over the corresponding device regions.

Further, depositing gold nanoparticles on the outer surface of the molecular layer comprises:

the molecules with destructive quantum interference effect and gold nanoparticles are covalently bonded.

Further, coating PMMA on the upper surface of the silicon substrate to cover the gold nanoparticles, wherein the step of coating PMMA comprises the following steps: defining the vertical distance from the silicon substrate to the top end of the nanoparticle as D, and coating PMMA with the thickness of D+50nm on the upper surface of the silicon substrate;

the etching of PMMA to expose an upper portion of the gold nanoparticles includes: and (3) etching the PMMA with the thickness of 100nm to expose the upper part of the gold nanoparticles.

Further, the method for using the self-assembled monolayer integrated chip comprises the following steps:

grounding the top electrode, applying continuously-changing electrode potential on the bottom electrode, obtaining the conductivity change of the molecular layer device, obtaining a conductivity turning point under the continuously-changing electrode potential, and taking the voltage corresponding to the conductivity turning point as the threshold voltage of the self-assembled monolayer integrated chip;

when a threshold voltage or more is applied to the bottom electrode, conduction is performed between the top electrode and the bottom electrode;

when a voltage equal to or lower than a threshold voltage is applied to the bottom electrode, the top electrode and the bottom electrode are disconnected.

Accordingly, the present invention provides the following effects and/or advantages:

the device has the advantages that the molecular layer is encapsulated and protected by PMMA, the contact area between the nano particles and the SAM layer at the bottom layer is extremely small, the damage to the molecular layer caused by high temperature and other factors in the process of covering the top electrode in the traditional metal deposition method is greatly reduced, the short circuit rate of the device is reduced, and meanwhile, the stability of the device is greatly improved. Compared with the technical scheme of the current mainstream EGaIn device, the integration level of the device is improved to reach the micron level. On the basis of the technical scheme, the substrate is subjected to specific patterning, so that the integration level can be improved to hundred nanometers, and the application requirements of the current mainstream devices are met.

Compared with the characteristic of EGaIn light-tightness, the top electrode of the device has light-tightness and has wider application range in the photoelectric field; meanwhile, the optical nano cavity formed by the gold nano particles of the device and the bottom gold electrode has a finite field effect, and the field enhancement can reach more than eight orders of magnitude.

The method has good adaptability and replaceability to different substrates and electrode materials, has wider application range, and can be suitable for researching the special properties of various heterogeneous materials.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

Fig. 1 is a schematic structural diagram of one embodiment of the present invention.

Fig. 2 is a cross-sectional view of fig. 1.

Fig. 3-4 are graphs of experimental data for one embodiment of the present invention.

FIG. 5 is a schematic illustration of a preparation flow of one embodiment of the present invention.

FIG. 6 is a schematic diagram of a first reticle according to one embodiment of the invention.

FIG. 7 is a schematic diagram of a second masking template according to one embodiment of the present invention.

Fig. 8 is a schematic diagram of the cooperation of the second mask template and the bottom electrode according to one embodiment of the present invention.

Detailed Description

For the convenience of understanding by those skilled in the art, the structure of the present invention will now be described in further detail with reference to the accompanying drawings:

referring to fig. 1, a self-assembled monolayer integrated chip based on an on-chip nanoparticle structure includes a silicon substrate 1, a silicon oxide insulating layer, an organic glass layer 4, a bottom electrode 2, a molecular layer 3, nanoparticles 5, and a top electrode 6;

a silicon dioxide insulating layer grows on the surface of the silicon substrate 1, and the organic glass layer 4 is paved on the silicon dioxide insulating layer;

in this embodiment, a silicon oxide wafer may be used as the silicon substrate 1 having a silicon oxide insulating layer grown on the surface, and PMMA may be used as the organic glass layer 4. Wherein, the silicon oxide slice and PMMA are both directly adopted in the prior art.

The bottom electrode 2 is arranged in the organic glass layer 4 and is in contact with the silicon dioxide insulating layer; the molecular layer 3 is arranged between the bottom electrode 2 and the organic glass layer 4;

in this embodiment, the bottom electrode may be disposed on the silicon substrate, and then the molecular layer 3 is coated on the periphery of the bottom electrode, and then the PMMA is coated on the silicon substrate so as to be coated on the periphery of the molecular layer 3.

The lower part of the nano particles 5 passes through the organic glass layer 4 and then contacts with the molecular layer 3, and the upper part of the nano particles 5 is exposed outside the organic glass layer 4;

in this embodiment, the organic glass layer has the characteristic of being etchable, and after being coated on the periphery of the molecular layer by PMMA, the upper surface of a certain thickness is etched on the organic glass layer, so that a part of the nanoparticles are exposed. Nanoparticles can be assembled to the outer surface of the molecular layer by a self-assembly method.

The top electrode 6 is disposed on the upper surface of the organic glass layer 4 and is in contact with the upper portion of the nanoparticles 5.

In this embodiment, the nanoparticles serve as contact points between the top electrode and the molecular layer, so that the contact area is reduced to the nanometer level, and the short circuit phenomenon caused by insufficient dense assembly of the molecular layer is greatly reduced. And the gold nano particles and the bottom electrode form an optical nano cavity, which has a finite field effect, a very strong field enhancement effect and great application potential in the photoelectric field.

Further, the bottom electrode is used as a drain electrode of the self-assembled monolayer integrated chip, the top electrode is used as a source electrode of the self-assembled monolayer integrated chip, and the molecular layer is used as a dielectric layer of the self-assembled monolayer integrated chip.

In this embodiment, a bias response switch is formed by the silicon substrate 1, the silicon dioxide insulating layer, the organic glass layer 4, the bottom electrode 2, the molecular layer 3, the nanoparticles 5, the top electrode 6 and the connection method thereof. The field effect transistor comprises a source electrode, a drain electrode and a dielectric layer. Wherein the dielectric layer undergoes a corresponding change in an electrical property, such as conductance, across the voltage difference between the source and drain electrodes, thereby controlling the conduction or disconnection between the source and drain electrodes. In this embodiment, the molecular layer is used as the dielectric layer therein, and under the condition of receiving the voltage change of the silicon substrate, the molecular layer will change correspondingly, so as to control the on/off between the source electrode and the drain electrode.

Further, the molecular layer contains molecules with destructive quantum interference effects.

In this embodiment, the molecules with destructive quantum interference effects may be p-terphenyl, m-terphenyl, or others. And are not limited herein.

The conductance of a single molecule is achieved by an electron wave function, which is similar to an acoustic wave. Just as sound waves "bypass" the wall across an obstruction, electrons can cross the insulating layer by quantum tunneling. The quantum tunneling effect of electrons bypassing molecules increases exponentially with decreasing molecular size, with smaller molecular sizes, more pronounced quantum tunneling effects. Studies have shown that tunneling of electrons in single molecule junctions can be suppressed by destructive quantum interference, a mechanism that is not length dependent. By destructive quantum interference is meant that when the peaks and troughs of the two waves are completely displaced, the electron wave function will oscillate off, thus suppressing quantum tunneling. Therefore, the molecular layer contains molecules with destructive quantum interference effect, so that quantum tunneling of electrons can be inhibited or released under the condition of corresponding potential, and the source electrode and the drain electrode are disconnected or connected, thereby realizing control of the monolayer integrated chip.

Further, by changing the potential difference between the source electrode and the drain electrode, the conduction mode is switched into molecular auxiliary tunneling or electron direct tunneling, so that the conductance of the self-assembled monolayer integrated chip is changed, and the connection or disconnection between the source electrode and the drain electrode is controlled.

The molecular layer is taken as an example of a m-terphenyl molecular layer, has destructive quantum interference effect, and the conduction of the self-assembled monolayer integrated chip is dominated by molecular auxiliary tunneling under the normal bias voltage of 0.5V, and electrons interfere when tunneling through two electron orbits of LUMO-HOMO, so that the self-assembled monolayer integrated chip is in a low-conductivity state; when the bias voltage is above 0.5V, the conduction of the self-assembled monolayer integrated chip is dominated by direct tunneling of electrons and is not affected by molecules, so that the self-assembled monolayer integrated chip is in a high-conductivity state. And thus can control on or off between the source and the drain.

Experimental data

The top electrode and the bottom electrode are communicated through the nano particles, and as the nano particles are obtained by reducing chloroauric acid by citrate under the same environment, the particle size and the sectional area of the nano particles are similar, the contact area of the top electrode and the bottom electrode is hundred square nanometers, the contact area of an EGaIn device is generally hundred square micrometers, and theoretically, the contact area between the top electrode and the bottom electrode provided by the embodiment is one thousandth of the contact area of the existing EGaIn device; and the area of the EGaIn device is uncontrollable, and the electrical property difference of each EGaIn device is greatly different. The device with the m-terphenyl as the molecular layer provided by the embodiment has extremely small difference of the electrical characteristics of each node, 600 nodes can be prepared on one 4-inch unit chip, the yield of the device is more than 10%, 60 or more devices can be obtained for testing by one-time preparation, and the yield can be greatly improved along with the improvement of the photoetching technology.

Referring to fig. 3, the conductance of the device measured at 0.1V dc bias is an order of magnitude greater than the conductance of a single molecule, consistent with the predictions of the conductance of a monolayer device.

Referring to fig. 4, IV scanning is performed on the m-terphenyl molecular layer device and the p-terphenyl molecular layer device to obtain corresponding IV graphs, and the phenomenon that the conductance becomes large along with the increase of the voltage can be seen from the graph, which proves that the tunneling mode changes along with the decrease of the energy barrier, and the self-assembled monolayer integrated chip provided by the embodiment has corresponding conductance under different potentials, and can be used for controlling the conductance of the chip by applying different potentials so as to control the on or off of the chip.

The following describes a method for preparing the self-assembled monolayer integrated chip provided in this embodiment.

Further, the self-assembled monolayer integrated chip is prepared by the following method:

s1, cleaning and drying a silicon oxide wafer to be used as a silicon substrate covered with a silicon dioxide insulating layer;

firstly, cleaning a silicon oxide wafer substrate with the thickness of 4 inches and 500um according to the following procedures: and respectively ultrasonically cleaning acetone, ethanol and deionized water for 10min, and then drying with nitrogen for later use.

S2, spin-coating photoresist on the upper surface of the silicon dioxide insulating layer and drying;

placing the silicon oxide wafer substrate into a 135 ℃ oven for drying and dewatering for more than 2 hours, and spin-coating HMDS tackifier after cooling to increase the adhesion between photoresist and the substrate; and spin-coating photoresist (AZ 5214-E, reverse photoresist, forming an inverted T-shaped reverse table after exposure, and facilitating subsequent stripping) for subsequent exposure patterning. And (3) after the spin coating is finished, placing the substrate on a constant temperature hot plate at 90-115 ℃ for baking for 1-5min. The baking temperature and the baking time depend on the thickness of the photoresist and the substrate, and the aim of the baking operation is to remove the redundant solvent in the photoresist.

S3, carrying out mask photoetching and developing on the photoresist, so as to develop a bottom electrode pattern corresponding to the first mask template on the photoresist;

in this embodiment, AZ5214E positive photoresist is selected, and post-baking inversion can be performed according to the characteristics of AZ5214E photoresist, where the photoresist is positive photoresist. And taking out the exposed substrate, and placing the substrate on a constant temperature hot plate at 90-115 ℃ for inversion for 1-5min. The inversion temperature and the duration depend on the thickness of the photoresist and the substrate, so as to realize the inversion of the photoresist pattern. The phenomenon of insufficient inversion is easy to occur when the temperature is too low, and the photoresist is easy to denature when the temperature is too high, so that the photoresist result is greatly influenced. And taking down the substrate from the hot plate, cooling to room temperature, placing the substrate on a photoetching alignment machine again, taking down the mask, and exposing by selecting proper light intensity. And taking down the substrate after photoetching, placing the substrate in positive photoresist developer for developing for 60-150s, and stopping developing until floccules do not float out on the surface of the film. And then flushing with flowing deionized water for 120s to remove the residual developer on the surface, drying the surface with nitrogen, and putting into a 135 ℃ oven for film hardening for 15min.

Specifically, the mask photoetching and developing of the photoresist comprises the following steps:

performing first ultraviolet exposure on the positive photoresist according to the first mask template, and generating carboxylic acid through photolysis reaction;

the carboxylic acid promotes the resin of the first ultraviolet exposure area in the positive photoresist to generate a crosslinking reaction at high temperature, so that the ultraviolet exposure area in the positive photoresist is insoluble in an alkaline developer;

and taking down the first mask template to carry out second ultraviolet exposure, generating carboxylic acid in the area which is not subjected to the first ultraviolet exposure, and dissolving the carboxylic acid in alkaline developer after development to obtain the pattern identical to the mask template.

AZ5214 photoresist consists essentially of 3 parts: photosensitive component, resin and solvent.

When the mask is exposed, the photosensitive component of the exposed area is converted into carboxylic acid, and the carboxylic acid after being baked again promotes the resin of the exposed area to generate a crosslinking reaction, so that the exposed area is insoluble in an alkaline developing solution, the step is also called glue inversion baking, then the mask is subjected to one-step flood exposure, namely maskless exposure, the carboxylic acid is generated in the area which is not exposed for the first time, and the carboxylic acid is dissolved in the alkaline developing solution after being developed to obtain the pattern which is the same as the mask.

The photoetching is carried out by two ultraviolet exposures, so that the inverted trapezoid glue appearance can be obtained, and the stripping of the subsequent electron beam vapor gold-plating and chromium film is facilitated. The metal side wall after the inverted trapezoid glue appearance evaporation is not adhered, and the smooth pattern side wall can be obtained after stripping, so that the device preparation yield is improved.

The first mask pattern of this embodiment is shown in fig. 6. Corresponding areas can be etched in the photoresist through the mask template, so that the photoresist is exposed corresponding to the silicon substrate below the first mask template.

And S4, growing a chromium layer on the region, corresponding to the bottom electrode pattern, of the upper surface of the silicon dioxide insulating layer by adopting electron beam evaporation, then growing a gold film on the upper surface of the chromium layer by adopting electron beam evaporation, and washing off photoresist to obtain the bottom electrode corresponding to the bottom electrode pattern.

On the basis of the pattern, an electron beam evaporation plating is adopted to grow a chromium layer with the thickness of 1-5nm for increasing the adhesive force between gold and a silicon substrate, and a gold film with the thickness of 30-200nm (film forming is required) and the surface roughness is within 2nm, wherein the growth rate is dependent on the used equipment and process conditions. And (3) soaking the substrate subjected to film coating in acetone for more than 2 hours, removing most of the structures after ultrasonic treatment for 5 seconds, and then sequentially stripping the substrate in acetone and ethanol by using dust-free cotton swabs to obtain a first layer of gold electrode pattern. A patterned bottom electrode as shown in fig. 5 was obtained.

S5, immersing the silicon substrate with the bottom electrode into a molecular solution with destructive quantum interference effect, so that the outer surface of the bottom electrode self-assembles the molecular layer;

taking a terphenyl molecule as an example, immersing a cell into a 0.1-3mM terphenyl molecule solution, immersing the cell for more than 12 hours with TMB as a solvent to self-assemble a molecular layer on the surface of the cell, flushing the surface of the cell with a large amount of solvent, and drying with nitrogen for later use. The resulting dip-assembled molecules are shown in FIG. 5.

S6, dripping gold nanoparticle solution on the molecular layer to enable gold nanoparticles to be deposited on the outer surface of the molecular layer;

preparing 0.05-0.5mg/mL Au nano-particle solution, wherein the deposition rate of Au nano-particles is easy to control under the concentration, and the number of nano-particles of most device nodes is ensured to be less than 5, so that the yield is improved. The Au nano particles are selected because the particle size of the Au nano particles is proper, the scattering light intensity is too weak, the coupling peak is too much to be red shifted and difficult to detect, the Au nano particle solution of 0.05-0.5mg/mL is dripped on the surface of the silicon substrate to contact the molecular layer, the Au nano particles are assembled for a proper amount of time, then a large amount of deionized water is used for flushing, molecules physically adsorbed on the surface are removed, and then the Au nano particles are dried by nitrogen for standby. Thereby depositing gold nanoparticles on the outer surface of the molecular layer to obtain the deposited gold nanoparticles as shown in fig. 5.

S7, coating PMMA on the upper surface of the silicon substrate to enable the PMMA to cover the gold nanoparticles, and etching the PMMA to enable the upper parts of the gold nanoparticles to be exposed to obtain the organic glass layer;

and spin-coating PMMA on the cell for 1min, wherein the spin-coating thickness is adapted to the particle size, and the thickness exceeds the particle part, so that good coating property of the particles is ensured. And (3) etching PMMA on the surface of the cell by using inductively coupled plasma etching equipment, and properly exposing the top of the gold nanoparticles by using proper oxygen flow and upper radio frequency power. PMMA coated, ICP etched as shown in fig. 5 was obtained.

And S8, covering the upper surface of the organic glass layer through a second mask template, wherein the second mask template is provided with a top electrode pattern, and growing a gold film on the upper surface of the organic glass layer by adopting electron beam evaporation to obtain the top electrode.

The hard mask is used for growing a gold film with the thickness of 5-20nm by adopting electron beam evaporation, under the condition of ensuring the film formation of evaporated metal under the instrument condition and good electric conduction, the thickness of the top electrode gold film is reduced, the light transmittance is increased, and the gold film with the light transmittance of 20nm or less is generally regarded as the light transmittance, and the light transmittance is more than 50%. Electron beam evaporation as shown in fig. 5 was obtained. Thus, a self-assembled monolayer integrated chip based on an on-chip nanoparticle structure is prepared.

Further, referring to fig. 6, the bottom electrode pattern includes device regions 200, the device regions 200 are in the shape of parallel lines which are staggered and arranged with gaps, the gaps between the parallel lines are 80-120um, and referring to fig. 7, the top electrode pattern is in the shape of a transverse line passing over the corresponding device regions. A schematic diagram of the cooperation of the second mask template and the bottom electrode is shown in fig. 8, and the top electrode pattern passes through the upper part of the corresponding device region.

Further, depositing gold nanoparticles on the outer surface of the molecular layer comprises:

the molecules with destructive quantum interference effect and gold nanoparticles are covalently bonded.

In this example, the m-terphenyl or p-terphenyl contains a sulfur anchoring group and the nanoparticle is covalently bonded to the molecule via Au-S. The nano particles are assembled indiscriminately in the whole self-assembled monolayer integrated chip, the lower part passes through the organic glass layer and then contacts with the molecular layer, and the upper part is exposed to the nano particles outside the organic glass layer, so that the function of the device is not affected.

Further, coating PMMA on the upper surface of the silicon substrate to cover the gold nanoparticles, wherein the step of coating PMMA comprises the following steps: defining the vertical distance from the silicon substrate to the top end of the nanoparticle as D, and coating PMMA with the thickness of D+50nm on the upper surface of the silicon substrate;

the etching of PMMA to expose an upper portion of the gold nanoparticles includes: and (3) etching the PMMA with the thickness of 100nm to expose the upper part of the gold nanoparticles.

Further, the method for using the self-assembled monolayer integrated chip comprises the following steps:

grounding the top electrode, applying continuously-changing electrode potential on the bottom electrode, obtaining the conductivity change of the molecular layer device, obtaining a conductivity turning point under the continuously-changing electrode potential, and taking the voltage corresponding to the conductivity turning point as the threshold voltage of the self-assembled monolayer integrated chip;

when a threshold voltage or more is applied to the bottom electrode, conduction is performed between the top electrode and the bottom electrode;

when a voltage equal to or lower than a threshold voltage is applied to the bottom electrode, the top electrode and the bottom electrode are disconnected.

In this embodiment, for example, the threshold voltage of p-terphenyl is 0.5V. The corresponding threshold voltages of the molecular layers of different molecules can be different, and the corresponding threshold voltages can be obtained only by acquiring the conductivity change of the molecular layer device to obtain the conductivity turning points under the continuously changed electrode potential.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms should not be understood as necessarily being directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Claims (9)

1. The self-assembled monolayer integrated chip based on the on-chip nanoparticle structure is characterized in that: the organic silicon oxide semiconductor device comprises a silicon substrate, a silicon oxide insulating layer, an organic glass layer, a bottom electrode, a molecular layer, nano particles and a top electrode;

a silicon dioxide insulating layer grows on the surface of the silicon substrate, and the organic glass layer is laid on the silicon dioxide insulating layer; the bottom electrode is arranged in the organic glass layer and is in contact with the silicon dioxide insulating layer; the molecular layer is arranged between the bottom electrode and the organic glass layer; the lower part of the nano particles passes through the organic glass layer and then contacts with the molecular layer, and the upper part of the nano particles is exposed outside the organic glass layer; the top electrode is disposed on an upper surface of the organic glass layer and is in contact with an upper portion of the nanoparticle.

2. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 1, wherein: the bottom electrode is used as a drain electrode of the self-assembled monolayer integrated chip, the top electrode is used as a source electrode of the self-assembled monolayer integrated chip, and the molecular layer is used as a dielectric layer of the self-assembled monolayer integrated chip.

3. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 2, wherein: the molecular layer contains molecules with destructive quantum interference effects.

4. A self-assembled monolayer integrated chip on the basis of on-chip nanoparticle structures as claimed in claim 2 or 3, characterized in that: the conduction mode is switched into molecular auxiliary tunneling or electron direct tunneling by changing the potential difference between the source electrode and the drain electrode, so that the conductance of the self-assembled monolayer integrated chip is changed, and the connection or disconnection between the source electrode and the drain electrode is controlled.

5. A self-assembled monolayer integrated chip on the basis of on-chip nanoparticle structures as claimed in claim 3, wherein: the self-assembled monolayer integrated chip is prepared by the following method:

cleaning and drying a silicon oxide wafer to obtain a silicon substrate covered with a silicon dioxide insulating layer;

spin-coating photoresist on the upper surface of the silicon dioxide insulating layer and drying;

performing mask photoetching and developing on the photoresist, so as to develop a bottom electrode pattern corresponding to the first mask template on the photoresist;

growing a chromium layer on the area of the upper surface of the silicon dioxide insulating layer, which corresponds to the bottom electrode pattern, by adopting electron beam evaporation, then growing a gold film on the upper surface of the chromium layer by adopting electron beam evaporation, and washing off photoresist to obtain a bottom electrode, which corresponds to the bottom electrode pattern;

immersing the silicon substrate with the bottom electrode in a molecular solution containing destructive quantum interference effects, so that the outer surface of the bottom electrode self-assembles the molecular layer;

dripping gold nanoparticle solution on the molecular layer to enable gold nanoparticles to be deposited on the outer surface of the molecular layer;

coating PMMA on the upper surface of the silicon substrate to cover the gold nanoparticles, and etching the PMMA to expose the upper parts of the gold nanoparticles to prepare the organic glass layer;

and covering the upper surface of the organic glass layer by a second mask template, wherein the second mask template is provided with a top electrode pattern, and growing a gold film on the upper surface of the organic glass layer by adopting electron beam evaporation to obtain the top electrode.

6. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 1, wherein: the bottom electrode pattern includes device regions in the shape of staggered and spaced parallel lines, and the top electrode pattern in the shape of transverse lines passing over the corresponding device regions.

7. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 1, wherein: depositing gold nanoparticles on the outer surface of the molecular layer comprises:

the molecules with destructive quantum interference effect and gold nanoparticles are covalently bonded.

8. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 1, wherein: coating PMMA on the upper surface of the silicon substrate to enable the PMMA to cover the gold nanoparticles comprises the following steps: defining the vertical distance from the silicon substrate to the top end of the nanoparticle as D, and coating PMMA with the thickness of D+50nm on the upper surface of the silicon substrate;

the etching of PMMA to expose an upper portion of the gold nanoparticles includes: and (3) etching the PMMA with the thickness of 100nm to expose the upper part of the gold nanoparticles.

9. The self-assembled monolayer integrated chip on chip nanoparticle structures of claim 1, wherein: the application method of the self-assembled monolayer integrated chip comprises the following steps:

grounding the top electrode, applying continuously-changing electrode potential on the bottom electrode, obtaining the conductivity change of the molecular layer device, obtaining a conductivity turning point under the continuously-changing electrode potential, and taking the voltage corresponding to the conductivity turning point as the threshold voltage of the self-assembled monolayer integrated chip;

when a threshold voltage or more is applied to the bottom electrode, conduction is performed between the top electrode and the bottom electrode;

when a voltage equal to or lower than a threshold voltage is applied to the bottom electrode, the top electrode and the bottom electrode are disconnected.

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