CN116192577A - Parallel time domain frame data equalization system and method for satellite communication - Google Patents

Abstract

The invention provides a equalization system and a method for parallel time domain frame data facing satellite communication, wherein the equalization system is composed of a parallel data filtering module realized based on FPGA, a parallel-serial conversion module and a tap coefficient updating module which are connected with each other, and the equalization method comprises the following steps: the parallel data filtering module acquires parallel time domain frame data of the delay buffer; the parallel-serial conversion module performs parallel-serial conversion on the parallel shift register time domain frame data according to the frame header and the pilot frequency enabling signal; the tap coefficient updating module carries out serial updating on the tap coefficient through single-path shift register frame data; and obtaining the equalization result of the multipath parallel time domain frame data at the current moment. The invention can improve the utilization rate of auxiliary information such as frame header, pilot frequency and the like in the parallel time domain frame data and the convergence speed of the equalization system, reduce steady-state errors after the equalization system converges, and improve the error vector amplitude performance of the parallel time domain frame data after equalization.

Description

Parallel time domain frame data equalization system and method for satellite communication

Technical Field

The invention belongs to the technical field of broadband satellite communication, relates to a time domain frame data equalization system and a time domain frame data equalization method, and in particular relates to a satellite communication-oriented multichannel parallel time domain frame data equalization system based on an FPGA and an MCMA (micro channel memory access) equalization method.

Background

With the development of broadband satellite communication technology, high-throughput satellites (High-throughput Satellite, HTS) have put higher demands on the processing capability of the receiving end of the communication system due to their High rate, high bandwidth and High capacity. In order to meet the requirements of high throughput and high rate communications, in practical satellite communications systems, a transmitting base station located on the ground outputs a series of data to the satellite, which data contains information that all users need to transmit, and is typically transmitted in multiple parallel ways in the time domain in units of frames. The parallel time domain frame data is forwarded through Input multiplexer (Input MultipleXer, IMUX), power amplifier (transmission-Wave TubeAmplifier, TWTA), output multiplexer (Output MultipleXer, OMUX) and other devices, and is transmitted to a receiving base station on the ground for demodulation through a satellite channel. Due to the filter characteristics of IMUX and OMUX, severe inter-symbol interference (Inter Symbol Interference, ISI) is generated in the transmitted parallel time domain frame data, and linear distortion is caused. While TWTA operates near the saturation region, causing nonlinear distortion. Therefore, the filter and the power amplifier in the satellite communication channel can introduce linear distortion and nonlinear distortion, and further distortion and distortion are caused on the transmitted parallel time domain frame data, so that the bit error rate performance of the receiving end is seriously deteriorated.

The equalization technology of the parallel time domain frame data refers to an anti-fading measure adopted for improving the transmission performance in a fading channel of a communication system, and can compensate the characteristics of the channel or the whole transmission system and improve the error vector magnitude (Error Vector Magnitude, EVM) performance of the parallel time domain frame data. The equalization technology of the parallel time domain frame data is divided into a frequency domain equalization technology and a time domain equalization technology, and an equalization system and an equalization method of the parallel time domain frame data based on a time domain constant modulus algorithm are typical time domain equalization methods, for example, wang Aihua et al in 2019, in the book of research and FPGA implementation of high-speed low-complexity parallel blind equalization published in university of Beijing university of technology, a system and a method for equalizing the parallel time domain frame data by adopting a time domain constant modulus (Constant modulus algorithm, CMA) equalization technology and a fast FIR algorithm are provided. The system consists of a delay module, a tap coefficient updating module, an error calculating module and a simplified parallel filtering module, wherein the simplified parallel filtering module adopts a fast Finite Impulse Response (FIR) algorithm, and the complexity and the occupied resource number of parallel filtering are reduced. However, the tap coefficient updating module of the system updates the tap coefficient in parallel by assuming that the product of the error function value and the input data is kept unchanged in parallel M paths, so that the utilization rate of auxiliary information in frame data is reduced, and the convergence speed is lower. In addition, a time domain constant modulus algorithm adopted by a tap coefficient updating module of the system cannot compensate the phase of the parallel time domain frame data after distortion, steady-state error after convergence is larger, and the optimization degree of error vector amplitude performance of the parallel time domain frame data is limited.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, and provides a system and a method for equalizing parallel time domain frame data for satellite communication, which are used for solving the technical problems of low utilization rate of auxiliary information in frame data, slow convergence speed, large steady state error after convergence and the like in the prior art.

In order to achieve the above purpose, the invention adopts the following technical scheme:

an equalization system of multi-channel parallel time domain frame data based on FPGA comprises a parallel data filtering module and a tap coefficient updating module; the parallel data filtering module comprises a parallel shift register, a delay buffer module and a parallel filtering module which are sequentially cascaded, wherein the parallel filtering module comprises M multiplication accumulation modules which are arranged in parallel and have the same number as the input data paths; the output end of the tap coefficient updating module is connected with the input end of the parallel filtering module; a parallel-serial conversion module is loaded between the output end of the parallel shift register and the input end of the tap coefficient updating module; the parallel data filtering module, the tap coefficient updating module and the parallel-serial conversion module are realized based on FPGA, and M is more than or equal to 2.

The tap coefficient updating module in the multi-channel parallel time domain frame data equalization system based on the FPGA comprises a filtering module, an error function calculating module and a tap coefficient iteration module which are sequentially cascaded; a delay unit is also loaded between the input end of the filtering module and the tap coefficient iteration module; the output end of the tap coefficient iteration module is connected with the input end of the filtering module.

An equalization method of a multipath parallel time domain frame data equalization system based on FPGA comprises the following steps:

(1) Initializing parameters:

initializing time domain frame data with distortion in M paths at k time points input through a communication channel as i (k) = { i _m (k) M=1, 2,..m }, i (k) frame header and pilot enable signal en _h (k) = {0,1}, the tap coefficient output by the tap coefficient update module is w (k) = { w _n (k) n=1, 2,.. _m (k) Represents the mth path of time domain frame data, N is the length of w (k), N is more than or equal to M, w _n (k) Represents the nth tap coefficient, and w _n (k) The method meets the following conditions:

representing a downward rounding;

(2) The parallel data filtering module acquires time-delay buffer time domain frame data:

(2a) Parallel shift register in parallel data filtering module for each time domain frame data i _m (k) Shift register processing is carried out, and frame head of input time domain frame data and pilot frequency enable signal en are processed _h (k) Registering to obtain shift register time domain frame data r (k) = { r corresponding to i (k) _m (k) M=1, 2, M and registered frame header and pilot enable signal en _p (k)，r _m (k)＝{r _m,n (k) N=1, 2,.. _m,n (k) Representing the nth time domain frame number of the mth pathAccording to the above, and satisfy:

(2b) Delay buffer module in parallel data filter module registers time domain frame data r for each path of shift _m (k) Performing delay buffer processing to obtain delay buffer time domain frame data d (k):

d(k)＝{d _m (k)|m＝1,2,...,M}

d _m (k)＝{d _m,n (k)|n＝1,2,...,N}

wherein d _m (k) Representing the time-delay buffer time domain frame data of the mth path;

(3) The parallel-serial conversion module performs parallel-serial conversion on the multi-path shift register time domain frame data r (k):

the parallel-serial conversion module is used for converting the frame header and the pilot frequency enabling signal en _p (k) To perform parallel-to-serial conversion on the multi-path shift register time domain frame data r (k) to obtain single-path shift register frame data x (k):

wherein r is _cnt(k) (k) The cnt (k) path comprises N shift registered time domain frame data;

(4) The tap coefficient updating module updates the tap coefficient through the single-path shift register frame data:

(4a) The delay unit delays the single-path shift register data x (k) to obtain delayed data g (k) = { g _n (k)|n＝1,2,...,N}；

(4b) The filtering module filters the single-path shift register frame data x (k) through the conjugate transpose result of the tap coefficient w (k-1) to obtain filtered data y (k);

(4c) The error function calculation module adopts a correction constant modulus algorithm MCMA to calculate an error function value e (k) of the filtered data y (k);

(4d) The tap coefficient iteration module updates the tap coefficient at the current moment through the error function value e (k) and the output shift register frame data g (k) of the delay unit to obtain an updated tap coefficient value w (k);

(5) Obtaining MCMA equalization results of multiple paths of parallel time domain frame data at the moment k:

the parallel filtering module outputs each path of frame data d output by the delay buffer module through output data w (k) of the tap coefficient updating module _m (k) Parallel filtering processing is carried out to obtain k time domain frame data i _m (k) Filtered frame data o _m (k)。

Compared with the prior art, the invention has the following advantages:

in the equalization system, the input parallel time domain frame data is converted into the serial time domain frame data through the parallel-serial conversion module loaded between the output end of the parallel shift register and the input end of the tap coefficient updating module, and the tap coefficient is updated in series through the serial time domain frame data, so that the utilization rate of auxiliary information such as frame heads, pilot frequencies and the like in the frame data and the convergence speed of the equalization system can be improved, and the error vector amplitude performance of the parallel time domain frame data is improved while the steady-state error after convergence is reduced.

Drawings

Fig. 1 is a schematic diagram of the equalization system of the present invention.

Fig. 2 is a flow chart of an implementation of the equalization method of the present invention.

Fig. 3 is a schematic diagram of an implementation of the parallel-to-serial conversion module of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples.

Referring to fig. 1, the equalization system of multi-channel parallel time domain frame data based on the FPGA of the invention is composed of a parallel data filtering module realized based on the FPGA, a parallel-serial conversion module and a tap coefficient updating module which are connected with each other.

The parallel data filtering module comprises a parallel shift register, a delay buffer module and a parallel filtering module which are sequentially cascaded, wherein the parallel filtering module comprises M multiplication accumulation modules which are arranged in parallel and have the same number as that of input data paths, M is more than or equal to 2, and M=4 in the embodiment.

The tap coefficient updating module comprises a filtering module, an error function calculating module and a tap coefficient iteration module which are sequentially cascaded; a delay unit is also loaded between the input end of the filtering module and the tap coefficient iteration module; the output end of the tap coefficient iteration module is connected with the input end of the filtering module.

The parallel-serial conversion module is loaded between the output end of the parallel shift register and the input end of the tap coefficient updating module.

The parallel data filtering module is responsible for caching the input multi-channel parallel time domain frame data, and filtering the cached frame data according to the filter coefficient calculated by the tap coefficient updating module to obtain a multi-channel parallel equalization result. The parallel-serial conversion module converts the multi-channel parallel time domain frame data buffered in the parallel data filtering module into single-channel serial time domain frame data, and inputs the single-channel serial time domain frame data into the tap coefficient module for updating the tap coefficient of the filter.

The tap coefficient updating module carries out serial updating on the tap coefficient through an MCMA (micro channel memory access) balancing algorithm, so that the utilization rate of auxiliary data such as frame heads, pilot frequencies and the like in frame data, the balanced convergence speed and the error vector amplitude performance of the balanced frame data can be improved.

Referring to fig. 2, the MCMA equalization method of the multi-channel parallel time domain frame data equalization system based on the FPGA of the present invention includes the following steps:

step 1) initializing parameters:

initializing 4 paths of time domain frame data with distortion and distortion at k time points input after communication channel as i (k) = { i _m (k) M=1, 2,3,4, frame header of i (k) and pilot enable signal en _h (k) = {0,1}, the tap coefficient output by the tap coefficient update module is w (k) = { w _n (k) N=1, 2,..9 }, where i _m (k) Represents the mth path time domain frame data, w _n (k) Represents the nth tap coefficient:

step 2) the parallel data filtering module obtains time-delay buffer time domain frame data:

(2a) Parallel shift register in parallel data filtering module for each time domain frame data i _m (k) Shift register processing is carried out, and frame head of input time domain frame data and pilot frequency enable signal en are processed _h (k) Registering to obtain shift register time domain frame data r (k) = { r corresponding to i (k) _m (k) M=1, 2,3,4} and registered frame header and pilot enable signal en _p (k)，r _m (k)＝{r _m,n (k) N=1, 2,..9 }, where r _m,n (k) Represents the mth path of time domain frame data, and satisfies:

(2b) Delay buffer module in parallel data filter module registers time domain frame data r for each path of shift _m (k) Performing delay buffer processing, reading out buffered data and sending the buffered data to a parallel filtering module after the tap coefficient is updated for the first time, so that the number of delayed clocks is the number of clocks required by the tap coefficient to be updated once, and the number of clocks required by the tap coefficient to be updated once is 150 to obtain delay buffer time domain frame data d (k):

d(k)＝{d _m (k)|m＝1,2,3,4}

d _m (k)＝{d _m,n (k)|n＝1,2,...,9}

wherein d _m (k) Representing the time-delay buffer time domain frame data of the mth path;

step 3) the parallel-serial conversion module performs parallel-serial conversion on the multi-path shift register time domain frame data r (k):

(3a) The parallel-serial conversion module performs remainder on the time k according to the parallel path number to obtain a remainder cnt (k) of k pairs of parallel path number 4:

where mod represents the remainder operation;

(3b) Referring to fig. 3, the parallel-serial conversion module registers each path of shift register frame data r _m (k) Respectively writing into 4 dual-port RAMs for buffering, and registering frame header and pilot enable signal en through remainder cnt (k) and i (k) in step (3 a) _p (k) Setting the read data enabling signal of the cnt (k) th dual-port RAM to be 1, and further setting the single-path shift register frame data r stored in the cnt (k) th dual-port RAM _cnt(k) (k) Reading out to obtain buffered single-path shift register frame data x (k):

wherein r is _cnt(k) (k) The cnt (k) path comprises 9 time domain frame data of shift registers;

step 4) the tap coefficient updating module updates the tap coefficient through the single-path shift register frame data:

(4a) The delay unit delays the single-way shift register data x (k), and inputs the single-way shift register data into the tap coefficient iteration module after the calculation of the error function calculation module is completed, so that the delayed clock number is the clock number required by obtaining the error function value according to the single-way shift register frame data, and in the embodiment, the clock number required by obtaining the error function value according to the single-way shift register frame data is 30, so as to obtain the output data g (k) = { g of the delay module _n (k)|n＝1,2,...,9}；

(4b) The filtering module filters the single-path shift register frame data x (k) according to the conjugate transpose result of the tap coefficient w (k-1) to obtain filtered data:

y(k)＝x(k)w ^H (k-1)

＝x ₁ (k)w ₁ ^* (k-1)+x ₂ (k)w ₂ ^* (k-1)+...+x _n (k)w _n ^* (k-1)+...+x ₉ (k)w ₉ ^* (k-1)

wherein w is ^H (k-1) represents the conjugate transpose result of the tap coefficient w (k-1), w _n ^* (k-1) represents the nth tap coefficient w _n Co-production of (k-1)A yoke value;

(4c) The error function calculation module adopts a correction constant modulus algorithm MCMA, and compared with the constant modulus algorithm CMA, the correction constant modulus algorithm MCMA not only calculates the distortion degree of the frame data amplitude, but also calculates the distortion degree of the frame data phase. The error function value contains amplitude information and phase information of the frame data, so that steady-state error after equalization convergence can be further reduced. Obtaining an error function value of the filtered data y (k) and the expected data through an error function calculation module:

e(k)＝y _R (k)[|y _R (k)| ² -a _R ² ]+iy _I (k)[|y _I (k)| ² -a _I ² ]

wherein y is _R (k)、y _I (k)、|y _R (k)| ² 、|y _I (k)| ² Respectively representing the real part, the imaginary part and the y of the filtered data _R (k) Square value of y _I (k) Square value of (2); a, a _R ² And a _I ² The square values of the real part and the imaginary part of the expected data are respectively represented, and because the frame header and the pilot frequency of the frame data adopt a QPSK modulation mode in the embodiment, the square values of the real part and the imaginary part of the expected data are both 0.5;

(4d) The tap coefficient iteration module updates the tap coefficient at the current moment through the error function value e (k) and the output shift register frame data g (k) of the delay unit to obtain an updated tap coefficient value:

w(k)＝w(k-1)-λe(k)g ^* (k)

wherein λ represents a step factor, g ^* (k) Representing the conjugation result of shift register data g (k);

step 5) obtaining MCMA equalization results of the multipath parallel time domain data at the k moment:

the parallel filtering module outputs each path of frame data d output by the delay buffer module through output data w (k) of the tap coefficient updating module _m (k) Parallel filtering processing is carried out to obtain k time domain frame data i _m (k) Filtered frame data o _m (k)：

o _m (k)＝d _m (k)·w ^H (k)

＝d _m,1 (k)·w ₁ ^* (k)+d _m,2 (k)·w ₂ ^* (k)+...+d _m,n (k)·w _n ^* (k)+...+d _m,9 (k)·w ₉ ^* (k)

Wherein w is ^H (k) Representing the result of the conjugate transpose of w (k) of the tap coefficient at time k, w _n ^* (k) Represents the nth tap coefficient w at time k _n (k) Is a result of conjugation of (c).

The parallel-serial conversion module in the equalization system converts the buffered multipath parallel time domain frame data into the single-path serial time domain frame data, and carries out serial update on the tap coefficient according to the single-path time domain frame data, so that each frame header and pilot frequency data can be utilized, the utilization rate of auxiliary data such as the frame header, the pilot frequency and the like in the time domain frame data can be further improved, the distortion degree of the parallel time domain frame data can be calculated more accurately, and the steady-state error of the time domain frame data after passing through the equalization system can be reduced. By combining the embodiment, the equalizer can be converged by carrying out iterative update on the tap coefficient for 500 times, the error vector amplitude performance of the parallel time domain frame data is reduced to be within 5%, and the equalized convergence speed and the error vector amplitude performance of the parallel time domain frame data after equalization are greatly improved.

Claims (8)

1. An equalization system of multi-channel parallel time domain frame data based on FPGA comprises a parallel data filtering module and a tap coefficient updating module; the parallel data filtering module comprises a parallel shift register, a delay buffer module and a parallel filtering module which are sequentially cascaded, wherein the parallel filtering module comprises M multiplication accumulation modules which are arranged in parallel and have the same number as the input data paths; the output end of the tap coefficient updating module is connected with the input end of the parallel filtering module; the parallel-serial conversion module is loaded between the output end of the parallel shift register and the input end of the tap coefficient updating module; the parallel data filtering module, the tap coefficient updating module and the parallel-serial conversion module are realized based on an FPGA; wherein M is more than or equal to 2.

2. The equalization system based on FPGA multiple parallel time-domain frame data of claim 1, wherein the tap coefficient updating module comprises a filtering module, an error function calculating module and a tap coefficient iterating module which are sequentially cascaded; a delay unit is also loaded between the input end of the filtering module and the tap coefficient iteration module; the output end of the tap coefficient iteration module is connected with the input end of the filtering module.

3. The equalization method of the equalization system of the multipath parallel time domain frame data based on the FPGA is characterized by comprising the following steps of:

(1) Initializing parameters:

initializing time domain frame data with distortion in M paths at k time points input in parallel through a communication channel as i (k) = { i _m (k) M=1, 2,..m }, i (k) frame header and pilot enable signal en _h (k) = {0,1}, the tap coefficient output by the tap coefficient update module is w (k) = { w _n (k) I n=1, 2,..and N }, where i _m (k) Represents the mth path of time domain frame data, N is the length of w (k), N is more than or equal to M, w _n (k) Represents the nth tap coefficient, and w _n (k) The method meets the following conditions:

representing a downward rounding;

(2) The parallel data filtering module acquires time-delay buffer time domain frame data:

(2a) Parallel shift register in parallel data filtering module for each time domain frame data i _m (k) Shift register processing is carried out, and frame head of input time domain frame data and pilot frequency enable signal en are processed _h (k) Registering to obtain shift register time domain frame data r (k) = { r corresponding to i (k) _m (k) M=1, 2, M and registered frame header and pilot enable signal en _p (k)，r _m (k) Indicating that the mth way contains N shift registersStored time domain frame data, r _m (k)＝{r _m,n (k) N=1, 2,.. _m,n (k) Represents the mth path of time domain frame data, and satisfies:

(2b) Delay buffer module in parallel data filter module registers time domain frame data r for each path of shift _m (k) Performing delay buffer processing to obtain delay buffer time domain frame data d (k):

d(k)＝{d _m (k)|m＝1,2,...,M}

d _m (k)＝{d _m,n (k)|n＝1,2,...,N}

wherein d _m (k) Representing the time-delay buffer time domain frame data of the mth path;

(3) The parallel-serial conversion module performs parallel-serial conversion on the multi-path shift register time domain frame data r (k):

the parallel-to-serial conversion module registers the frame header and the pilot enabling signal en according to the step (2 a) _p (k) To perform parallel-to-serial conversion on the multi-path shift register time domain frame data r (k) to obtain single-path shift register frame data x (k):

wherein r is _cnt(k) (k) The cnt (k) path comprises N shift registered time domain frame data;

(4) The tap coefficient updating module updates the tap coefficient through the single-path shift register frame data:

(4a) The delay unit delays the single-path shift register data x (k) to obtain delayed data g (k) = { g _n (k)|n＝1,2,,N}；

(4b) The filtering module filters the single-path shift register frame data x (k) through the conjugate transpose result of the tap coefficient w (k-1) to obtain filtered data y (k);

(4c) The error function calculation module adopts a correction constant modulus algorithm MCMA to calculate an error function value e (k) of the filtered data y (k);

(4d) The tap coefficient iteration module updates the tap coefficient at the current moment through the error function value e (k) and the output shift register frame data g (k) of the delay unit to obtain an updated tap coefficient value w (k);

(5) Obtaining MCMA equalization results of multiple paths of parallel time domain frame data at the moment k:

the parallel filtering module outputs each path of frame data d output by the delay buffer module through output data w (k) of the tap coefficient updating module _m (k) Parallel filtering processing is carried out to obtain k time domain frame data i _m (k) Filtered frame data o _m (k)。

4. The equalization method of a parallel time domain frame data equalization system as set forth in claim 3, wherein said parallel-to-serial conversion module in step (3) performs parallel-to-serial conversion on shift register time domain frame data, and the implementation steps are as follows:

(3a) The parallel-serial conversion module performs remainder on time k according to the parallel path number M to obtain a remainder cnt (k) of k pairs M:

where mod represents the remainder operation;

(3b) The parallel-serial conversion module registers each path of shift register frame data r _m (k) Respectively writing into M dual-port RAMs for buffering, and registering frame header and pilot enable signal en through remainder cnt (k) of k to M and i (k) in (3 a) _p (k) The stored single-path shift register frame data r of the cnt (k) th dual-port RAM _cnt(k) (k) And reading out to obtain the cached single-path shift register frame data x (k).

5. The equalization method of parallel time domain frame data equalization system as set forth in claim 3, wherein said filtering module in step (4 b) filters the single-path shift register frame data x (k) by a conjugate transpose result of tap coefficients, and a filtering formula is:

y(k)＝x(k)w ^H (k-1)

＝x ₁ (k)w ₁ ^* (k-1)+x ₂ (k)w ₂ ^* (k-1)++x _n (k)w _n ^* (k-1)+...+x _N (k)w _N ^* (k-1)

wherein w is ^H (k-1) represents the conjugate transpose result of the tap coefficient w (k-1), w _n ^* (k-1) represents the nth tap coefficient w _n Conjugate value of (k-1).

6. The equalization method of a parallel time domain frame data equalization system as set forth in claim 3, wherein said error function value e (k) in step (4 c) is calculated by the following formula:

e(k)＝y _R (k)[|y _R (k)| ² -a _R ² ]+i·y _I (k)[|y _I (k)| ² -a _I ² ]

wherein y is _R (k)、y _I (k)、|y _R (k)| ² 、|y _I (k)| ² Respectively representing the real part, the imaginary part and the y of the filtered data _R (k) Square value of y _I (k) Square value of (2); a, a _R ² And a _I ² Representing the square values of the real and imaginary parts of the desired data, respectively.

7. The equalization method of a parallel time domain frame data equalization system of claim 3, wherein said tap coefficient value w (k) in step (4 d) is updated by:

w(k)＝w(k-1)-λe(k)g ^* (k)

wherein λ represents a step factor, g ^* (k) The result of the conjugation of the shift register data g (k) is shown.

8. A method of equalizing a parallel time domain frame data equalizing system according to claim 3, wherein said filtered frame data o in step (5) is each of _m (k) The filter formula is:

o _m (k)＝d _m (k)·w ^H (k)

＝d _m,1 (k)·w ₁ ^* (k)+d _m,2 (k)·w ₂ ^* (k)+...+d _m,n (k)·w _n ^* (k)+...+d _m,N (k)·w _N ^* (k)

wherein w is ^H (k) Representing the result of the conjugate transpose of w (k) of the tap coefficient at time k, w _n ^* (k) Represents the nth tap coefficient w at time k _n (k) Is a result of conjugation of (c).

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