CN116192162A - Method and device for decoding polarization code and nonvolatile computer readable storage medium - Google Patents
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Abstract
The disclosure relates to a decoding method and device of a polarization code and a nonvolatile computer readable storage medium, and relates to the technical field of communication. The decoding method of the polarization code comprises the following steps: continuously eliminating SC decoding and detection judgment by utilizing each decoder to each segment of the code element sequence to be decoded, and outputting each signal component with the maximum occurrence probability; checking the check codes of the signal components respectively, and reserving the signal components passing the check; and performing position replacement on each signal component passing through verification, and determining a decoding result. The technical scheme of the present disclosure can improve decoding efficiency.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method for decoding a polarization code, a device for decoding a polarization code, and a non-volatile computer readable storage medium.
Background
Channel polarization is a phenomenon commonly existing in channel coding, in the first type of channel coding, a channel is invariable in the coding process, and in the second type of channel coding, a channel is an important parameter in the coding process, and the coding result is affected. The polar code belongs to the second class of channel coding. The coding rule of the polarization code and the construction method of the polarization code determine the performance of the polarization code.
The basic idea of polarization coding is that the composite channel exhibits polarization phenomena by coding such that a part of the channel capacity tends to be 1, another part of the channel capacity tends to be 0, and yet another part of the channel capacity is between 1 and 0.
In the related art, a polarization code uses an SC (processing-cncell) decoding algorithm, only a single decoding path is reserved, and when decoding, symbols are continuously and immediately decided and decoded in sequence, and the decoding process is also a deleting process; or using SCL (list successive elimination) decoding algorithm to reserve L alternative paths during decoding; or using parallel SCL (list successive elimination) decoding algorithm, multiple segments are decoded in parallel at decoding time.
Disclosure of Invention
The inventors of the present disclosure found that the above-described related art has the following problems: the amount of calculation is large, the processing time is long, and the decoding efficiency is low.
In view of this, the present disclosure proposes a decoding technical scheme of a polarization code, which can improve decoding efficiency.
According to some embodiments of the present disclosure, there is provided a decoding method of a polarization code, including: continuously eliminating SC decoding and detection judgment by utilizing each decoder to each segment of the code element sequence to be decoded, and outputting each signal component with the maximum occurrence probability; checking the check codes of the signal components respectively, and reserving the signal components passing the check; and performing position replacement on each signal component passing through verification, and determining a decoding result.
In some embodiments, using decoders to perform successive cancellation SC decoding and detection decisions on segments of a symbol sequence to be decoded, respectively, outputting signal components with maximum probability of occurrence includes: in the case where there are a plurality of signal components of the same segment output by the decoders, the signal component in which the probability of occurrence is the largest is retained.
In some embodiments, using decoders to perform successive cancellation SC decoding and detection decisions on segments of a symbol sequence to be decoded, respectively, outputting signal components with maximum probability of occurrence includes: each decoder respectively reserves one of a plurality of alternative paths with the largest occurrence probability as the input of detection decision, and the alternative paths reserved by each decoder are different from each other.
In some embodiments, performing check code check on each signal component, and reserving each signal component passing the check includes: each signal component is checked in parallel using a plurality of decoders.
In some embodiments, performing check code check on each signal component, and reserving each signal component passing the check includes: each signal component is serially checked using a decoder.
In some embodiments, performing check code check on each signal component, and reserving each signal component passing the check includes: and carrying out parallel verification on one part of each signal component, and carrying out serial verification on the other part of each signal component.
According to other embodiments of the present disclosure, there is provided a decoding apparatus of a polarization code, including: the decoding unit is used for respectively carrying out continuous elimination SC decoding and detection judgment on each segment of the code element sequence to be decoded by using each decoder and outputting each signal component with the maximum occurrence probability; the verification unit is used for respectively carrying out verification code verification on each signal component and reserving each signal component passing the verification; and the replacement unit is used for carrying out position replacement on each signal component passing the verification and determining a decoding result.
In some embodiments, the decoding unit retains a signal component in which the probability of occurrence is largest in the case where there are a plurality of decoders outputting signal components of the same segment.
In some embodiments, each decoder of the decoding unit respectively reserves one of a plurality of alternative paths with the largest occurrence probability, and the reserved alternative paths of each decoder are different from each other as the input of the detection decision.
In some embodiments, the verification unit performs parallel verification on each signal component using a plurality of decoders.
In some embodiments, the verification unit performs a serial verification of the signal components using a decoder.
In some embodiments, the verification unit performs a parallel verification of one portion of each signal component and a serial verification of another portion of each signal component.
According to still further embodiments of the present disclosure, there is provided a decoding apparatus of a polarization code, including: a memory; and a processor coupled to the memory, the processor configured to perform the method of decoding the polarization code in any of the embodiments described above based on instructions stored in the memory device.
According to still further embodiments of the present disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of decoding a polarization code in any of the above embodiments.
In the above embodiment, the coupling-joint decision SC decoding of each segment is performed by a plurality of segment coupling-joint decision SC decoders, respectively, thereby improving decoding efficiency.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 illustrates a flow chart of some embodiments of a method of decoding a polar code of the present disclosure;
FIGS. 2a, 2b are schematic diagrams illustrating some embodiments of a method of decoding a polar code of the present disclosure;
FIGS. 3a, 3b are schematic diagrams illustrating further embodiments of methods of decoding a polarization code of the present disclosure;
FIG. 4 illustrates a block diagram of some embodiments of a decoding apparatus of a polar code of the present disclosure;
FIG. 5 illustrates a block diagram of further embodiments of a decoding apparatus of a polar code of the present disclosure;
fig. 6 shows a block diagram of still further embodiments of a decoding apparatus of the polarization code of the present disclosure.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and apparatus should be considered part of the specification.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
As described above, since the decision of the subsequent symbol in the SC decoding algorithm depends on the decision result of the previous symbol, if the decision result of the previous symbol is wrong, the correct decoding path is deleted, and the decision result of the subsequent symbol is wrong, and the error is continuously transferred to the decoding of the subsequent symbol.
The list SC decoding algorithm (SCL) changes the way that the SC only keeps a single decoding path, keeps L alternative paths during decoding, and selects the alternative path with the largest occurrence probability as a decoding result. The alternative paths are enlarged, so that the possibility of deleting the optimal path by mistake is greatly reduced, the decoding performance is remarkably improved, and the decoding complexity is increased by L times. When decoding is performed by the list SC decoding algorithm, a maximum value L of the number of alternative paths is generally set, and when the number of the alternative paths is larger than L, only L alternative paths with the largest occurrence probability are reserved, so that the computational complexity is limited to an acceptable range. The larger the value of L, the better the decoding performance, if l=2k (k is the length of the information bit in the codeword), the maximum likelihood decoding is equivalent, but the decoding performance is the best, but the relation between the decoding performance and L is not linear, and the simulation shows that when L is larger than a certain value, the decoding performance is not obviously improved.
In the CRC (Cyclic Redundancy Check, cyclic redundancy check code) -SCL algorithm, the encoder side performs polarization code encoding with the CRC check code as an information symbol together with a source information symbol and a freeze symbol. At the decoder end, SCL decodes and outputs the code element sequence to be decoded, and then carries out cyclic redundancy check operation; if the code element passes, selecting the alternative code element sequence as a code result; if a plurality of alternative decoding symbol sequences pass the cyclic redundancy check, the alternative decoding symbol sequence with the largest occurrence probability is selected as a decoding result.
Aiming at the technical problem of low CRC-SCL decoding efficiency, the method adopts L segmentation coupling-joint decision SC decoders to respectively execute segmentation coupling-joint decision SC decoding at the decoder end, realizes the parallel CRC-SCL decoding of the respective segments, provides decoding flexibility, improves throughput and reduces decoding time. For example, the technical solution of the present disclosure may be implemented by the following embodiments.
Fig. 1 illustrates a flow chart of some embodiments of a method of decoding a polar code of the present disclosure.
As shown in fig. 1, in step 110, each decoder performs SC decoding and detection decision for each segment of the symbol sequence to be decoded, and outputs each signal component having the highest occurrence probability.
In some embodiments, in the case where there are multiple decoders outputting signal components of the same segment, the signal component in which the probability of occurrence is the greatest is retained.
For example, during segment decoding, each segment respectively reserves L candidate paths with the largest occurrence probability, and L segment coupling-joint decision SC decoders respectively execute segment coupling-joint decision SC decoding.
In some embodiments, each decoder respectively reserves one of a plurality of alternative paths with the largest occurrence probability, and the reserved alternative paths of each decoder are different from each other as the input of detection decision.
For example, L alternative paths with the highest occurrence probability are reserved in the segmented SC decoding code tree, and the alternative paths are identified as: l1, L2, L3, … and LL. The 1 st segment coupling-joint decision SC decoder only keeps the L1 alternative path in the SC decoding process; the 2 nd segment coupling-joint decision SC decoder only reserves an L2 alternative path in the SC decoding process, and so on; the L-th segment coupling-joint decision SC decoder only reserves the LL alternative path in the SC decoding process.
The allocation manner of the segmented coupling-joint decision SC decoder and the alternative path is not unique, and other pairing manners can be adopted.
In step 120, each signal component is checked for a check code, and each signal component passing the check is retained. For example, the check code may be a CRC check code, a parity check code, or other check code.
In some embodiments, after each segment-coupled-joint-decision SC decoder performs a detection decision, the sequence of information symbols in each output signal component is independently checked, the output signal components that passed the check are reserved for output, and the output signal components that did not pass the check are deleted.
For example, after each segment-coupled-joint-decision SC decoder performs detection decisions on the signal components
And->
The information symbol sequence in each signal component of the (a) is independently CRC checked, the output signal component that passed the CRC check is reserved for output, and the output signal component that failed the CRC check is deleted.
The L combined decision SC decoders in the decoder independently perform SC decoding, so that different specific implementation modes can be flexibly adopted. In some embodiments, each signal component is checked in parallel using multiple decoders.
For example, the check code of the L alternative paths may be performed in parallel with the L joint decision SC decoders to assist in SC decoding, which is completed in the shortest time.
In some embodiments, each signal component is serially checked using a decoder.
For example, a joint decision SC decoder may be used to serially perform check code assisted SC decoding of the L alternative paths with minimal hardware resources.
In some embodiments, one portion of each signal component is checked in parallel and another portion of each signal component is checked in series.
For example, the check code assisted SC decoding may also be performed in a serial-parallel hybrid manner to balance hardware resource requirements and decoding time requirements.
In some embodiments, m SC decoders in the joint decision SC decoder perform SC decoding independently, so different specific implementations can be flexibly adopted.
For example, SC decoding may be performed in parallel with m SC decoders, and completed in the shortest time; one SC decoder may be used to serially perform the SC decoding of m segments with minimal hardware resources required; the SC decoding of m segments may also be performed in a serial-parallel hybrid fashion to balance hardware resource requirements and SC decoding time requirements.
In step 130, the position of each verified signal component is permuted to determine the decoding result.
In some embodiments, the signal components output by the L segment-coupled-joint-decision SC decoders are subjected to position substitution as decoding results.
For example, if a plurality of segment-coupled-joint-decision SC decoders output signal components of the same segment at the same time in the L segment-coupled-joint-decision SC decoders, an output signal component in which the probability of occurrence is the largest is selected as a decoding result; if the output signal component of any segment is deleted by the L segment coupling-joint decision SC decoder in the decoding process due to failing verification, the decoding fails.
In the above embodiment, the L segmentation coupling-joint decision SC decoders respectively execute segmentation coupling-joint decision SC decoding, so as to improve decoding performance; the CRC check is independently carried out on the information code element sequence in each output signal component in the segmented coupling-combined decision SC decoder, so that parallel decoding can be carried out, and the decoding time is short; the parallel, serial and serial-parallel mixed decoding can be realized, the realization mode is flexible, and the requirements of different application scenes can be met.
Fig. 2a, 2b illustrate schematic diagrams of some embodiments of the decoding method of the polarization code of the present disclosure.
As shown in fig. 2a and 2b, during the segment decoding, each segment respectively reserves L alternative paths with the largest occurrence probability, and the L segment coupling-joint decision SC decoders respectively execute the segment coupling-joint decision SC decoding.
After each segment coupling-joint decision SC decoder executes detection decision, the information code element sequence in each output signal component is independently checked by check codes, the output signal component passing the check is reserved for output, and the output signal component not passing the check is deleted. And the signal components output by the L segmentation coupling-joint decision SC decoders are subjected to position substitution to be used as decoding results. If a plurality of segmentation coupling-joint decision SC decoders output the output signal component of the same segment at the same time in the L segmentation coupling-joint decision SC decoders, selecting the output signal component with the largest occurrence probability as a decoding result; if the output signal component of any segment is deleted by the L segment coupling-joint decision SC decoder in the decoding process due to failing verification, the decoding fails.
For example, the check code may be a CRC check code, a parity check code, or other check code.
Fig. 3a, 3b are schematic diagrams illustrating further embodiments of the decoding method of the polarization code of the present disclosure.
As shown in fig. 3a, 3b, the segment-coupled-joint-decision SC decoding is performed by L segment-coupled-joint-decision SC decoders.
L alternative paths with the largest occurrence probability are reserved in the segmented SC decoding code tree, and the alternative paths are marked from left to right as follows: l1, L2, L3, … and LL. The 1 st segment coupling-joint decision SC decoder only keeps the L1 alternative path in the SC decoding process; the 2 nd segment coupling-joint decision SC decoder only reserves an L2 alternative path in the SC decoding process, and so on; the L-th segment coupling-joint decision SC decoder only reserves the LL alternative path in the SC decoding process. The allocation manner of the segmented coupling-joint decision SC decoder and the alternative path is not unique, and other pairing manners can be adopted.
After each segment-coupled-joint-decision SC decoder performs detection decision, the signal component is processed
And->
The information symbol sequence in each signal component of the (a) is independently CRC checked, the output signal component that passed the CRC check is reserved for output, and the output signal component that failed the CRC check is deleted. And the signal components output by the L segmentation coupling-joint decision SC decoders are subjected to position substitution to be used as decoding results. If a plurality of sectional coupling-joint decision SC decoders output the same output signal component, selecting the output signal component with the largest occurrence probability as a decoding result; if the output signal component of any segment is deleted by the L segment coupling-joint decision SC decoder in the decoding process due to failing verification, the decoding fails.
The L combined decision SC decoders in the decoder independently perform SC decoding, so that different specific implementation modes can be flexibly adopted. For example, the check code of the L alternative paths can be executed in parallel by using L joint decision SC decoders to assist SC decoding, and decoding is completed in the shortest time; a joint decision SC decoder can also be adopted to serially execute the check codes of L alternative paths to assist SC decoding, and the required hardware resources are minimum; the check code can also be used for assisting SC decoding in a serial-parallel hybrid mode so as to balance the hardware resource requirement and the decoding time requirement.
The m SC decoders in the joint decision SC decoder independently perform SC decoding, so that different specific implementation manners can be flexibly adopted.
Similarly, the SC decoding can be performed in parallel with m SC decoders, and completed in the shortest time; one SC decoder may be used to serially perform the SC decoding of m segments with minimal hardware resources required; the SC decoding of m segments may also be performed in a serial-parallel hybrid fashion to balance hardware resource requirements and SC decoding time requirements.
Fig. 4 illustrates a block diagram of some embodiments of a decoding apparatus of a polar code of the present disclosure.
As shown in fig. 4, the decoding device 4 for the polarization code includes: a decoding unit 41, configured to perform SC decoding and detection decision elimination successively on each segment of the symbol sequence to be decoded by using each decoder, and output each signal component with the largest occurrence probability; a checking unit 42, configured to check the check codes of the signal components, and reserve the signal components passing the check; and a permutation unit 43 for performing position permutation on each signal component passing the verification to determine a decoding result.
In some embodiments, decoding unit 41 retains the signal component in which the probability of occurrence is greatest in the case where there are multiple decoder outputs of the same segment of signal component.
In some embodiments, the decoding unit 41 respectively reserves one of a plurality of alternative paths with the largest occurrence probability for each decoder, and the reserved alternative paths of each decoder are different from each other as the input of the detection decision.
In some embodiments, the verification unit 42 performs parallel verification on each signal component using multiple decoders.
In some embodiments, the verification unit 42 performs a serial verification of the signal components using a decoder.
In some embodiments, the verification unit 42 performs a parallel verification of one portion of each signal component and a serial verification of another portion of each signal component.
Fig. 5 shows a block diagram of further embodiments of a decoding apparatus of the polarization code of the present disclosure.
As shown in fig. 5, the decoding device 5 of the polarization code of this embodiment includes: a memory 51 and a processor 52 coupled to the memory 51, the processor 52 being configured to perform the method of decoding a polarization code in any one of the embodiments of the present disclosure based on instructions stored in the memory 51.
The memory 51 may include, for example, a system memory, a fixed nonvolatile storage medium, and the like. The system memory stores, for example, an operating system, application programs, boot Loader, database, and other programs.
Fig. 6 shows a block diagram of still further embodiments of a decoding apparatus of the polarization code of the present disclosure.
As shown in fig. 6, the decoding device 6 of the polarization code of this embodiment includes: a memory 610 and a processor 620 coupled to the memory 610, the processor 620 being configured to perform the method of decoding a polar code in any of the foregoing embodiments based on instructions stored in the memory 610.
The memory 610 may include, for example, system memory, fixed nonvolatile storage media, and the like. The system memory stores, for example, an operating system, application programs, boot Loader, and other programs.
The decoding device 6 of the polarization code may further include an input/output interface 630, a network interface 640, a storage interface 650, and the like. These interfaces 630, 640, 650 and the memory 610 and processor 620 may be connected by, for example, a bus 660. The input/output interface 630 provides a connection interface for input/output devices such as a display, a mouse, a keyboard, a touch screen, a microphone, and a speaker. Network interface 640 provides a connection interface for various networking devices. The storage interface 650 provides a connection interface for external storage devices such as SD cards, U-discs, and the like.
It will be appreciated by those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable non-transitory storage media including, but not limited to, disk storage, CD-ROM, optical storage, and the like, having computer-usable program code embodied therein.
Heretofore, a decoding method of a polarization code, a decoding apparatus of a polarization code, and a non-volatile computer-readable storage medium according to the present disclosure have been described in detail. In order to avoid obscuring the concepts of the present disclosure, some details known in the art are not described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.
The methods and systems of the present disclosure may be implemented in a number of ways. For example, the methods and systems of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (14)
1. A method of decoding a polarization code, comprising:
continuously eliminating SC decoding and detection judgment by utilizing each decoder to each segment of the code element sequence to be decoded, and outputting each signal component with the maximum occurrence probability;
checking the check codes of the signal components respectively, and reserving the signal components passing the check;
and performing position replacement on the signal components passing through the verification to determine a decoding result.
2. The decoding method as claimed in claim 1, wherein the sequentially removing SC decoding and detecting decisions are performed on each segment of the symbol sequence to be decoded by each decoder, respectively, and outputting each signal component having the largest occurrence probability comprises:
in the case where there are a plurality of signal components of the same segment output by the decoders, the signal component in which the probability of occurrence is the largest is retained.
3. The decoding method as claimed in claim 1, wherein the sequentially removing SC decoding and detecting decisions are performed on each segment of the symbol sequence to be decoded by each decoder, respectively, and outputting each signal component having the largest occurrence probability comprises:
each decoder respectively reserves one of a plurality of alternative paths with the largest occurrence probability as the input of detection decision, and the reserved alternative paths of each decoder are different from each other.
4. A decoding method according to any one of claims 1-3, wherein said separately performing a check code check on said signal components, retaining each signal component that passes the check comprises:
and carrying out parallel verification on each signal component by utilizing a plurality of decoders.
5. A decoding method according to any one of claims 1-3, wherein said separately performing a check code check on said signal components, retaining each signal component that passes the check comprises:
and carrying out serial verification on each signal component by using a decoder.
6. A decoding method according to any one of claims 1-3, wherein said separately performing a check code check on said signal components, retaining each signal component that passes the check comprises:
and carrying out parallel verification on one part of each signal component, and carrying out serial verification on the other part of each signal component.
7. A decoding apparatus of a polarization code, comprising:
the decoding unit is used for respectively carrying out continuous elimination SC decoding and detection judgment on each segment of the code element sequence to be decoded by using each decoder and outputting each signal component with the maximum occurrence probability;
the verification unit is used for respectively carrying out verification code verification on each signal component and reserving each signal component passing the verification;
and the replacement unit is used for carrying out position replacement on the signal components passing through the verification and determining a decoding result.
8. The decoding device according to claim 7, wherein,
the decoding unit retains a signal component in which the probability of occurrence is the largest in the case where there are a plurality of decoders outputting signal components of the same segment.
9. The decoding device according to claim 7, wherein,
and each decoder of the decoding unit respectively reserves one of a plurality of alternative paths with the largest occurrence probability as the input of detection decision, and the reserved alternative paths of each decoder are different from each other.
10. The decoding apparatus according to any one of claims 7 to 9, wherein,
the verification unit performs parallel verification on each signal component by using a plurality of decoders.
11. The decoding apparatus according to any one of claims 7 to 9, wherein,
the verification unit performs serial verification on the signal components by using a decoder.
12. The decoding apparatus according to any one of claims 7 to 9, wherein,
the verification unit performs parallel verification on one part of each signal component and serial verification on the other part of each signal component.
13. A decoding apparatus of a polarization code, comprising:
a memory; and
a processor coupled to the memory, the processor configured to perform the method of decoding a polarization code of any one of claims 1-6 based on instructions stored in the memory.
14. A non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of decoding a polarization code according to any of claims 1 to 6.
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