CN116189741A - Erasing method and device of non-volatile memory - Google Patents

Abstract

The invention discloses an erasing method of a non-volatile memory, which comprises the following steps of: step 11, performing an erase operation on a selected erase block in the blocks of the nonvolatile memory device. And step 12, performing an erasure verification operation. In the step of erasing at least one time, after the completion of the step 11 and before the step 12, the method further comprises: step 13, performing a first over-erase operation to make the low boundary point of the threshold voltage distribution of the selected erase block greater than or equal to a first lower limit value; the first lower limit value ensures that the low boundary point of the threshold voltage distribution is greater than or equal to the second lower limit value after the erase operation of step 11 is completed in the next erase cycle step, and the second lower limit value ensures that the non-selected erase blocks located in the same block will not generate a read failure. The invention also provides an erasing device of the nonvolatile memory. The invention can ensure that read data errors of the non-erased area of the same block can be avoided after restarting when abnormal interruption or power failure occurs in the erasing process.

Description

Erasing method and device of non-volatile memory

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a method for erasing a nonvolatile memory. The invention also relates to an erasing device of the nonvolatile memory.

Background

For Floating Gate (FG) Flash memory, since charge is stored in the Floating gate, the threshold voltage (Vt) of the memory cell (cell) is high when there is more charge in the Floating gate; when there is less charge in the floating gate, the threshold voltage of the memory cell is low. This can distinguish whether a "0" or a "1" is stored according to how much charge is stored. Is generally defined as: during programming (Program), charges are attracted to the floating gate, more charges exist in the floating gate, the threshold voltage of a memory cell is high, and stored data is 0; in contrast, during erase, charge is attracted to the floating gate, there is less charge in the floating gate, the threshold voltage of the memory cell is low, and the stored data is "1".

Because of the presence of the floating gate, the voltage on the Word Line (WL) and the voltage on the Bit Line (BL) on a memory cell both have an effect on the floating gate, and the final voltage on the floating gate is determined by both the word line and bit line voltages. In a read operation, a word line read Voltage (VREAD) such as 5V is applied to the word line of the cell to be read, a bit line read Voltage (VRBL) such as 1V is applied to the bit line, and a select Voltage (VDSEL) such as 0V is applied to the unselected word lines of the cell, but due to the shrink characteristics of the memory cells, the word lines of some cells in the row direction are shared, the bit lines of other cells in the column direction are shared, and when more cell bit lines are shared, the bit line voltage also contributes to the floating gate, and when the memory cell is over-erased or the charge in the floating gate is too low, the unselected cells are turned on slightly, contributing to additional leakage current. When reading "0", this leakage current may change the read "0" to the read "1".

Therefore, in the erase flow of floating gate flash memory, over-erase correction (over erase correction, OEC) is required to correct this over-erase phenomenon, so that a certain amount of charge is maintained on the floating gate of the erased memory cell to prevent the information of the memory cell that is not erased and programmed from being misread.

However, in some applications, if the memory device in which the memory cell being erased is located is suddenly powered off or suddenly interrupted, the OEC method cannot be performed, and the next time the non-erased area is re-enabled for reading, the "0" memory cell may have a false reading condition, resulting in a chip failure.

In the prior art, over-erasure detection is generally performed during power-up, and when the leakage current on a certain bit line exceeds a certain standard, over-erasure correction operation is performed on the storage on the whole bit line. But this approach brings new problems:

1. if the capacity of the chip is large, the over-erasure of which memory block exists is not known when the chip is powered on, so that the over-erasure search of the whole chip needs to consume more time, and the overlong time has a certain influence on customer experience and application;

2. the voltage may not reach the minimum operable power supply voltage specified in the specification during power-up, and at this time, certain errors are brought to the reading verification or over-erasing repair, and particularly certain influence is brought to the read data after certain erasing times.

The following describes the over-erase generated read failure phenomenon in the existing erase method as follows:

FIG. 1 is a schematic diagram of a memory block of a conventional nonvolatile memory; the memory block is simply referred to as block 100, and block 100 includes a plurality of erase blocks 101. N erase blocks 101 are shown in FIG. 1 and are labeled with numbers 0, 1 through n-1, respectively; each erase block 101 is formed on the same P-type semiconductor substrate 102. Each erase block 101 is provided with a word line drive circuit 103, the word line drive circuit 103 providing a drive signal for each word line 104 in the erase block 101. Each erase block 101 of the entire block 100 includes aligned columns of memory cells, the same column of memory cells sharing a common bit line 105, indicated by BL in fig. 1, and j bit lines, numbered 0, 1 through j-1, respectively.

As shown in fig. 1, when an erase operation is performed on one of the erased blocks 101, if there is an over-erase phenomenon, the read operation on other unerased blocks 101 in the same block 100 will be affected, and a serious over-erase will cause a read failure phenomenon. This is because, when reading the memory cells in the unerased block 101, since the over-erased memory cells in the erased block are also located on the same bit line 105, the potential of the bit line 105 changes due to the leakage of the over-erased memory cells, thereby disabling the reading of the memory cells in the unerased block 101.

FIG. 2 is a flow chart showing an erasing method of a conventional nonvolatile memory; the conventional erasing method of the nonvolatile memory comprises the following steps:

step S101, the erase command is started to be accepted.

Step S102, performing erasure initialization, namely chip internal initialization, and setting all erasing block addresses to be clear.

Step S103, performing erase block pre-verification and pre-programming operation. Pre-programming, like programming, also writes charge into the floating gate, ensures that the threshold voltage of the erased block memory cells is in a higher state before erasing.

Step S104, erasing the erasing block. The pre-programming is completed and the erase operation is started, i.e., the erase operation is performed on the selected erase block.

Step S105, performing erase block erase verification, that is, performing erase verification on the erase block after each erase is completed.

Step S106, determining the result of the erase verification, that is, determining whether "the erase passes? ".

If the judgment result in the step S106 is no, then:

step S107, determining whether the maximum number of erasures is reached, i.e. "reach the maximum number of erasures? ". If the determination result is no, that is, the maximum number of times is not reached, the flow goes to step S104.

If the judgment result of step S106 is yes or the judgment result of step S107 is yes, the subsequent step S108 is performed.

As can be seen from the above, the process in the dashed box 201 corresponds to the whole erasing process step, which includes more than one erasing loop step, and the erasing loop step is composed of steps S104 to S107. Therefore, if the erase verification is successful within a defined number of times, the erase is no longer performed; if the number of times exceeds the limit, the erase verification is unsuccessful, and the erase operation is not performed any more.

Step S108, performing an over-erase operation for ending the erase block erase, that is, after completing the flow of the dashed box 201, indicating that the erase process of the erase block is ended, and then performing an over-erase operation for correcting the over-erase generated during the erase process. Over-erase operations include over-erase verification, which detects whether over-erase exists, and over-erase programming; over-erase programming programs the floating gate to charge the floating gate with a certain charge, so that the threshold voltage of the memory cell changes.

After that, step S109, other operations, that is, when the erase block erase is ended and the over erase operation is ended, are performed, and other operations such as an anti-tamper repair operation and the like are performed. And (5) ending other operations, and ending the whole erasing process, namely, ending the erasing of the erasing block in the step S110.

FIG. 3 is a graph showing the distribution of threshold voltages of memory cells during an erase process of the erase method of the conventional nonvolatile memory shown in FIG. 2; in fig. 3:

PV represents a program verify boundary point, that is, when the threshold voltage is less than PV, the program fails, and when the threshold voltage is greater than or equal to PV, the program verification passes.

EV represents a boundary point of erase verification (erase), that is, erase failure when the threshold voltage is greater than EV and erase verification passes when the threshold voltage is less than or equal to EV;

RD represents the read voltage, i.e., the word line voltage operating point at read (read).

B1 represents a boundary point where over-erasure needs to be repaired, that is, when over-erasure exists, it is necessary to repair all threshold voltages to B1 or more.

Curve 301 is the memory cell threshold distribution at the end of the pre-programming of step S103, as can be seen by the larger threshold voltage.

Curve 302 is the threshold distribution of memory cells after successful erase, where the high boundary point of the threshold voltage of the memory cells is the EV point, which is guaranteed by erase verification.

However, the threshold voltage of the memory cell of the curve 302 has a low boundary point exceeding B1, i.e., B1 or less, and this boundary point B1 is the boundary point that needs to be repaired for final over-erase, and may exceed a lot, if the over-erase operation is not performed, the read failure occurs when the read operation is performed on the erased area of the same block as the erased area.

Curve 303 is the threshold distribution of the memory cells after the over-erase operation is completed in step S108 after the over-erase operation is completed in the completion of the erase block erase operation, and at this time, the threshold voltage low boundary point of the memory cells reaches or exceeds B1, so that no interference is caused to the non-erased area of the block after the completion of step S108.

However, if a power loss occurs before step S108 is completed, the threshold voltage distribution curve of the memory cell will remain as curve 302, at which time a restart will produce a read failure.

As shown in fig. 4, the erase method of the conventional nonvolatile memory shown in fig. 2 is adopted to perform the read current curve of the memory cells in the same block after the abnormal power-down restart in the erase process; in fig. 4:

the read voltage is RD;

curve 401 is the current curve of the reference memory cell;

curve 403 is the current curve for a memory cell storing a "1";

curve 402 is the current curve for a memory cell storing a "0".

In the case where the normal Word Line (Word Line) is in RD, there is a margin between the memory cells "1" and "0" from the reference memory cell, and it is easier to distinguish between "0" and "1". However, if over-erase occurs, a normal leakage current is generated in "0" cell, which is the leakage current generated by over-erased cells in the same block 100 and read cells in different erase blocks 101 in fig. 1, that is, the threshold voltage is smaller than that of B1, which causes curve 402 to deviate from curve 404, and the actual read cell current (Icell) is the current of curve 404, it can be seen that, at RD, curve 404 is located above curve 401, indicating that the read data is "1", which is the contrary to the actual stored data, that is, the read failure occurs.

Disclosure of Invention

The invention aims to solve the technical problem of providing an erasing method of a non-volatile memory, which can ensure that read data errors of a non-erased area of the same block can be avoided after restarting when abnormal interruption or power failure occurs in the erasing process. Therefore, the invention also provides an erasing device of the nonvolatile memory.

In order to solve the above technical problems, the erasing process steps in the erasing method of the nonvolatile memory provided by the invention comprise more than one erasing cycle step, wherein the erasing cycle step comprises the following steps:

step 11, performing an erase operation on a selected erase block in the blocks of the nonvolatile memory device.

Step 12, performing an erase verification operation on the selected erase block.

In the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure.

A further improvement is that before the step of the erasing process, the method further comprises:

step one, pre-verifying and pre-programming the selected erase block.

Further improvement is that in the step of the erasing process, if the result of the erasing verification operation in the step 12 is passing or the number of times of the erasing cycle step reaches the maximum number of times, the step of the erasing process is ended;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

Further improvement is that after the step of the erasing process is finished, the method further comprises:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value.

In a further improvement, in step 12, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is less than or equal to the set first upper limit value, the result of the erase verification operation is passing; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit.

A further improvement is that in the step of the erasing process, step 13 is inserted every time in the step of the erasing cycle;

or, step 13 is inserted once after every n times of step 11, n is greater than or equal to 2;

or after completing n times of the erasing loop steps, inserting a step 13 in each subsequent erasing loop step, wherein n is greater than 1;

or after completing n times of the erasing loop steps, inserting a step 13 once after every k times of the step 11 in the subsequent loops, wherein n is greater than 1, k is greater than or equal to 1, and k is a fixed value or an indefinite value.

In a further improvement, in step 13, the first over-erase operation includes:

performing a first over-erase verification for detecting a low boundary point of a threshold voltage distribution of the selected erase block;

and performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter.

A further improvement is that said first over-erase parameters include over-erase voltage and over-erase time and erase voltage and erase time of said erase operation in step 11 of the next said erase cycle step; the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step are set according to the difference between the second lower limit value and the first lower limit value.

In order to solve the above technical problems, the erasing device of a nonvolatile memory provided by the present invention includes: and a flow control module.

The flow control module controls the step of the erasing process;

the erasing process step includes an erasing loop step including:

step 11, performing an erase operation on a selected erase block in the blocks of the nonvolatile memory device.

Step 12, performing an erase verification operation on the selected erase block.

In the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure.

In a further improvement, the flow control module further realizes the following control:

before the erasing process step, further comprising:

step one, pre-verifying and pre-programming the selected erase block.

Further improvement is that in the step of the erasing process, if the result of the erasing verification operation in the step 12 is passing or the number of times of the erasing cycle step reaches the maximum number of times, the step of the erasing process is ended;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

In a further improvement, the flow control module further realizes the following control:

after the erasing process is finished, the method further comprises the following steps:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value.

In a further improvement, in step 12, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is less than or equal to the set first upper limit value, the result of the erase verification operation is passing; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit.

A further improvement is that in the step of the erasing process, step 13 is inserted every time in the step of the erasing cycle;

or, step 13 is inserted once after every n times of step 11, n is greater than or equal to 2;

or after completing n times of the erasing loop steps, inserting a step 13 in each subsequent erasing loop step, wherein n is greater than 1;

or after completing n times of the erasing loop steps, inserting a step 13 once after every k times of the step 11 in the subsequent loops, wherein n is greater than 1, k is greater than or equal to 1, and k is a fixed value or an indefinite value.

In a further improvement, in step 13, the first over-erase operation includes:

performing a first over-erase verification for detecting a low boundary point of a threshold voltage distribution of the selected erase block;

performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter;

the erasing device further includes:

the detection module is used for realizing the first over-erasure verification;

and the repair module is used for realizing the first over-erase programming.

A further improvement is that said first over-erase parameters include over-erase voltage and over-erase time and erase voltage and erase time of said erase operation in step 11 of the next said erase cycle step; setting an erase voltage and an erase time of the erase operation in step 11 of the next erase cycle step according to a difference between the second lower limit value and the first lower limit value;

The erasing device further comprises a voltage control module, wherein the voltage control module receives the first over-erasing parameter and provides voltage to the corresponding memory cell according to the first over-erasing parameter.

Unlike the prior art in which the threshold voltage distribution of the selected erase block is adjusted by performing the over-erase operation after the erase process step is completed, the over-erase operation, i.e., the first over-erase operation, is inserted in more than one erase cycle step of the erase process step, so that the first over-erase operation can adjust the threshold voltage distribution of the selected erase block in the erase process step, and the threshold voltage distribution of the selected erase block can be equal to or greater than the second lower limit value after the erase operation of step 11 is completed, and since the second lower limit value is set to ensure that the non-selected erase block located in the same block will not generate a read failure, even if an abnormal interruption or power failure occurs in the erase process, each memory cell in the selected erase block can be ensured not to be in an over-erase state, but to be in an erase state with the threshold voltage being equal to or greater than the second lower limit value; after restarting, the storage state of each storage unit in the selected erase block will be maintained in an abnormal interruption or power-off state, so that no electric leakage occurs when the storage unit of the selected erase block is in an over-erased state and thus the storage units of the non-selected erase block in the same block generate reading errors after restarting, and the invention can ensure that the reading errors of the non-erased area of the same block can be avoided after restarting when the abnormal interruption or power-off occurs in the erasing process.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a schematic diagram of a memory block of a conventional nonvolatile memory;

FIG. 2 is a flow chart of an erase method of a conventional nonvolatile memory;

FIG. 3 is a graph showing a threshold voltage distribution of memory cells during an erase process of the erase method of the conventional nonvolatile memory shown in FIG. 2;

FIG. 4 is a graph of the read current of memory cells in the same block after an abnormal power-down restart in an erase process using the erase method of the conventional nonvolatile memory shown in FIG. 2;

FIG. 5 is a flowchart of an erasing method of a nonvolatile memory according to an embodiment of the invention;

FIG. 5A is a flowchart of a method for erasing a nonvolatile memory according to a preferred embodiment of the present invention;

FIG. 6 is a diagram showing a threshold voltage distribution of memory cells during an erase process of an erase method of a nonvolatile memory according to an embodiment of the present invention;

FIG. 7 is a graph showing the read current of memory cells in the same block after an abnormal power-down restart in the erasing process according to the erasing method of the nonvolatile memory of the embodiment of the invention;

FIG. 8 is a schematic diagram of an erasing apparatus of a nonvolatile memory according to an embodiment of the invention.

Detailed Description

FIG. 5 is a flowchart of a method for erasing a nonvolatile memory according to an embodiment of the invention; FIG. 5A is a flowchart showing an erasing method of the nonvolatile memory according to the preferred embodiment of the invention; FIG. 6 is a graph showing a threshold voltage distribution of memory cells during an erase process of an erase method of a nonvolatile memory according to an embodiment of the present invention; the erasing process step in the erasing method of the nonvolatile memory of the embodiment of the invention comprises more than one erasing cycle step,

before the erasing process step, further comprising:

step one, pre-verifying and pre-programming the selected erase block.

In some preferred embodiments, as shown in FIG. 5A, step one corresponds to step S203, erase block pre-verify and program. Pre-programming, like programming, also writes charge into the floating gate, ensures that the threshold voltage of the erased block memory cells is in a higher state before erasing.

The method further comprises the following steps:

step S201, the erase command is started to be accepted.

Step S202, performing erasure initialization, namely chip internal initialization, and setting all erasing block addresses to be clear.

In fig. 6, curve 601 is a threshold voltage distribution curve of the selected erase block after the pre-programming, where each memory cell of the selected erase block is in a higher programmed state, and a portion of the threshold voltages are less than PV, where PV represents a boundary point of program verification, but because of the pre-programming, it is not necessary to ensure that the threshold voltages of each memory cell of the pre-programming are all greater than or equal to PV.

In the embodiment of the present invention, the erasing cycle step is a second step, including:

step 11, performing an erase operation on a selected erase block in the blocks of the nonvolatile memory device.

Step 12, performing an erase verification operation on the selected erase block. In step 12, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is smaller than or equal to the set first upper limit value, the result of the erase verification operation is that the selected erase block passes; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit. In fig. 6, the first upper limit value corresponds to EV, which represents a boundary point of erase verification.

In the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure. In fig. 6, the first lower limit value is B1A, and the second lower limit value is B1B.

In the embodiment of the present invention, in step 13, the first over-erase operation includes:

a first over-erase detection is performed for detecting a low boundary point of a threshold voltage distribution of the selected erase block. As shown in fig. 6, curve 602 is a threshold voltage distribution curve of memory cells of the selected erase block after the erase operation of step 11 is completed, it can be seen that a low boundary point of curve 602 is greater than or equal to B1B and a low boundary point of curve 602 is less than B1A. The low boundary point of curve 602 being greater than or equal to B1B ensures that no read failure occurs after restart even when a power outage occurs at this time. The low boundary point of curve 602 being less than B1A indicates that the low boundary point of curve 602 of the first over-erase detection is still somewhat low, requiring subsequent adjustments to raise the low boundary point above B1A.

And performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter. Curve 603 is a threshold voltage distribution curve for the selected erase block after the first over-erase operation of step 13 is completed, and it can be seen that the low boundary point in curve 603 is raised to B1A or more. In some embodiments, the first over-erase parameters include an over-erase voltage and an over-erase time, and an erase voltage and an erase time for the erase operation in step 11 of the next erase cycle step; the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step are set according to the difference between the second lower limit value and the first lower limit value. As can be seen from the above, the arrangement of B1B and B1A in the embodiment of the present invention can ensure that the lower boundary point of the threshold voltage distribution is located above B1B after the completion of the subsequent step 11 after the over-erase operation in step 13.

In the embodiment of the present invention, in the step of the erasing process, if the result of the erase verification operation in step 12 is that the number of cycles of the erase cycle step reaches the maximum number, the step of the erasing process is ended.

If the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

In fig. 5, step 13 is represented by a node inserted between step 11 and step 12, which means that in embodiments of the present invention, step 13 may be inserted in some of the erase cycle steps, and step 13 may not be inserted in other of the erase cycle steps, and may be selected according to actual needs. The insertion control of the step 13 includes:

in some embodiments, step 13 is inserted in each of the erase cycle steps.

In some embodiments, step 13 is inserted once every n times after step 11, n being greater than or equal to 2.

In some embodiments, after completing n of the erase cycle steps, step 13 is inserted for each subsequent erase cycle step, where n is greater than 1.

In some embodiments, after completing n of the erase cycle steps, step 13 is inserted once every k of the subsequent cycles after step 11, n is greater than 1, k is greater than or equal to 1, and k is a fixed or indefinite value.

In some preferred embodiments:

as shown in fig. 5A, step 11 corresponds to step S204 in fig. 5A, and erase block erase is performed. The erase operation is started after the end of the pre-programming, i.e., the erase operation is performed on the selected erase block.

Step 13 corresponds to step S205 of fig. 5A, and the over-erase operation of the erase block erase process is the first over-erase operation, which means that the over-erase operation performed during the erase block erase process is different from the time point at which the over-erase operation performed after the end of the erase block erase process is performed, that is, the second over-erase operation.

Step 12 corresponds to step S206 in fig. 5A, erase block erase verification is performed, that is, erase verification is performed on the erase block after each erase is completed.

As can be seen from FIG. 6, the erase block erase verification in step 12 is primarily for comparing the high boundary point of the threshold voltage distribution of the selected erase block with EV, which represents the boundary point of erase verification, if the high boundary point is greater than EV, then verification is failed; and if the high boundary point is less than or equal to EV, the verification is passed.

And the first over-erase operation in step 13 is used to compare the low boundary point of the threshold voltage distribution of the selected erase block with B1A, and if less than B1A, adjust the low boundary point of the threshold voltage distribution of the selected erase block to be greater than or equal to B1A; this ensures that the threshold voltage distribution of the selected erase block is at least B1B after the next erase operation of step 11, so that even if the power-down restart is performed after the erase operation of step 11, the threshold voltage distribution of the selected erase block is maintained at least B1B, so that no read failure occurs.

In fig. 5A, step S206 further includes:

step S207, determining the result of the erase verification, i.e. determining whether "erase pass? ".

If the determination result in step S207 is no, that is, if the high boundary point of the threshold voltage distribution of the selected erase block is greater than EV, then:

step S208, determining whether the maximum number of erasures is reached, i.e. "reach the maximum number of erasures? ". If the determination result is no, i.e. the maximum number of times is not reached, the process goes to step S204, and the erase operation of step S204 further erases the charges in the floating gate, so that the high boundary point of the threshold voltage distribution of the selected erase block is further lowered.

If the judgment result of step S207 is yes, that is, the high boundary point of the threshold voltage distribution of the selected erase block is EV or less, or the judgment result of step S208 is yes, the subsequent step S209 is performed.

As can be seen from the above, the process in the dashed box 501 corresponds to the whole erasing process step, which includes more than one erasing loop step, and the erasing loop step is composed of steps S204 to S208. Steps S204, S205, and S206 are the main body of the erase cycle step, and steps S207 and S208 are used to control the cycle, and if the erase verification is successful within a limited number of times, the erase is not performed any more; if the number of times exceeds the limit, the erase verification is unsuccessful, and the erase operation is not performed any more. In fig. 5A, step 13 is performed once after each completion of step 11.

In the embodiment of the present invention, after the erasing process is finished, the method further includes:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value. In fig. 6, the third lower limit value is B1, and B1 is a boundary point that needs to be repaired in the final over-erase.

In some preferred embodiments:

as shown in fig. 5A, step three corresponds to step S209, and step S209 performs an over-erase operation for ending the erase block erase, where the over-erase operation for ending the erase block erase is the second over-erase operation, that is, after the flow of the dashed box 501 is completed, the erase process of the erase block is ended, and then the over-erase operation is performed, and the over-erase operation is used for correcting the over-erase generated in the erase process. The first over-erase operation and the second over-erase operation both include over-erase verification and over-erase programming, the over-erase verification detecting whether over-erase exists; the over-erase programming will program the floating gate to charge the floating gate with certain charge to change the threshold voltage of the memory cell to realize the regulation of the lower boundary point.

As can be seen from fig. 6, the curve 603 is obtained by performing the first over-erase operation on the basis of the curve 602 to adjust the lower boundary point, and the upper boundary point of the curve 602 is still greater than EV, which means that the erase procedure is still finished.

Curve 604 is a threshold voltage distribution curve after the second over-erase operation is completed, where the second over-erase operation is performed under the condition that the upper boundary point is less than or equal to EV, and the erase cycle step is performed multiple times to achieve the adjustment of the upper boundary point; after the junction depth is adjusted for the upper boundary point, the erasing process is finished, and then the second over-erasing operation is performed to adjust the lower boundary point in the curve 604, so that the lower boundary point is greater than or equal to B1.

After that, step S210 is performed, other operations, that is, when the erase block erase is ended and the over erase operation is ended, other operations such as an anti-tamper repair operation and the like are performed. And (3) ending other operations, and ending the whole erasing process, namely step S211 and erasing the erasing block.

Unlike the prior art in which the threshold voltage distribution of the selected erase block is adjusted by performing the over-erase operation after the erase process step is completed, the embodiment of the present invention inserts the over-erase operation, i.e., the first over-erase operation, in more than one erase cycle step of the erase process step, so that the first over-erase operation can adjust the threshold voltage distribution of the selected erase block in the erase process step, and the threshold voltage distribution of the selected erase block can be equal to or greater than the second lower limit value after the erase operation of step 11 is completed, because the second lower limit value is set to ensure that the non-selected erase block located in the same block will not generate a read failure, so that even if an abort or power failure occurs during the erase process, each memory cell in the selected erase block can be ensured not to be in an over-erase state, but to be an erase state with the threshold voltage being equal to or greater than the second lower limit value; after restarting, the storage state of each storage unit in the selected erase block will be kept in an abnormal interruption or power-off state, so that no electric leakage occurs when the storage unit in the selected erase block is in an over-erased state and thus the storage units in the non-selected erase block in the same block generate reading errors after restarting, and therefore, the embodiment of the invention can ensure that the reading data errors in the non-erase area of the same block can be avoided after restarting when the abnormal interruption or power-off occurs in the erase process.

In the method of the embodiment of the invention, after each erasure, an over-erasure verification and programming mechanism of the erasure process is buried in advance, so that after each erasure, a certain repair is carried out on the over-erasure memory unit of the erasure unit, and after the next erasure operation, the leakage current on the bit line is still within a certain safety range, and even if the erasure is interrupted or the power is lost at the moment, other un-operated memory units of the same area module can not have the phenomenon of error reading.

Further description is provided below in connection with fig. 6, where:

PV represents a program verify boundary point, that is, when the threshold voltage is less than PV, the program fails, and when the threshold voltage is greater than or equal to PV, the program verification passes.

EV represents a boundary point of erase verification (erase), that is, erase failure when the threshold voltage is greater than EV and erase verification passes when the threshold voltage is less than or equal to EV;

RD represents the read voltage, i.e., the word line voltage operating point at read (read).

B1 represents a boundary point where over-erasure needs to be repaired, that is, when over-erasure exists, it is necessary to repair all threshold voltages to B1 or more.

Curve 601 is the memory cell threshold distribution at the end of the pre-programming, i.e., the memory cell threshold distribution at the end of the pre-programming of step S203, and it can be seen that the threshold voltage is large.

Curve 602 is the threshold distribution of the memory cell after one or more erasures, i.e., the threshold voltage distribution after one step 11 is completed or repeated a plurality of times 11, at which time the erasing may not be successful, the threshold voltage of the memory cell may be higher than EV, which is the boundary point passing the erase verification; the threshold voltage low boundary point of the memory cell exceeds the B1 point, and reaches the B1B point, wherein the B1B point is the lowest point of the low boundary point required to be ensured by one-time erasure, and under the condition of the boundary point, the non-erased memory cells of the same block are read and still cannot fail.

Curve 603 is the threshold distribution of memory cells after performing an over-erase operation of the erase block erase process, i.e., the first over-erase operation, and point B1A is the boundary point reached by the over-erase operation of the erase block erase process, where point B1A is the boundary point to ensure that the low boundary point after the second erase is not lower than point B1B. The moving distance of the boundary points B1A to B1B is controlled by the erase voltage and the erase time.

Curve 604 is the threshold distribution of memory cells after the completion of the over-erase operation, i.e., the second erase operation, after the completion of the erase block erase operation, where the threshold voltage low boundary point of the memory cells reaches or exceeds B1 without disturbing the un-erased area of the same erase block.

FIG. 7 is a graph showing the read current (Icell) of memory cells in the same block after an abnormal power-down restart in the erasing process according to the erasing method of the nonvolatile memory of the embodiment of the invention; in fig. 4:

the read voltage is RD;

curve 701 is the current curve of the reference memory cell;

curve 703 is the current curve for a memory cell storing a "1";

curve 702 is a current curve for a memory cell storing a "0".

In the case where the normal Word Line (Word Line) is in RD, there is a margin between the memory cells "1" and "0" from the reference memory cell, and it is easier to distinguish between "0" and "1".

Curve 704 is a current curve of smaller leakage current of a memory cell after one-time erasing after the erasing process is improved in the embodiment of the present invention, because the over-erasing degree is inhibited, the bit line leakage current is smaller, and the read "0" current and the reference current still have a certain point margin directly, so that the read failure can not occur.

Fig. 8 is a schematic structural diagram of an erasing device of a nonvolatile memory according to an embodiment of the invention. The erasing device of the nonvolatile memory comprises: the flow control module 801.

Before the erasing process, the flow control module 801 performs the following control:

Step one, pre-verifying and pre-programming the selected erase block.

In the step of the erasing process, if the result of the erasing verification operation in the step 12 is that the number of times of the erasing cycle step reaches the maximum number of times, ending the step of the erasing process;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

The flow control module 801 controls the erasing process steps;

the erasing process step includes an erasing loop step including:

step 11, performing an erase operation on a selected erase block in the blocks of the nonvolatile memory device.

Step 12, performing an erase verification operation on the selected erase block.

In the device of the embodiment of the invention, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is smaller than or equal to the set first upper limit value, the result of the erase verification operation is that the selected erase block passes; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit.

In the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure.

In step 13, the first over-erase operation includes:

performing a first over-erase detection for detecting a low boundary point of a threshold voltage distribution of the selected erase block;

and performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter.

The first over-erase parameters include over-erase voltage and over-erase time and the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step; the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step are set according to the difference between the second lower limit value and the first lower limit value.

The erasing device of the embodiment of the invention further comprises:

a detection module 802, configured to implement the first over-erase detection;

a repair module 803 for implementing the first over-erase programming.

The erasing device further includes a voltage control module 804, where the voltage control module 804 receives the first over-erase parameter and provides a voltage to a corresponding memory cell according to the first over-erase parameter. In fig. 8, the memory cells are located in the flash memory array 805.

In the device of the embodiment of the present invention, in the step of the erasing process, if the result of the erase verification operation in step 12 is that the number of cycles of the erase cycle step reaches the maximum number, the step of the erasing process is ended;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

In the step of the erasing process, step 13 is inserted in each erasing cycle step;

or, step 13 is inserted once after every n times of step 11, n is greater than or equal to 2;

or after completing n times of the erasing loop steps, inserting a step 13 in each subsequent erasing loop step, wherein n is greater than 1;

Or after completing n times of the erasing loop steps, inserting a step 13 once after every k times of the step 11 in the subsequent loops, wherein n is greater than 1, k is greater than or equal to 1, and k is a fixed value or an indefinite value.

The flow control module 801 further performs the following control:

after the erasing process is finished, the method further comprises the following steps:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value.

In summary, the apparatus of the embodiment of the present invention shown in fig. 8 includes a flow control module 801, a detection module 802, a repair module 803, a voltage control module 804 and a storage array 805;

detection module 802: after the one-time erasing is finished, namely, over-erasing detection is carried out on the erased block, if the low boundary point of the erasing is lower than B1A, the over-erasing operation is confirmed, and if the low boundary point is lower than B1B, the parameter configuration needs to be carried out on the time and the voltage of the next erasing operation.

Repair module 803: when the detection module 802 determines that over-erasure repair is needed, an instruction is issued to perform over-erasure parameter configuration and repair flow control.

Voltage control module 804: after receiving the instruction of the detection module 802 or the repair module 803, voltage generation and control are performed, and the voltage is configured to a required memory cell.

Flow control module 801: in the erasing process, the progress of the whole process is controlled, including over-erasure detection and repair control after one-time erasure is finished.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (16)

1. An erasing method of a non-volatile memory is characterized in that: the erasing process step includes an erasing loop step of more than one time, the erasing loop step including:

step 11, performing one-time erasing operation on selected erasing blocks in the blocks of the nonvolatile memory device;

step 12, performing an erase verification operation on the selected erase block;

in the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure.

2. The method of erasing a non-volatile memory as in claim 1, further comprising, prior to the erasing step:

step one, pre-verifying and pre-programming the selected erase block.

3. The method for erasing a non-volatile memory as in claim 2, wherein: in the step of the erasing process, if the result of the erasing verification operation in the step 12 is that the number of times of the erasing cycle step reaches the maximum number of times, ending the step of the erasing process;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

4. The method for erasing a non-volatile memory as in claim 3, wherein: after the erasing process is finished, the method further comprises the following steps:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value.

5. The method for erasing a non-volatile memory as in claim 3, wherein: in step 12, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is smaller than or equal to the set first upper limit value, the result of the erase verification operation is that the selected erase block passes; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit.

6. The method for erasing a non-volatile memory as in claim 1, wherein: in the step of the erasing process, step 13 is inserted in each erasing cycle step;

or, step 13 is inserted once after every n times of step 11, n is greater than or equal to 2;

or after completing n times of the erasing loop steps, inserting a step 13 in each subsequent erasing loop step, wherein n is greater than 1;

or after completing n times of the erasing loop steps, inserting a step 13 once after every k times of the step 11 in the subsequent loops, wherein n is greater than 1, k is greater than or equal to 1, and k is a fixed value or an indefinite value.

7. The method for erasing a non-volatile memory as in claim 1, wherein: in step 13, the first over-erase operation includes:

performing a first over-erase verification for detecting a low boundary point of a threshold voltage distribution of the selected erase block;

and performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter.

8. The method for erasing a non-volatile memory as in claim 7, wherein: the first over-erase parameters include over-erase voltage and over-erase time and the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step; the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step are set according to the difference between the second lower limit value and the first lower limit value.

9. An erasing device for a nonvolatile memory, comprising: a flow control module;

the flow control module controls the step of the erasing process;

the erasing process step includes an erasing loop step including:

step 11, performing one-time erasing operation on selected erasing blocks in the blocks of the nonvolatile memory device;

step 12, performing an erase verification operation on the selected erase block;

in the above-mentioned erasing loop step, after the completion of step 11 and before the execution of step 12, the method further comprises:

step 13, performing a first over-erase operation on the selected erase block, wherein the first over-erase operation enables a low boundary point of a threshold voltage distribution of the selected erase block to be greater than or equal to a first lower limit value; the first lower limit value ensures that after the erase operation of step 11 is completed in the next erase cycle step, the threshold voltage distribution of the selected erase block has a low boundary point greater than or equal to a second lower limit value, which is less than the first lower limit value, which ensures that non-selected erase blocks located in the same block will not experience a read failure.

10. The erasing apparatus of a nonvolatile memory as in claim 9, wherein: the flow control module also realizes the following control:

before the erasing process step, further comprising:

step one, pre-verifying and pre-programming the selected erase block.

11. The erasing apparatus of a nonvolatile memory as in claim 10, wherein: in the step of the erasing process, if the result of the erasing verification operation in the step 12 is that the number of times of the erasing cycle step reaches the maximum number of times, ending the step of the erasing process;

if the erase verify operation of step 12 results in no pass and the number of cycles of the erase cycle step is less than a maximum number, continuing the erase cycle step next.

12. The erasing apparatus of a nonvolatile memory as in claim 11, wherein: the flow control module also realizes the following control:

after the erasing process is finished, the method further comprises the following steps:

and thirdly, performing a second over-erase operation on the selected erase block, wherein the second over-erase operation enables a low boundary point of threshold voltage distribution of the selected erase block to be larger than or equal to a third lower limit value, and the third lower limit value is larger than or equal to the first lower limit value.

13. The erasing apparatus of a nonvolatile memory as in claim 11, wherein: in step 12, the erase verification operation is used for verifying the high boundary point of the threshold voltage distribution of the selected erase block, and when the high boundary point of the threshold voltage distribution of the selected erase block is smaller than or equal to the set first upper limit value, the result of the erase verification operation is that the selected erase block passes; the erase verify operation results in no pass when a high boundary point of a threshold voltage distribution of the selected erase block is greater than the first upper limit.

14. The erasing apparatus of a nonvolatile memory as in claim 9, wherein: in the step of the erasing process, step 13 is inserted in each erasing cycle step;

or, step 13 is inserted once after every n times of step 11, n is greater than or equal to 2;

or after completing n times of the erasing loop steps, inserting a step 13 in each subsequent erasing loop step, wherein n is greater than 1;

or after completing n times of the erasing loop steps, inserting a step 13 once after every k times of the step 11 in the subsequent loops, wherein n is greater than 1, k is greater than or equal to 1, and k is a fixed value or an indefinite value.

15. The erasing apparatus of a nonvolatile memory as in claim 9, wherein: in step 13, the first over-erase operation includes:

Performing a first over-erase verification for detecting a low boundary point of a threshold voltage distribution of the selected erase block;

performing first over-erase programming, wherein the first over-erase programming is used for setting the first over-erase parameter and completing the first over-erase operation according to the set first over-erase parameter;

the erasing device further includes:

the detection module is used for realizing the first over-erasure verification;

and the repair module is used for realizing the first over-erase programming.

16. The erasing apparatus for a nonvolatile memory as in claim 15, wherein: the first over-erase parameters include over-erase voltage and over-erase time and the erase voltage and erase time of the erase operation in step 11 of the next erase cycle step; setting an erase voltage and an erase time of the erase operation in step 11 of the next erase cycle step according to a difference between the second lower limit value and the first lower limit value;

the erasing device further comprises a voltage control module, wherein the voltage control module receives the first over-erasing parameter and provides voltage to the corresponding memory cell according to the first over-erasing parameter.

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