CN116186048B - Data processing method and device of FPGA (field programmable gate array) components and electronic equipment - Google Patents

Data processing method and device of FPGA (field programmable gate array) components and electronic equipment Download PDF

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Publication number
CN116186048B
CN116186048B CN202310224458.4A CN202310224458A CN116186048B CN 116186048 B CN116186048 B CN 116186048B CN 202310224458 A CN202310224458 A CN 202310224458A CN 116186048 B CN116186048 B CN 116186048B
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index
master
level
slave
searching
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CN116186048A (en
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于浩月
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Suzhou Yige Technology Co ltd
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Suzhou Yige Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/22—Indexing; Data structures therefor; Storage structures
    • G06F16/2228—Indexing structures
    • G06F16/2264—Multidimensional index structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/22—Indexing; Data structures therefor; Storage structures
    • G06F16/2228—Indexing structures
    • G06F16/2246—Trees, e.g. B+trees
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/2453—Query optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/2455—Query execution
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a data processing method and device of components of an FPGA and electronic equipment. The method comprises the following steps: receiving a message of searching a target component in a plurality of components of the FPGA, and obtaining index information of the target component, wherein the components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level; searching target components in the corresponding master hierarchy and slave hierarchy according to index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master components in the master hierarchy, and the slave index is used for searching the corresponding slave components in the corresponding slave hierarchy; and acquiring attribute information of the target component. The method solves the problems that in the related art, the components of the FPGA are indexed according to the unique numbers, and the speed and the efficiency are low during searching.

Description

Data processing method and device of FPGA (field programmable gate array) components and electronic equipment
Technical Field
The application relates to the field of design assistance, in particular to a data processing method and device for components of an FPGA and electronic equipment.
Background
After the FPGA is applied, UI identification is needed to be carried out on components used after the application is realized, so that a user can check the attribute of the components after operating in an interface. The components are programmable devices inside the FPGA, such as CLC (Configurable Logic Cluster configurable logic cluster) and its internal LUT (Look Up Table), MUX (multiplexer selector), FF (Flip Flop), etc. The storage realized by the components is needed to be used for quick search and attribute searching, so that the debugging work is convenient for the user.
Conventionally, components are numbered, and when the components are searched, interface elements in the UI are correspondingly numbered correspondingly, and the components are indexed according to unique numbers. However, this approach has the disadvantage that when the FPGA implementation scale is large, the amount of data implemented is large, and for the purpose of querying quickly, storage needs to be built in the memory, resulting in a large memory consumption, and for ensuring that the components after each FPGA implementation are positioned when selected in the UI, one instance needs to be reserved, and this number of instances is very large, resulting in a slow processing speed.
Aiming at the problems of low speed and low efficiency in searching when the components of the FPGA in the related technology are indexed according to the unique numbers, no effective solution is proposed at present.
Disclosure of Invention
The application mainly aims to provide a data processing method and device for components of an FPGA and electronic equipment, and aims to solve the problems that in the related art, the components of the FPGA are indexed according to unique numbers, and the speed is low and the efficiency is low during searching.
In order to achieve the above object, according to one aspect of the present application, there is provided a data processing method of a component of an FPGA, the method comprising: receiving a message of searching a target component in a plurality of components of an FPGA, and obtaining index information of the target component, wherein the components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level; searching the target component in a corresponding master level and a corresponding slave level according to the index information, wherein the index information comprises a master index or a master index and a slave index, the master index is used for searching the corresponding master component in the master level, and the slave index is used for searching the corresponding slave component in the corresponding slave level; and acquiring attribute information of the target component.
Optionally, searching the target component in the corresponding master hierarchy and slave hierarchy according to the index information includes: under the condition that the index information only comprises a main index, searching the target component in the main hierarchy according to the main index; under the condition that the index information comprises a master index and a slave index, searching a master device to which the target component belongs in the master hierarchy according to the master index; and searching the target component in a plurality of components of a slave level of the master component according to the slave index based on the master component to which the target component belongs.
Optionally, the main hierarchy is a top tile hierarchy, and the main index is a two-dimensional coordinate, where main devices of the top tile hierarchy are all arranged according to two-dimensional rows and columns; according to the primary index, searching the target component in the primary hierarchy comprises: searching the target component in the main component of the top tile level according to the two-dimensional coordinates; according to the master index, searching the master device to which the target component belongs in the master hierarchy comprises: and searching the main device to which the target component belongs from the main devices of the top tile level according to the two-dimensional coordinates.
Optionally, the slave hierarchy includes: a part site level, a unit element level, wherein the slave index comprises relative coordinates of each slave level relative to the components of the upper level; according to the slave index, searching the target component in the components of the slave level of the master component comprises: searching the component belonging to the target component in the component site level according to the relative coordinates of the main component belonging to the target component, wherein the component site level is the next level of the main level; and searching the target component in the unit element level according to the relative coordinates of the component to which the target component belongs in the component site level, or searching the component to which the target component belongs until the target component is found, wherein the component site level is the next level of the main level.
Optionally, the two-dimensional coordinates of the master device in the master hierarchy are stored in the form of an array; the relative coordinates of the components in the slave level are stored in a tree structure, and the relative coordinates are stored in a storage catalog of the main component or the component of the upper level to which the relative coordinates belong.
Optionally, before receiving a message for searching for a target component in a plurality of components of the FPGA and obtaining the master index and the slave index of the target component, the method further includes: displaying visual identifiers of a plurality of components of the FPGA, wherein each component uniquely corresponds to one visual identifier; and generating the message in response to the operation of the visual identification of the target component.
Optionally, the attribute information includes: name, location, type, parameters; after obtaining the attribute information of the target component, the method further comprises: and displaying the attribute information in a preset display mode.
In order to achieve the above object, according to another aspect of the present application, there is provided a data processing apparatus of a component of an FPGA, including: the device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving a message for searching a target component in a plurality of components of an FPGA and obtaining index information of the target component, wherein the plurality of components are divided into a plurality of layers, including a master layer and a slave layer, and the components of the slave layer are arranged based on the component division of the master layer; the searching module is used for searching the target component in a corresponding master level and a corresponding slave level according to the index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master component in the master level, and the slave index is used for searching the corresponding slave component in the corresponding slave level; and the acquisition module is used for acquiring the attribute information of the target component.
In order to achieve the above object, according to another aspect of the present application, there is provided a computer-readable storage medium for storing a program, wherein the program performs the data processing method of the components of the FPGA of any one of the above.
In order to achieve the above object, according to another aspect of the present application, there is provided an electronic device including one or more processors and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement a data processing method of an element of the FPGA of any one of the above.
The method comprises the steps of obtaining index information of a target component by receiving a message of searching the target component in a plurality of components of an FPGA, wherein the components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level; searching target components in the corresponding master hierarchy and slave hierarchy according to index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master components in the master hierarchy, and the slave index is used for searching the corresponding slave components in the corresponding slave hierarchy; and acquiring attribute information of the target component. The method achieves the aim of quickly searching the target components according to the main index or the main index and the auxiliary index, further achieves the technical effect of improving the searching speed and efficiency of the two-zero target components, and further solves the problems that the speed is low and the efficiency is low when the components of the FPGA are indexed according to the unique number in the related technology.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 is a flow chart of a method for processing data of components of an FPGA according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a master device of a master hierarchy provided in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram of components of a part site level provided in accordance with an embodiment of the present application;
FIG. 4 is a schematic diagram of components of a unit element hierarchy provided in accordance with an embodiment of the present application;
FIG. 5 is a schematic diagram of a data processing apparatus for components of an FPGA according to an embodiment of the present application;
fig. 6 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The present application will be described with reference to preferred implementation steps, and fig. 1 is a flowchart of a method for processing data of an FPGA component according to an embodiment of the present application, as shown in fig. 1, where the method includes the following steps:
step S101, receiving a message of searching a target component in a plurality of components of the FPGA, and obtaining index information of the target component, wherein the plurality of components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level;
step S102, searching target components in a corresponding master level and a slave level according to index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master component in the master level, and the slave index is used for searching the corresponding slave component in the corresponding slave level;
step S103, obtaining attribute information of the target component.
The method comprises the steps of obtaining index information of a target component by receiving a message of searching the target component in a plurality of components of an FPGA, wherein the plurality of components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level; searching target components in the corresponding master hierarchy and slave hierarchy according to index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master components in the master hierarchy, and the slave index is used for searching the corresponding slave components in the corresponding slave hierarchy; and acquiring attribute information of the target component.
The method achieves the aim of quickly searching the target components according to the main index or the main index and the auxiliary index, further achieves the technical effect of improving the searching speed and efficiency of the two-zero target components, and further solves the problems that the speed is low and the efficiency is low when the components of the FPGA are indexed according to the unique number in the related technology.
The execution subject of the above steps may be a management application of the FPGA or a design application, which may be set on a processor, a calculator or a controller to perform data processing to perform the data processing operations in the above steps, for example, step S101 to step S103.
The design application can be a general code writing tool, writes the design data according to a language with a fixed format through the design application, and generates files with different formats to provide the design data for different design scenes. The management application can collect, manage and analyze data of the components of the FPGA.
In step S101, a message for searching for a target component from a plurality of components in the FPGA is received, and index information of the target component is obtained. The device comprises a plurality of components and a plurality of sub-layers, wherein the components are divided into a plurality of layers, including a master layer and a sub-layer, and the components of the sub-layer are arranged based on the component division of the master layer;
the FPGA comprises a plurality of levels of components, including a master level and a slave level, wherein the slave level is based on the master device of the master level, namely, the master devices in the master level are provided with the corresponding slave levels, and the slave levels among different master devices can be mutually independent without interference, so that the searching efficiency of the components can be improved. The method and the device avoid the logic crossing of components of different main devices, and the query range is widened.
Optionally, before receiving a message for searching for the target component in the multiple components of the FPGA and obtaining the master index and the slave index of the target component, the method further includes: displaying visual identifications of a plurality of components of the FPGA, wherein each component uniquely corresponds to one visual identification; and responding to the operation of the visual identification of the target component, and generating a message.
The execution main body can display a plurality of components in the UI interface through the UI interface interacted with the user, or can check the icons of all the components by clicking the logic tree, and can automatically generate the message by clicking the icon of a selected target component, namely, the message for searching the target component in the plurality of components of the FPGA.
The message carries the master index and the slave index of the target component. It should be noted that, the target component may be a master component or a slave component, and in the case that the target component is a master component, the message carries the master index, because the master index can find the target component. In the case that the target component is a slave component, the message may carry a master index of the master component to which the slave component belongs and a slave index corresponding to the slave component.
After the execution body receives the message, the corresponding target component is searched according to the main index or the main index and the slave index carried by the message. If the target component is the main component, the target component can be quickly found out only according to the main index during the search.
If the target component is a slave component, the master component to which the slave component belongs is quickly found through the master index during searching, and then the corresponding slave component is searched by using the slave index based on the slave components with the smaller number included in the master component. And further ensuring the searching efficiency and speed of the target component.
Optionally, the main hierarchy is a top tile hierarchy, and the main index is a two-dimensional coordinate, wherein main devices of the top tile hierarchy are arranged according to two-dimensional rows and columns; according to the primary index, searching the target component in the primary hierarchy comprises: searching a target component in the main component of the top tile level according to the two-dimensional coordinates; according to the master index, searching the master device to which the target component belongs in the master hierarchy comprises the following steps: and searching the main device to which the target component belongs from the main devices of the top tile level according to the two-dimensional coordinates.
In this embodiment, the main hierarchy is a top-level tile hierarchy, and in order to ensure high efficiency of implementation, in this hierarchy, the implemented main devices are put to the same top-level tile hierarchy as much as possible, and the main devices in the top-level tile hierarchy are arranged in a regular rectangular shape of an X and Y coordinate system, as shown in fig. 2. Therefore, according to the X and Y coordinates of the user operation, which top tile level the user belongs to can be rapidly positioned.
The step S102 searches for the target component in the corresponding master hierarchy and slave hierarchy according to the index information, where the index information includes a master index, or a master index and a slave index, the master index refers to searching for the corresponding master component in the master hierarchy, and the slave index refers to searching for the corresponding slave component in the corresponding slave hierarchy.
Optionally, searching the target component in the corresponding master hierarchy and slave hierarchy according to the index information includes:
under the condition that the index information only comprises a main index, searching a target component in a main level according to the main index;
under the condition that the index information comprises a master index and a slave index, searching a master device to which a target component belongs in a master level according to the master index; and searching the target component in the components of the slave hierarchy of the master component according to the slave index based on the master component to which the target component belongs.
And under the condition that the index information only comprises the main index, searching the corresponding target component according to the main index carried by the message. During searching, the target component can be quickly searched only according to the main index.
And under the condition that the index information comprises the master index and the slave index, searching the corresponding target component according to the master index and the slave index carried by the message. During searching, the master device to which the slave device belongs is quickly found through the master index, and then the corresponding slave device is searched by the slave index based on the slave devices with the smaller number included in the master device. And further ensuring the searching efficiency and speed of the target component.
Optionally, the slave hierarchy includes: a part site level, a unit element level, and a slave index comprising the relative coordinates of each slave level relative to the upper level of the component; according to the slave index, searching the target component in the components of the slave level of the master component comprises the following steps:
searching the component belonging to the target component in a component site level according to the relative coordinates of the main component belonging to the target component, wherein the component site level is the next level of the main level; and searching the target component in the unit element level according to the relative coordinates of the component to which the target component belongs in the component site level, or searching the component to which the target component belongs until the target component is found, wherein the component site level is the next level of the main level.
In this embodiment, two slave levels of the master CLC are provided, from top to bottom, respectively, a component site level, and a unit element level, based on the master being the top tile level.
Fig. 3 is a schematic diagram of components of a component site level provided according to an embodiment of the present application, and as shown in fig. 3, the component site level of a master CLC includes a plurality of slave devices such as a Switch hub_hub, an Input multiplexer input_mux, an Output multiplexer output_mux, an Input logic multiplexer Input2 logic_mux, and a Function Block.
Fig. 4 is a schematic diagram of a component of a unit element level provided according to an embodiment of the present application, where, as shown in fig. 4, the unit element level of the Function Block includes a plurality of LUTs, a plurality of CLAs, a plurality of FFs, and other slave devices.
The coordinates of the use of the components of different levels are different, and the storage modes are also different. In the CLC, the relative coordinates may be used to locate to a site, such as a function block located at the relative coordinate (2, 2) position inside the CLC. In the Function Block, the relative coordinates may be used to locate to an element, such as a LUT located at its internal relative coordinates (0, 0).
Optionally, the two-dimensional coordinates of the master device in the master hierarchy are stored in the form of an array; the relative coordinates of the components in the slave hierarchy are stored in a tree structure, and the relative coordinates are stored in a storage directory of the main component or the component of the upper level to which the relative coordinates belong.
The coordinates of all the master devices are stored in an array form so that quick search and retrieval can be performed. In the components below the top tile level, the relative coordinates are used, and each slave device stores its own relative coordinates and the coordinates of the previous level, and stores the relative coordinates in a tree structure, so that the query can be traversed orderly and quickly during the query.
In step S103, attribute information of the target component is acquired. Optionally, the attribute information includes: name, location, type, parameters; after obtaining the attribute information of the target component, the method further comprises the following steps: and displaying the attribute information through a preset display mode.
After the attribute information of the target component is acquired, the attribute information of the selected target component can be displayed on the UI interface of the execution body so as to display the attribute information of the selected target component to the user.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in a different order than that illustrated herein.
It should be noted that the present application also provides an alternative embodiment, and the following detailed description of the embodiment is provided.
According to the embodiment, the components are positioned and retrieved in the UI tool efficiently, according to the characteristics of FPGA implementation, the components are first hierarchical, the top layer is a top layer tile hierarchy, strict rectangular coordinates (X and Y coordinates) are arranged, then the hierarchy is arranged, and then each component also has relative coordinates of the hierarchy.
Carefully look at the data characteristics: the elements of the top tile level of the FPGA are sparse, because in order to ensure the high efficiency of implementation, in this level, the implemented main devices are put to the same top tile level as much as possible, and the main devices of the top tile level are arranged in a regular rectangular shape of the X and Y coordinate system. Therefore, according to the X and Y coordinates of the user operation, which top tile level the user belongs to can be rapidly positioned.
Fig. 2 is a schematic diagram of a master device of a master level provided according to an embodiment of the present application, as shown in fig. 2, the master devices of the master level being the top tile level (such as Pad and CLC in fig. 2) are arranged in a rectangular shape according to an x and y coordinate system, and may be located to a designated and unique master device according to an input (x and y) coordinate. After the main device is positioned, the specific main device selected in the main device is confirmed according to the relative coordinates and the stored fixed position information.
In this way, the actual instance does not need to be reserved during drawing, and only the positioning is needed to be performed according to the X and Y coordinates and the actual multi-level index during user operation.
The positioning process is as follows: first a master device, such as a CLC located at (1, 1), is located based on the entered (x, y) coordinates.
In the CLC, the relative coordinates may be used to locate to a part site level, and fig. 3 is a schematic diagram of a part site level component provided according to an embodiment of the present application, as shown in fig. 3, and a Function Block located at a position of the relative coordinates (2, 2) inside the CLC.
In the Function Block, the relative coordinates may be used to locate to a unit element level, and fig. 4 is a schematic diagram of a unit element level component provided according to an embodiment of the present application, and as shown in fig. 4, an LUT located in the relative coordinates (0, 0) of the unit element level component is shown. Such a multi-level index is used to locate a specific component.
The coordinates of the use of the components of different levels are different, and the storage modes are also different. In the top tile level, the coordinates of the master devices of all top tile levels are saved in an array form using the (x, y) coordinates.
In the components below the top tile level, the relative coordinates are used, and each component stores its own relative coordinates and the coordinates of the previous level, and stores the relative coordinates and the coordinates of the previous level in a tree structure.
The (x, y) coordinates are used for positioning to the main device, the relative coordinates are used for indexing the components of the next level in the main device, and the relative coordinates are continuously used for indexing in the components of the next level until the components which are specifically applied are positioned.
By utilizing the characteristics of the FPGA, a multi-level index storage mode is adopted, so that the retrieval speed is improved, excessive examples are not required to be saved when the UI is drawn, and the display efficiency is improved.
Examples of specific application scenarios:
the top tile level has masters of Pad and CLC, and is located using (x, y) coordinates.
After locating a specific master device (such as CLC), the components (including Function Block, switch_hub, etc.) in the CLC are indexed by using the relative coordinate index, and after indexing to the Function Block, the components in the CLC (Carry-look ahead Adder), LUT, FF, etc. are used.
After positioning, the device is used for viewing attribute information of the device, such as name, position, device type and the like.
The reason why the search speed can be improved is that: the arrangement of the components of the top tile level is regular and sparse, the number of sub-level components included in the top tile level is huge, the components can be rapidly indexed to a designated main component by using the (x, y) coordinates, and the specific components are positioned in the top tile level through the level index mode.
Compared with the common searching of all element index numbers, the method can quickly position specific components inside.
Fig. 5 is a schematic diagram of a data processing device of an FPGA according to an embodiment of the present application, and as shown in fig. 5, an embodiment of the present application further provides a data processing device of an FPGA, and it should be noted that, the data processing device of an FPGA of the embodiment of the present application may be used to execute the data processing method for an FPGA of the embodiment of the present application. The following describes a data processing device of an FPGA component provided in an embodiment of the present application. The device comprises: the receiving module 51, the searching module 52, and the obtaining module 53 are specifically as follows.
The receiving module 51 is configured to receive a message for searching for a target component from a plurality of components of the FPGA, and obtain index information of the target component, where the plurality of components are divided into a plurality of levels, including a master level and a slave level, and components of the slave level are set based on component division of the master level; the searching module 52 is connected to the receiving module 51, and is configured to search the target component in a corresponding master hierarchy and a slave hierarchy according to the index information, where the index information includes a master index, or a master index and a slave index, the master index refers to searching the corresponding master component in the master hierarchy, and the slave index is configured to search the corresponding slave component in the corresponding slave hierarchy; and the obtaining module 53 is connected to the searching module 52, and is configured to obtain attribute information of the target component.
According to the data processing device of the components of the FPGA, the index information of the target components is obtained by receiving the information of searching the target components in the components of the FPGA, wherein the components are divided into a plurality of layers, including a master layer and a slave layer, and the components of the slave layer are arranged based on the component division of the master layer; searching target components in the corresponding master hierarchy and slave hierarchy according to index information, wherein the index information comprises a master index or a master index and a slave index, the master index refers to searching the corresponding master components in the master hierarchy, and the slave index is used for searching the corresponding slave components in the corresponding slave hierarchy; and acquiring attribute information of the target component.
The method achieves the aim of quickly searching the target components according to the main index or the main index and the auxiliary index, further achieves the technical effect of improving the searching speed and efficiency of the two-zero target components, and further solves the problems that the speed is low and the efficiency is low when the components of the FPGA are indexed according to the unique number in the related technology.
The data processing device of the components of the FPGA comprises a processor and a memory, the receiving module 51, the searching module 52, the obtaining module 53 and the like are all stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The core can be provided with one or more cores, and the problems of low speed and low efficiency in searching are solved by adjusting the core parameters to index the components of the FPGA according to the unique numbers in the related technology.
The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.
The embodiment of the application provides a computer readable storage medium, on which a program is stored, which when executed by a processor, implements a data processing method for components of the FPGA.
The embodiment of the application provides a processor which is used for running a program, wherein the data processing method of the components of the FPGA is executed when the program runs.
Fig. 6 is a schematic diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 6, an embodiment of the present application provides an electronic device 60, where the device includes a processor, a memory, and a program stored in the memory and capable of running on the processor, and the steps of the data processing method of the components of the FPGA are implemented when the processor executes the program:
the device herein may be a server, PC, PAD, cell phone, etc.
The application also provides a computer program product adapted to perform a program initialized with any of the above method steps when executed on a data processing device of a component of an FPGA.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions.
These computer program instructions may be provided to a processor of a data processing apparatus of a general purpose computer, special purpose computer, embedded processor, or other programmable FPGA's component to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable FPGA's component, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable gate array (FPGA) device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a data processing apparatus of a component of a computer or other programmable FPGA, such that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (8)

1. The data processing method of the components of the FPGA is characterized by comprising the following steps of:
receiving a message of searching a target component in a plurality of components of an FPGA, and obtaining index information of the target component, wherein the components are divided into a plurality of levels, including a master level and a slave level, and the components of the slave level are arranged based on component division of the master level;
searching the target component in a corresponding master level and a corresponding slave level according to the index information, wherein the index information comprises a master index or a master index and a slave index, the master index is used for searching the corresponding master component in the master level, and the slave index is used for searching the corresponding slave component in the corresponding slave level;
acquiring attribute information of the target component;
searching the target component in the corresponding main hierarchy and slave hierarchy according to the index information comprises the following steps:
under the condition that the index information only comprises a main index, searching the target component in the main hierarchy according to the main index;
under the condition that the index information comprises a master index and a slave index, searching a master device to which the target component belongs in the master hierarchy according to the master index;
based on a master device to which the target component belongs, searching the target component from a plurality of components of a slave level of the master device according to the slave index;
the main level is a top level, and the main index is a two-dimensional coordinate, wherein main devices of the top level are all arranged according to two-dimensional rows and columns;
according to the primary index, searching the target component in the primary hierarchy comprises:
searching the target component in the main component of the top layer level according to the two-dimensional coordinates;
according to the master index, searching the master device to which the target component belongs in the master hierarchy comprises:
and searching the master device to which the target component belongs from the master devices of the top layer hierarchy according to the two-dimensional coordinates.
2. The method of claim 1, wherein the slave hierarchy comprises: a component level and a unit level, wherein the slave index comprises relative coordinates of each slave level relative to a component of an upper level;
according to the slave index, searching the target component in the components of the slave level of the master component comprises:
searching the component to which the target component belongs in the component hierarchy according to the relative coordinates of the main component to which the target component belongs, wherein the component hierarchy is the next hierarchy of the main hierarchy;
and searching the target component in the unit level according to the relative coordinates of the component to which the target component belongs in the component level, or searching the component to which the target component belongs until the target component is found, wherein the component level is the next level of the main level.
3. The method of claim 2, wherein the two-dimensional coordinates of the master devices in the master hierarchy are stored in the form of an array;
the relative coordinates of the components in the slave level are stored in a tree structure, and the relative coordinates are stored in a storage catalog of the main component or the component of the upper level to which the relative coordinates belong.
4. The method of claim 1, wherein receiving a message to find a target component among a plurality of components of an FPGA, prior to obtaining a master index and a slave index for the target component, the method further comprises:
displaying visual identifiers of a plurality of components of the FPGA, wherein each component uniquely corresponds to one visual identifier;
and generating the message in response to the operation of the visual identification of the target component.
5. The method of claim 1, wherein the attribute information comprises: name, location, type, parameters;
after obtaining the attribute information of the target component, the method further comprises:
and displaying the attribute information in a preset display mode.
6. A data processing apparatus for components of an FPGA, comprising:
the device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving a message for searching a target component in a plurality of components of an FPGA and obtaining index information of the target component, wherein the plurality of components are divided into a plurality of layers, including a master layer and a slave layer, and the components of the slave layer are arranged based on the component division of the master layer;
the searching module is used for searching the target component in a corresponding main level and a corresponding slave level according to the index information, wherein the index information comprises a main index or a main index and a slave index, the main index is used for searching the corresponding main component in the main level, and the slave index is used for searching the corresponding slave component in the corresponding slave level, and particularly is used for searching the target component in the main level according to the main index under the condition that the index information only comprises the main index; under the condition that the index information comprises a master index and a slave index, searching a master device to which the target component belongs in the master hierarchy according to the master index; based on a master device to which the target component belongs, searching the target component from a plurality of components of a slave level of the master device according to the slave index; the main level is a top level, and the main index is a two-dimensional coordinate, wherein main devices of the top level are all arranged according to two-dimensional rows and columns; according to the primary index, searching the target component in the primary hierarchy comprises: searching the target component in the main component of the top layer level according to the two-dimensional coordinates; according to the master index, searching the master device to which the target component belongs in the master hierarchy comprises: according to the two-dimensional coordinates, searching a main device to which the target component belongs from the main devices of the top layer level;
and the acquisition module is used for acquiring the attribute information of the target component.
7. A computer-readable storage medium for storing a program, wherein the program performs the data processing method of the components of the FPGA of any one of claims 1 to 5.
8. An electronic device comprising one or more processors and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of data processing for the components of the FPGA of any of claims 1-5.
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