CN116185915A - Bus scheduling method, device and equipment, medium and baseboard management control chip - Google Patents
Bus scheduling method, device and equipment, medium and baseboard management control chip Download PDFInfo
- Publication number
- CN116185915A CN116185915A CN202310431057.6A CN202310431057A CN116185915A CN 116185915 A CN116185915 A CN 116185915A CN 202310431057 A CN202310431057 A CN 202310431057A CN 116185915 A CN116185915 A CN 116185915A
- Authority
- CN
- China
- Prior art keywords
- module
- bus
- target
- priority
- system bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The application discloses a bus scheduling method, a bus scheduling device, bus scheduling equipment, a medium and a substrate management control chip, and relates to the technical field of computers, wherein the bus scheduling method comprises the following steps: dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories; when an interrupt request of a first target functional module higher than a preset priority is received, distributing control right of a system bus to the first target functional module; when an interrupt request of a first target functional module with higher than a preset priority is not received, polling whether the functional module with lower than the preset priority has a data transmission requirement, and when a second target functional module with the data transmission requirement is polled, distributing control right of a system bus to the second target functional module. The method and the device avoid bus blocking under an interrupt mechanism and simultaneously avoid that key information can not be transmitted in time under a polling mechanism.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a bus scheduling method, apparatus and device, medium, and baseboard management control chip.
Background
There are two types of scheduling management strategies for the system bus in the conventional baseboard management control chip, namely an interrupt mode and a polling mode. The interrupt mode sets interrupt priority for each peripheral module hung on the bus for the bus arbitration module, when a certain module wants to transmit data through the bus, the interrupt is reported to the bus arbitration module, and the bus arbitration module prioritizes the controller of the bus according to the priority setting of each module and weights the controller of the bus for each sub-module. The polling mode is to make the CPU (central processing unit ) inquire each peripheral in sequence with a certain period, inquire whether there is a data input or output requirement, if so, perform corresponding input/output service; if not, or the data transmission processing is finished, the CPU then inquires the next peripheral.
In a conventional baseboard management control chip, in order to prevent bus blocking, for example, high-priority peripheral devices always transmit data and occupy a system bus, while a low-priority module has urgent data to transmit at the moment, but cannot acquire bus control rights and transmit data through the bus, so that critical information is not transmitted timely, and the bus occupation processing of each peripheral device is generally performed in a polling mode. The disadvantage of the polling method is that the urgent data cannot be transmitted at the first time, for example, the module a currently occupies the bus, but the module B needs to transmit the urgent data, for example, the warning information that the motherboard temperature is too high but the bus control right cannot be obtained all the time, which may cause extreme serious consequences, for example, burning out the CPU of the motherboard of the server or scrapping the entire motherboard, resulting in serious irrecoverable loss.
Therefore, how to avoid bus blocking under the interrupt mechanism, and at the same time, avoid that key information cannot be timely transmitted under the polling mechanism is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a bus scheduling method and device, electronic equipment and a computer readable storage medium, which avoid bus blocking under an interrupt mechanism and simultaneously avoid that key information can not be transmitted in time under a polling mechanism.
In order to achieve the above object, the present application provides a bus scheduling method, including:
dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories;
when an interrupt request of a first target functional module higher than a preset priority is received, distributing control rights of the system bus to the first target functional module;
when an interrupt request of a first target functional module higher than the preset priority is not received, whether a functional module lower than the preset priority has a data transmission requirement or not is polled, and when a second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
The method for classifying the plurality of functional modules connected to the system bus in the baseboard management control chip into a plurality of categories, and assigning different priorities to the functional modules in different categories comprises the following steps:
the method comprises the steps of dividing a plurality of functional modules, except a central processing unit and a storage module, connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules in different categories.
Wherein, the dividing the plurality of functional modules of the baseboard management control chip except the central processing unit and the storage module connected to the system bus into a plurality of categories, and assigning different priorities to the functional modules of different categories comprises:
dividing a plurality of functional modules of the baseboard management control chip, except for a central processing unit and a storage module, which are connected to a system bus into a first category, a second category and a third category; the first category comprises a functional module which interacts with the storage module, the second category comprises a functional module which interacts with a host end, and the third category comprises a key information detection module;
assigning different priorities to the different types of functional modules; the priority of the function modules of the third category is higher than that of the function modules of the second category, and the priority of the function modules of the second category is higher than that of the function modules of the first category.
The memory module is specifically a double-rate synchronous dynamic random access memory.
The first category of functional modules comprises any one or a combination of any two of a video graphic array module, an image file module and a display interface module.
The second class of functional modules comprise any one or a combination of any two of an LPC bus module, a universal serial bus module, an H2B module and a management component transmission protocol module.
Wherein the third class of functional modules comprises any one or a combination of a plurality of master-slave serial bus modules, universal asynchronous receiver transmitter modules and pulse width modulation modules.
The multi-master-slave serial bus module is used for detecting any one or a combination of any two of main board temperature, main board voltage, fan rotating speed and CPU information.
When receiving an interrupt request of a first target functional module higher than a preset priority, the method distributes control rights of the system bus to the first target functional module, and comprises the following steps:
and when receiving the interrupt request of the first target functional module of the second category or the third category, distributing the control right of the system bus to the first target functional module.
When no interrupt request of the first target function module higher than the preset priority is received, polling whether a function module lower than the preset priority has a data transmission requirement, and when polling a second target function module having the data transmission requirement, distributing control rights of the system bus to the second target function module, wherein the method comprises the following steps:
when the interrupt request of the first target functional module of the second category or the third category is not received, the functional module of the first category is polled whether the data transmission requirement exists, and when the second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
When receiving an interrupt request of a first target functional module higher than a preset priority, the method distributes control rights of the system bus to the first target functional module, and comprises the following steps:
when interrupt requests of a plurality of first target function modules with higher than preset priority are received, the control right of the system bus is distributed to the first target function module with the highest priority.
Wherein, still include:
The method comprises the steps of dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of groups, and distributing different priorities to the functional modules of different groups.
Wherein each group contains all kinds of functional modules.
When receiving interrupt requests of a plurality of first target function modules with higher than preset priority, the method distributes control rights of the system bus to the first target function module with highest priority, and comprises the following steps:
respectively receiving interrupt requests of a plurality of first target function modules with priorities higher than preset priorities in different groups by using sub-scheduling units corresponding to the different groups, and determining the first target function module with the highest priority in each group;
and determining a first target function module with the highest priority from the first target function modules with the highest priority determined by different sub-scheduling units by utilizing the total scheduling unit, and distributing the control right of the system bus to the first target function module with the highest priority.
The polling of whether the functional module with the lower priority than the preset priority has a data transmission requirement, when polling a second target functional module with the data transmission requirement, distributing the control right of the system bus to the second target functional module, including:
And utilizing the total scheduling unit to poll whether the functional module with the lower priority than the preset priority has the data transmission requirement, and distributing the control right of the system bus to a second target functional module when the second target functional module with the data transmission requirement is polled.
Wherein, still include:
in the process of data transmission of the third target functional module, if an interrupt request of a fourth target functional module with higher than the preset priority is received, judging whether the priority of the fourth target functional module is higher than the priority of the third target functional module;
and if the control right is higher than the control right, switching the control right of the system bus to the fourth target functional module.
After the control right of the system bus is switched to the fourth target functional module, the method further comprises:
and after the data transmission of the fourth target functional module is completed, switching the control right of the system bus to the third target functional module.
To achieve the above object, the present application provides a bus scheduling apparatus, including:
the first dividing module is used for dividing a plurality of functional modules connected to the system bus in the baseboard management control chip into a plurality of categories and distributing different priorities to the functional modules in different categories;
The first allocation module is used for allocating the control right of the system bus to the first target functional module when receiving an interrupt request of the first target functional module with higher than a preset priority;
and the second allocation module is used for polling whether the function module with the lower priority has data transmission requirements or not when the interrupt request of the first target function module with the higher priority is not received, and allocating the control right of the system bus to the second target function module when the second target function module with the data transmission requirements is polled.
To achieve the above object, the present application provides an electronic device, including:
a memory for storing a computer program;
and a processor for implementing the steps of the bus scheduling method as described above when executing the computer program.
To achieve the above object, the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the bus scheduling method as described above.
In order to achieve the above object, the present application provides a baseboard management control chip, including a plurality of functional modules, a plurality of sub-scheduling units and a total scheduling unit, wherein a plurality of the functional modules are divided into a plurality of categories, different categories of functional modules correspond to different priorities, a plurality of the functional modules in the same category are divided into a plurality of groups, different groups of functional modules correspond to different priorities, and each group contains all the categories of functional modules;
The sub-scheduling unit is used for receiving interrupt requests of a plurality of first target function modules which are higher than a preset priority in the corresponding packet, and determining the first target function module with the highest priority in each packet;
the total scheduling unit is used for determining a first target functional module with the highest priority among the first target functional modules with the highest priority determined by different sub-scheduling units, and distributing the control right of the system bus to the first target functional module with the highest priority;
the total scheduling unit is further configured to poll whether a functional module with a lower priority than the preset priority has a data transmission requirement when an interrupt request of a first target functional module with a higher priority than the preset priority is not received, and allocate control rights of the system bus to a second target functional module with the data transmission requirement when the second target functional module with the data transmission requirement is polled.
According to the scheme, the bus scheduling method provided by the application comprises the following steps: dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories; when an interrupt request of a first target functional module higher than a preset priority is received, distributing control rights of the system bus to the first target functional module; when an interrupt request of a first target functional module higher than the preset priority is not received, whether a functional module lower than the preset priority has a data transmission requirement or not is polled, and when a second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
The beneficial effects of this application lie in: and classifying the functional modules according to the characteristics of the functional modules in the baseboard management control chip, and distributing different priorities to the functional modules of different categories. And scheduling the function module with higher priority by adopting an interrupt mechanism, ensuring that key information can be transmitted in time, and scheduling the function module with lower priority by adopting a polling mechanism, thereby avoiding system bus blocking. Therefore, the bus scheduling method provided by the application adopts a comprehensive scheduling strategy of combining local scheduling with overall scheduling, and the polling and the interruption are organically coordinated, namely, a timely exit detection mechanism for sudden interruption exists, so that the bus blockage is prevented while the priority output of emergency data is ensured, and the bus load of a substrate management control chip is ensured to the greatest extent. The application also discloses a bus scheduling device, electronic equipment and a computer readable storage medium, and the technical effects can be achieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
FIG. 1 is a diagram of a system bus arbitration management architecture in baseboard management control in accordance with the related art;
FIG. 2 is a flowchart illustrating a method of bus scheduling, according to an example embodiment;
FIG. 3 is a flowchart illustrating another bus scheduling method according to an exemplary embodiment;
FIG. 4 is a diagram of a baseboard management control chip bus load balancing architecture shown in accordance with an exemplary embodiment;
FIG. 5 is a block diagram of a bus scheduler shown according to an exemplary embodiment;
fig. 6 is a block diagram of an electronic device, according to an example embodiment.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. In addition, in the embodiments of the present application, "first," "second," and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence.
In the related art, as shown in fig. 1, a system bus arbitration management architecture in baseboard management control is shown, a processor (BMC CPU) of a baseboard management control chip is connected to a system bus, and then other sub-modules of the chip are mounted on the system bus, such as tens of sub-modules including DDR (double rate synchronous dynamic Random Access Memory, double Data Rate SDRAM), IIC (Inter-Integrated Circuit, multi-master serial bus), UART (universal asynchronous transceiver, universal Asynchronous Receiver/Transmitter), SPI (serial peripheral interface ), flash, H2B (Host 2BMC, control module for accessing internal registers of the BMC at a Host end), VGA (Video Graphics Array ), JPEG (video compression), EMAC (Ethernet Media Access Controller ), USB (Universal Serial Bus, universal serial bus), MCTP (Management Component Transport Protocol, management component transfer protocol), SRAM (Static Random Access Memory), DMA (Direct Memory Access ), AXI2AHB, and the like.
In order to avoid bus congestion caused by long-time occupation of high-priority interrupt, the traditional scheme adopts a polling mode, such as a mode that a CPU inquires whether the IIC has data to be transmitted or not, if so, the IIC transmits, if not, the CPU detects UART, the UART is sequentially carried out, then the UART is circulated, no concept of priority is adopted among the sub-modules, and the sub-modules are completely carried out according to a preset sequence, so that bus congestion is avoided, and the method is a more conventional reasonable method.
However, the above solution has a huge disadvantage, for example, when the module a has an emergency, and there is urgent information to be transmitted, at this time, if a is not polled, the urgent information cannot be transmitted to the upper software in time, for example, the IIC detects that the temperature of the CPU at the host end is abnormally high, and the information needs to be transmitted in time, and the upper software needs to process the information in time, but if the IIC is not polled, for example, the CPU of the baseboard management control chip is processing UART data, the UART transmits only ordinary data, and as a result, the urgent information cannot be transmitted in time, which causes damage to the host CPU or the server motherboard and irrecoverable loss.
The embodiment of the application discloses a bus scheduling method, which avoids bus blocking under an interrupt mechanism and simultaneously avoids that key information can not be transmitted in time under a polling mechanism.
Referring to fig. 2, a flowchart of a bus scheduling method is shown according to an exemplary embodiment, as shown in fig. 2, including:
s101: dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories;
in this step, a plurality of functional modules of the baseboard management control chip, except for the central processor and the memory module, which are connected to the system bus are divided into a plurality of categories, and different priorities are assigned to the functional modules of different categories. In the process of classifying the remaining functional modules except the BMC CPU and the DDR in the baseboard management control chip, different classifications may be performed according to the number and functions of specific modules and application scenarios, and the embodiment is not specifically limited.
As a possible implementation manner, the dividing the plurality of functional modules of the baseboard management control chip, except for the central processor and the memory module, connected to the system bus into a plurality of categories, and assigning different priorities to the functional modules of different categories includes: dividing a plurality of functional modules of the baseboard management control chip, except for a central processing unit and a storage module, which are connected to a system bus into a first category, a second category and a third category; the first category comprises a functional module which interacts with the storage module, the second category comprises a functional module which interacts with a host end, and the third category comprises a key information detection module; assigning different priorities to the different types of functional modules; the priority of the function modules of the third category is higher than that of the function modules of the second category, and the priority of the function modules of the second category is higher than that of the function modules of the first category.
The first category includes modules with large amounts of data, with the main data being interacted with the memory module, and the main data being read into and out of the memory module, such as Video Graphics Array (VGA), image file (JPEG), display interface (DP), etc. The second category includes functional modules that interact with the host side, such as any one or a combination of any of the LPC bus (low pin count bus ) module (linear predictive coding, LPC), universal serial bus module (USB), H2B module, management component transport protocol Module (MCTP). The third category includes critical information detection modules such as a multi-master-slave serial bus module (IIC), a universal asynchronous receiver transmitter module (UART), a pulse width modulation module (PWM), etc. The serial bus module with multiple master and slave functions is used for detecting the temperature of the main board, the voltage of the main board, the rotating speed of the fan and the information of the central processing unit. The modules are characterized in that the modules are used for monitoring and managing information on a host side and a server main board, transmitting the information to an application layer of a baseboard management control chip, knowing the information by a user, receiving configuration of upper software and managing related components on the server main board.
Furthermore, different priorities are allocated to different types of functional modules, and the embodiment does not limit the setting mode of the priorities, so that a user can flexibly set according to specific application scenes. For example, in the above classification method, the priority of the function module of the third class is set higher than the priority of the function module of the second class, and the priority of the function module of the second class is set higher than the priority of the function module of the first class.
S102: when an interrupt request of a first target functional module higher than a preset priority is received, distributing control rights of the system bus to the first target functional module;
in this step, an interrupt mechanism is used for the functional module higher than the preset priority, and when the baseboard management control chip receives an interrupt request of the first target functional module higher than the preset priority, the control right of the system bus is distributed to the first target functional module.
On the premise of the classification mode and the priority setting mode, when an interrupt request of a first target function module of the second category or the third category is received, the control right of the system bus is distributed to the first target function module.
When interrupt requests of a plurality of first target function modules with higher than a preset priority are received, the control right of the system bus is distributed to the first target function module with the highest priority.
S103: when an interrupt request of a first target functional module higher than the preset priority is not received, whether a functional module lower than the preset priority has a data transmission requirement or not is polled, and when a second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
In this step, when no interrupt is generated, a polling mechanism is adopted, that is, a polling mechanism is adopted for the functional modules lower than the preset priority, and when a second target functional module having a data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
On the premise of the classification mode and the priority setting mode, when the interrupt request of the first target function module of the second class or the third class is not received, whether the function module of the first class has a data transmission requirement or not is polled, and when the second target function module having the data transmission requirement is polled, the control right of the system bus is distributed to the second target function module.
On the basis of the present embodiment, as a preferred implementation manner, the method further includes: in the process of data transmission of the third target functional module, if an interrupt request of a fourth target functional module with higher than the preset priority is received, judging whether the priority of the fourth target functional module is higher than the priority of the third target functional module; and if the control right is higher than the control right, switching the control right of the system bus to the fourth target functional module. And after the data transmission of the fourth target functional module is completed, switching the control right of the system bus to the third target functional module.
In a specific implementation, when the low-priority data is transmitted, an interrupt with a high priority is generated, and the low priority needs to give out the bus control right, and the bus control right cannot be obtained again until the high-priority interrupt is processed.
According to the bus scheduling method provided by the embodiment of the application, each functional module is classified according to the characteristics of each functional module in the substrate management control chip, and different priorities are allocated to the functional modules of different categories. And scheduling the function module with higher priority by adopting an interrupt mechanism, ensuring that key information can be transmitted in time, and scheduling the function module with lower priority by adopting a polling mechanism, thereby avoiding system bus blocking. Therefore, the bus scheduling method provided by the embodiment of the application adopts the comprehensive scheduling strategy of combining local scheduling with overall scheduling, and the polling and the interruption are organically coordinated, namely, a timely exit detection mechanism for sudden interruption exists, so that the bus blockage is prevented while the priority output of emergency data is ensured, and the bus load of the substrate management control chip is ensured to the greatest extent.
The embodiment of the application discloses a bus scheduling method, and compared with the previous embodiment, the technical scheme is further described and optimized. Specific:
referring to fig. 3, a flowchart of another bus scheduling method is shown according to an exemplary embodiment, as shown in fig. 3, including:
s201: dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories;
s202: the method comprises the steps of dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of groups, and distributing different priorities to the functional modules of different groups.
In this embodiment, a plurality of functional modules connected to a system bus in a baseboard management control chip are divided into a plurality of categories, and different priorities are assigned to the functional modules of different categories. Meanwhile, a plurality of functional modules connected to a system bus in the baseboard management control chip are divided into a plurality of groups, different priorities are allocated to the functional modules in different groups, and each group contains all kinds of functional modules.
For example, the other functional modules except the BMC CPU and the DDR in the baseboard management control chip are divided into three types A, B, C, the type a module corresponds to a module with large data size, the main data is interacted with the DDR, the main data is a module interacted with the host end corresponding to the type B module for reading and reading the DDR, and the type C module corresponds to a detection module of key information on the motherboard. Grouping the modules of class A, B, C, the first group: a0, B0, C0, second group: a1, B1, C1, third group: a2, B2, C2, fourth group: the standard for the grouping A3, B3, C3 is that each group contains modules of the A, B, C class, so-called grouping is in fact a grouping in a virtual sense, since all modules are also mounted on the system bus. For example, A0 is VGA, A1 is JPEG, A2 is DP, A3 is EMAC, B0 is LPC, B1 is USB, B2 is H2B, B3 is MCTP, C0 is IIC, C1 is UART, C2 is PWM, and C3 is I3C.
S203: respectively receiving interrupt requests of a plurality of first target function modules with priorities higher than preset priorities in different groups by using sub-scheduling units corresponding to the different groups, and determining the first target function module with the highest priority in each group;
s204: and determining a first target function module with the highest priority from the first target function modules with the highest priority determined by different sub-scheduling units by utilizing the total scheduling unit, and distributing the control right of the system bus to the first target function module with the highest priority.
S205: and utilizing the total scheduling unit to poll whether the functional module with the lower priority than the preset priority has the data transmission requirement, and distributing the control right of the system bus to a second target functional module when the second target functional module with the data transmission requirement is polled.
In a specific implementation, the CPU of the baseboard management control chip polls each functional module in turn in a polling manner. As shown in fig. 4, the baseboard management control chip bus load balancing architecture is that the virtual packet corresponds to the bus arbitration priority, the priority of class C is highest, the priority of class B is lowest, and the priority of class a is lowest. Among the classes C, the priority of C0 is highest, and C1 times are sequentially set. When interrupts are generated in group 0, i.e. both B0 and C0, i.e. all the system bus controllers need to be obtained, analysis is performed by using the local_sch module, i.e. the sub-scheduling unit, and at this time, the priority of C0 is the highest, C0 corresponds to monitoring information of key components on the server motherboard, and the condition for generating interrupts by C0 is: compared with the traditional scheme, the C0 needs to additionally add an abnormal condition detection function, and receives the register configuration of the CPU of the baseboard management control chip, such as C0 is responsible for detecting the temperature information of the CPU of the host computer, and an additional hardware abnormal condition detection module is needed, wherein the module receives the threshold temperature of the register configuration, such as 80 degrees, and simultaneously can detect the temperature information of the CPU of the host computer read back by the C0, if the temperature information is normally lower than 80 degrees, no interruption is generated, if the temperature information is higher than 80 degrees, the temperature is excessively high, the upper layer software needs to be timely processed, at the moment, the C0 needs to timely obtain the bus control right in the first time, at the moment, a polling mechanism needs to be broken, and a priority mechanism is entered. Meanwhile, the abnormality detection module needs to detect the interface between the C0 module and the system bus, and after detecting that abnormal information is read by upper software, the abnormality detection module needs to exit from an interrupt mode in time to give out bus control right. B0 corresponds to a module that interacts with the host, such as LPC, which is not available at all times, so that conventionally polling is sufficient and if so, an interrupt is triggered. Therefore, a corresponding data detection function needs to be added, namely, a data valid signal of a corresponding port is detected to be pulled high or a transmission enabling signal is detected to be pulled high, when data sent by a host end or data sent to the host end by a substrate management control chip are detected, interruption is required to be reported, and after data transmission is completed, interruption is required to be withdrawn in time, so that bus control right is given out. The data corresponding to A0 is to be written into or read from a storage module (DDR), and the data is often large in data size, so that the interrupt of the local scheduling module is not set, and the priority setting is performed in the center_sch module, that is, the polling detection is performed on A0, A1, A2 only when none of C0, C1, C2, B0, B1, and B2 is interrupted.
The bus control right allocation, scheduling, reclamation and the like of the functional module are completed by a sub-scheduling unit 0 (local_sch0). The cases of the group 1 A1, B1, C1, the group 2 A2, B2, C2, the group 3 A3, B3, C3 are the same as those of the group 0 A0, B0, C0, except that the sub-scheduling units correspond to the sub-scheduling unit 1 (lo_sch1), the sub-scheduling unit 2 (local_sch2), and the sub-scheduling unit 3 (local_sch3), respectively. The CENTER SCH is the total scheduling unit and the function performed by this module is to collect and aggregate the scheduling information of the 4 sub-scheduling units local_sch0, local_sch1, local_sch2, local_sch3 for final allocation scheduling and reclamation. The final bus control right can be determined by a arbitration mechanism with highest priority of the 0 th group, namely the highest priority of C0 in the C class, the highest priority of B0 in the B class and the highest priority of A0 in the A class, and the interrupt exit of each corresponding local scheduling unit is timely detected, and when the interrupt of the packet with high priority exits, the bus control right is given to the packet with secondary priority.
Therefore, the embodiment provides a comprehensive scheduling strategy of the system bus of the baseboard management control chip by combining local scheduling with overall scheduling, avoids bus blocking under an interrupt mechanism, simultaneously avoids the defect that key information cannot be timely transmitted under a polling mechanism, provides an interrupt and timely exit mechanism under an autonomous detection mode, greatly improves the bus load balancing capability of the baseboard management control chip, improves the bus utilization rate, and ensures the timely transmission of the key information.
The embodiment of the application discloses a baseboard management control chip, which comprises a plurality of functional modules, a plurality of sub-scheduling units and a total scheduling unit, wherein the functional modules are divided into a plurality of categories, the functional modules of different categories correspond to different priorities, the functional modules of the same category are divided into a plurality of groups, the functional modules of different groups correspond to different priorities, and each group comprises all the functional modules of the categories;
the sub-scheduling unit is used for receiving interrupt requests of a plurality of first target function modules which are higher than a preset priority in the corresponding packet, and determining the first target function module with the highest priority in each packet;
the total scheduling unit is used for determining a first target functional module with the highest priority among the first target functional modules with the highest priority determined by different sub-scheduling units, and distributing the control right of the system bus to the first target functional module with the highest priority;
the total scheduling unit is further configured to poll whether a functional module with a lower priority than the preset priority has a data transmission requirement when an interrupt request of a first target functional module with a higher priority than the preset priority is not received, and allocate control rights of the system bus to a second target functional module with the data transmission requirement when the second target functional module with the data transmission requirement is polled.
Referring to fig. 4, local_sch0, local_sch1, local_sch2, local_sch3 are four sub-scheduling units, and center_sch is a total scheduling unit. All the functional modules are divided into three categories, wherein the priority of the category C is highest, the priority of the category B is next highest, and the priority of the category A is lowest. Meanwhile, all the functional modules are divided into four packets, the priority of the packets scheduled by local_SCH0 is highest, and the priority of the packets scheduled by local_SCH1 is sequentially set. The total scheduling unit CENTER SCH collects and gathers scheduling information of 4 sub scheduling units local_sch0, local_sch1, local_sch2, local_sch3 for final allocation scheduling and reclamation.
The following describes a bus scheduling apparatus provided in the embodiments of the present application, and a bus scheduling apparatus described below and a bus scheduling method described above may be referred to each other.
Referring to fig. 5, a block diagram of a bus scheduler according to an exemplary embodiment is shown, as shown in fig. 5, including:
a first dividing module 501, configured to divide a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and allocate different priorities to the functional modules in different categories;
A first allocation module 502, configured to allocate, when an interrupt request of a first target function module higher than a preset priority is received, control rights of the system bus to the first target function module;
and a second allocation module 503, configured to poll whether a functional module lower than the preset priority has a data transmission requirement when an interrupt request of a first target functional module higher than the preset priority is not received, and allocate control rights of the system bus to a second target functional module having the data transmission requirement when the second target functional module is polled.
According to the bus scheduling device provided by the embodiment of the application, each functional module is classified according to the characteristics of each functional module in the substrate management control chip, and different priorities are allocated to the functional modules of different categories. And scheduling the function module with higher priority by adopting an interrupt mechanism, ensuring that key information can be transmitted in time, and scheduling the function module with lower priority by adopting a polling mechanism, thereby avoiding system bus blocking. Therefore, the bus scheduling device provided by the embodiment of the application adopts a comprehensive scheduling strategy of matching local scheduling with overall scheduling, and the polling and the interruption are organically coordinated, namely, a timely exit detection mechanism for sudden interruption exists, so that the bus blockage is prevented while the priority output of emergency data is ensured, and the bus load of the substrate management control chip is ensured to the greatest extent.
Based on the foregoing embodiment, as a preferred implementation manner, the first dividing module 501 is specifically configured to: the method comprises the steps of dividing a plurality of functional modules, except a central processing unit and a storage module, connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules in different categories.
Based on the foregoing embodiment, as a preferred implementation manner, the first dividing module 501 is specifically configured to: dividing a plurality of functional modules of the baseboard management control chip, except for a central processing unit and a storage module, which are connected to a system bus into a first category, a second category and a third category; the first category comprises a functional module which interacts with the storage module, the second category comprises a functional module which interacts with a host end, and the third category comprises a key information detection module; assigning different priorities to the different types of functional modules; the priority of the function modules of the third category is higher than that of the function modules of the second category, and the priority of the function modules of the second category is higher than that of the function modules of the first category.
Based on the foregoing embodiment, as a preferred implementation manner, the memory module is specifically a double-rate synchronous dynamic random access memory.
On the basis of the above embodiment, as a preferred implementation manner, the functional modules of the first category include any one or a combination of any several of a video graphics array module, an image file module and a display interface module.
Based on the above embodiments, as a preferred implementation manner, the second class of functional modules includes any one or a combination of any several of an LPC bus module, a universal serial bus module, an H2B module, and a management component transmission protocol module.
Based on the above embodiments, as a preferred implementation manner, the third class of functional modules includes any one or a combination of any several of a serial bus module with multiple master and slave, a universal asynchronous receiver transmitter module, and a pulse width modulation module.
Based on the above embodiment, as a preferred implementation manner, the multi-master serial bus module is configured to detect any one or a combination of any two of a motherboard temperature, a motherboard voltage, a fan speed, and cpu information.
Based on the foregoing embodiment, as a preferred implementation manner, the first allocation module 502 is specifically configured to: and when receiving the interrupt request of the first target functional module of the second category or the third category, distributing the control right of the system bus to the first target functional module.
On the basis of the above embodiment, as a preferred implementation manner, the second allocation module 503 is specifically configured to: when the interrupt request of the first target functional module of the second category or the third category is not received, the functional module of the first category is polled whether the data transmission requirement exists, and when the second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
Based on the foregoing embodiment, as a preferred implementation manner, the first allocation module 502 is specifically configured to: when interrupt requests of a plurality of first target function modules with higher than preset priority are received, the control right of the system bus is distributed to the first target function module with the highest priority.
On the basis of the above embodiment, as a preferred implementation manner, the method further includes:
And the second dividing module is used for dividing the plurality of functional modules connected to the system bus in the baseboard management control chip into a plurality of groups and distributing different priorities to the functional modules of different groups.
On the basis of the above embodiment, as a preferred implementation, each group contains all kinds of functional modules.
Based on the foregoing embodiment, as a preferred implementation manner, the first allocation module 502 is specifically configured to: respectively receiving interrupt requests of a plurality of first target function modules with priorities higher than preset priorities in different groups by using sub-scheduling units corresponding to the different groups, and determining the first target function module with the highest priority in each group; and determining a first target function module with the highest priority from the first target function modules with the highest priority determined by different sub-scheduling units by utilizing the total scheduling unit, and distributing the control right of the system bus to the first target function module with the highest priority.
On the basis of the above embodiment, as a preferred implementation manner, the second allocation module 503 is specifically configured to: when an interrupt request of a first target function module higher than the preset priority is not received, the total scheduling unit is utilized to poll whether a function module lower than the preset priority has a data transmission requirement, and when a second target function module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target function module.
On the basis of the above embodiment, as a preferred implementation manner, the method further includes:
the first switching module is used for judging whether the priority of the fourth target functional module is higher than the priority of the third target functional module if an interrupt request of the fourth target functional module higher than the preset priority is received in the process of data transmission of the third target functional module; and if the control right is higher than the control right, switching the control right of the system bus to the fourth target functional module.
And the second switching module is used for switching the control right of the system bus to the third target functional module after the data transmission of the fourth target functional module is completed.
The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.
Based on the hardware implementation of the program modules, and in order to implement the method of the embodiments of the present application, the embodiments of the present application further provide an electronic device, fig. 6 is a block diagram of an electronic device according to an exemplary embodiment, and as shown in fig. 6, the electronic device includes:
A communication interface 1 capable of information interaction with other devices such as network devices and the like;
and the processor 2 is connected with the communication interface 1 to realize information interaction with other devices and is used for executing the bus scheduling method provided by one or more technical schemes when running the computer program. And the computer program is stored on the memory 3.
Of course, in practice, the various components in the electronic device are coupled together by a bus system 4. It will be appreciated that the bus system 4 is used to enable connected communications between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. But for clarity of illustration the various buses are labeled as bus system 4 in fig. 6.
The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.
It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 3 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.
The method disclosed in the embodiments of the present application may be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 2 or by instructions in the form of software. The processor 2 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium in the memory 3 and the processor 2 reads the program in the memory 3 to perform the steps of the method described above in connection with its hardware.
The processor 2 implements corresponding flows in the methods of the embodiments of the present application when executing the program, and for brevity, will not be described in detail herein.
In an exemplary embodiment, the present application also provides a storage medium, i.e. a computer storage medium, in particular a computer readable storage medium, for example comprising a memory 3 storing a computer program executable by the processor 2 for performing the steps of the method described above. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, CD-ROM, etc.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.
Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (21)
1. A bus scheduling method, comprising:
dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules of different categories;
when an interrupt request of a first target functional module higher than a preset priority is received, distributing control rights of the system bus to the first target functional module;
when an interrupt request of a first target functional module higher than the preset priority is not received, whether a functional module lower than the preset priority has a data transmission requirement or not is polled, and when a second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
2. The bus scheduling method as set forth in claim 1, wherein the dividing the plurality of functional modules connected to the system bus in the baseboard management control chip into a plurality of categories, assigning different priorities to the functional modules in the different categories, comprises:
the method comprises the steps of dividing a plurality of functional modules, except a central processing unit and a storage module, connected to a system bus in a baseboard management control chip into a plurality of categories, and distributing different priorities for the functional modules in different categories.
3. The bus scheduling method as set forth in claim 2, wherein the dividing the plurality of functional modules of the baseboard management control chip except for the central processor and the memory module connected to the system bus into a plurality of categories, assigning different priorities to the functional modules of different categories, comprises:
dividing a plurality of functional modules of the baseboard management control chip, except for a central processing unit and a storage module, which are connected to a system bus into a first category, a second category and a third category; the first category comprises a functional module which interacts with the storage module, the second category comprises a functional module which interacts with a host end, and the third category comprises a key information detection module;
Assigning different priorities to the different types of functional modules; the priority of the function modules of the third category is higher than that of the function modules of the second category, and the priority of the function modules of the second category is higher than that of the function modules of the first category.
4. The bus scheduling method of claim 2, wherein the memory module is embodied as a double rate synchronous dynamic random access memory.
5. A bus scheduling method according to claim 3 wherein the first class of functional modules comprises any one or a combination of video graphics array modules, image file modules, display interface modules.
6. A bus scheduling method according to claim 3 wherein the second class of functional modules comprises any one or a combination of several of an LPC bus module, a universal serial bus module, an H2B module, a management component transport protocol module.
7. A bus scheduling method according to claim 3 wherein the third class of functional modules comprises any one or a combination of several of a multi-master serial bus module, a universal asynchronous receiver transmitter module, a pulse width modulation module.
8. The bus scheduling method of claim 7, wherein the multi-master serial bus module is configured to detect any one or a combination of any two of a motherboard temperature, a motherboard voltage, a fan speed, and cpu information.
9. The bus scheduling method according to claim 3, wherein the allocating control right of the system bus to the first target function module when receiving the interrupt request of the first target function module higher than a preset priority, comprises:
and when receiving the interrupt request of the first target functional module of the second category or the third category, distributing the control right of the system bus to the first target functional module.
10. A bus scheduling method according to claim 3, wherein when an interrupt request of a first target function module higher than the preset priority is not received, polling whether a function module lower than the preset priority has a data transmission demand, and when a second target function module having a data transmission demand is polled, assigning control of the system bus to the second target function module comprises:
When the interrupt request of the first target functional module of the second category or the third category is not received, the functional module of the first category is polled whether the data transmission requirement exists, and when the second target functional module with the data transmission requirement is polled, the control right of the system bus is distributed to the second target functional module.
11. The bus scheduling method according to claim 1, wherein the allocating the control right of the system bus to the first target function module when receiving the interrupt request of the first target function module higher than a preset priority, comprises:
when interrupt requests of a plurality of first target function modules with higher than preset priority are received, the control right of the system bus is distributed to the first target function module with the highest priority.
12. The bus scheduling method of claim 11, further comprising:
the method comprises the steps of dividing a plurality of functional modules connected to a system bus in a baseboard management control chip into a plurality of groups, and distributing different priorities to the functional modules of different groups.
13. The bus scheduling method of claim 12, wherein each packet contains all classes of functional modules.
14. The bus scheduling method as set forth in claim 12, wherein when interrupt requests of a plurality of first target function modules higher than a preset priority are received, assigning control rights of the system bus to the first target function module having the highest priority, comprising:
respectively receiving interrupt requests of a plurality of first target function modules with priorities higher than preset priorities in different groups by using sub-scheduling units corresponding to the different groups, and determining the first target function module with the highest priority in each group;
and determining a first target function module with the highest priority from the first target function modules with the highest priority determined by different sub-scheduling units by utilizing the total scheduling unit, and distributing the control right of the system bus to the first target function module with the highest priority.
15. The bus scheduling method of claim 14, wherein the polling whether a functional module having a lower priority than the preset priority has a data transmission requirement, and when polling a second target functional module having a data transmission requirement, assigning control of the system bus to the second target functional module, comprises:
and utilizing the total scheduling unit to poll whether the functional module with the lower priority than the preset priority has the data transmission requirement, and distributing the control right of the system bus to a second target functional module when the second target functional module with the data transmission requirement is polled.
16. The bus scheduling method of claim 1, further comprising:
in the process of data transmission of the third target functional module, if an interrupt request of a fourth target functional module with higher than the preset priority is received, judging whether the priority of the fourth target functional module is higher than the priority of the third target functional module;
and if the control right is higher than the control right, switching the control right of the system bus to the fourth target functional module.
17. The bus scheduling method of claim 16, further comprising, after switching control of the system bus to the fourth target function module:
and after the data transmission of the fourth target functional module is completed, switching the control right of the system bus to the third target functional module.
18. A bus scheduler, comprising:
the first dividing module is used for dividing a plurality of functional modules connected to the system bus in the baseboard management control chip into a plurality of categories and distributing different priorities to the functional modules in different categories;
the first allocation module is used for allocating the control right of the system bus to the first target functional module when receiving an interrupt request of the first target functional module with higher than a preset priority;
And the second allocation module is used for polling whether the function module with the lower priority has data transmission requirements or not when the interrupt request of the first target function module with the higher priority is not received, and allocating the control right of the system bus to the second target function module when the second target function module with the data transmission requirements is polled.
19. An electronic device, comprising:
a memory for storing a computer program;
processor for implementing the steps of the bus scheduling method according to any one of claims 1 to 17 when executing said computer program.
20. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the bus scheduling method of any of claims 1 to 17.
21. The substrate management control chip is characterized by comprising a plurality of functional modules, a plurality of sub-scheduling units and a total scheduling unit, wherein the functional modules are divided into a plurality of categories, the functional modules in different categories correspond to different priorities, the functional modules in the same category are divided into a plurality of groups, the functional modules in different groups correspond to different priorities, and each group comprises all the functional modules in the category;
The sub-scheduling unit is used for receiving interrupt requests of a plurality of first target function modules which are higher than a preset priority in the corresponding packet, and determining the first target function module with the highest priority in each packet;
the total scheduling unit is used for determining a first target function module with the highest priority among the first target function modules with the highest priority determined by different sub-scheduling units, and distributing the control right of the system bus to the first target function module with the highest priority;
the total scheduling unit is further configured to poll whether a functional module with a lower priority than the preset priority has a data transmission requirement when an interrupt request of a first target functional module with a higher priority than the preset priority is not received, and allocate control rights of the system bus to a second target functional module with the data transmission requirement when the second target functional module with the data transmission requirement is polled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310431057.6A CN116185915B (en) | 2023-04-21 | 2023-04-21 | Bus scheduling method, device and equipment, medium and baseboard management control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310431057.6A CN116185915B (en) | 2023-04-21 | 2023-04-21 | Bus scheduling method, device and equipment, medium and baseboard management control chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116185915A true CN116185915A (en) | 2023-05-30 |
| CN116185915B CN116185915B (en) | 2023-08-04 |
Family
ID=86442631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310431057.6A Active CN116185915B (en) | 2023-04-21 | 2023-04-21 | Bus scheduling method, device and equipment, medium and baseboard management control chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116185915B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5218703A (en) * | 1988-07-07 | 1993-06-08 | Siemens Aktiengesellschaft | Circuit configuration and method for priority selection of interrupts for a microprocessor |
| US20050097226A1 (en) * | 2003-10-31 | 2005-05-05 | Sun Microsystems, Inc. | Methods and apparatus for dynamically switching between polling and interrupt to handle network traffic |
| US20060200610A1 (en) * | 2005-02-04 | 2006-09-07 | Sony Computer Entertainment Inc. | System and method of interrupt handling |
| CN106569897A (en) * | 2016-11-07 | 2017-04-19 | 许继集团有限公司 | Shared bus polling method and device based on collaborative multi-task scheduling mechanism |
| CN111639044A (en) * | 2020-05-22 | 2020-09-08 | 中国人民解放军国防科技大学 | Method and device for supporting interrupt priority polling arbitration dispatching |
| CN112506821A (en) * | 2020-09-27 | 2021-03-16 | 山东云海国创云计算装备产业创新中心有限公司 | System bus interface request arbitration method and related components |
| CN113687944A (en) * | 2021-07-29 | 2021-11-23 | 山东云海国创云计算装备产业创新中心有限公司 | Task execution method, device, equipment and medium for baseboard management control chip |
| CN113852564A (en) * | 2021-11-29 | 2021-12-28 | 苏州浪潮智能科技有限公司 | Server control method, device and medium |
| US20230064411A1 (en) * | 2020-06-24 | 2023-03-02 | Inspur (Beijing) Electronic Information Industry Co., Ltd. | I2c bus communication control method, device and system, and readable storage medium |
-
2023
- 2023-04-21 CN CN202310431057.6A patent/CN116185915B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5218703A (en) * | 1988-07-07 | 1993-06-08 | Siemens Aktiengesellschaft | Circuit configuration and method for priority selection of interrupts for a microprocessor |
| US20050097226A1 (en) * | 2003-10-31 | 2005-05-05 | Sun Microsystems, Inc. | Methods and apparatus for dynamically switching between polling and interrupt to handle network traffic |
| US20060200610A1 (en) * | 2005-02-04 | 2006-09-07 | Sony Computer Entertainment Inc. | System and method of interrupt handling |
| CN106569897A (en) * | 2016-11-07 | 2017-04-19 | 许继集团有限公司 | Shared bus polling method and device based on collaborative multi-task scheduling mechanism |
| CN111639044A (en) * | 2020-05-22 | 2020-09-08 | 中国人民解放军国防科技大学 | Method and device for supporting interrupt priority polling arbitration dispatching |
| US20230064411A1 (en) * | 2020-06-24 | 2023-03-02 | Inspur (Beijing) Electronic Information Industry Co., Ltd. | I2c bus communication control method, device and system, and readable storage medium |
| CN112506821A (en) * | 2020-09-27 | 2021-03-16 | 山东云海国创云计算装备产业创新中心有限公司 | System bus interface request arbitration method and related components |
| CN113687944A (en) * | 2021-07-29 | 2021-11-23 | 山东云海国创云计算装备产业创新中心有限公司 | Task execution method, device, equipment and medium for baseboard management control chip |
| CN113852564A (en) * | 2021-11-29 | 2021-12-28 | 苏州浪潮智能科技有限公司 | Server control method, device and medium |
Non-Patent Citations (1)
| Title |
|---|
| 苏永海;黄莉;: "基于PCI Express的多通道动态优先级DMA系统的FPGA设计", 通信技术, no. 07 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116185915B (en) | 2023-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3699833B2 (en) | Priority encoding and decoding for memory architecture | |
| US9367517B2 (en) | Integrated circuit package with multiple dies and queue allocation | |
| CN102567109B (en) | Interrupt distribution scheme | |
| EP2333673B1 (en) | Signal sampling and transfer | |
| US8060679B2 (en) | Information processing apparatus and access control method capable of high-speed data access | |
| US8504751B2 (en) | Integrated circuit package with multiple dies and interrupt processing | |
| US6826640B1 (en) | Bus bandwidth control system | |
| US7617344B2 (en) | Methods and apparatus for controlling access to resources in an information processing system | |
| US9703736B2 (en) | Data transmission apparatus, communication control method, and communication control program | |
| US8213461B2 (en) | Method of designating slots in a transmission frame for controlling transmission of data over an interconnect coupling a plurality of master units with a plurality of slave units | |
| CN107480078B (en) | bus bandwidth allocation method, device and chip | |
| KR100480605B1 (en) | Method of controlling transmitting buffer and receiving buffer of network controller, and the network controller | |
| EP3326347B1 (en) | Method and system for usb 2.0 bandwidth reservation | |
| KR20160112305A (en) | Method for arbitrating shared resource access and shared resource access arbitration apparatus and shared resource apparatus access arbitration system for performing the same | |
| US8468381B2 (en) | Integrated circuit package with multiple dies and a synchronizer | |
| CN116185915B (en) | Bus scheduling method, device and equipment, medium and baseboard management control chip | |
| KR20170117326A (en) | Direct memory access control device for at least one processing unit having a random access memory | |
| CN115878333A (en) | Method, device and equipment for judging consistency between process groups | |
| US11144486B2 (en) | System and method for overcoming in-band interrupt starvation with dynamic address remapping | |
| TW201621675A (en) | Data processing method and system with application-level information awareness | |
| JP2000250853A (en) | Bus arbitration controller | |
| CN114968840B (en) | Memory usage amount control method and system | |
| US20240163231A1 (en) | Electronic apparatus and control method for managing available pointers of packet buffer | |
| US20070245052A1 (en) | System and method for bandwidth sharing in busses | |
| CN117234989A (en) | Data transmission method, system, medium and terminal based on high-speed serial bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |