CN116185439A

CN116185439A - Electronic device and updating method

Info

Publication number: CN116185439A
Application number: CN202111430126.9A
Authority: CN
Inventors: 吴明宗
Original assignee: Getac Technology Corp
Current assignee: Getac Technology Corp
Priority date: 2021-11-29
Filing date: 2021-11-29
Publication date: 2023-05-30

Abstract

The embodiment of the invention discloses an electronic device and an updating method, wherein the electronic device with a connector supporting multiple connection standards comprises a connector, a processor, a controller, an extended display capability identification read-only memory, a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is coupled to at least one signal pin of the connector, the processor and the controller. The second multiplexing circuit is coupled to the extended display capability identification ROM, the first multiplexing circuit, the processor and the controller. In the update state, the controller is electrically connected to the extended display capability recognition read-only memory through the second multiplexing circuit, and updates the extended display capability recognition data in the extended display capability recognition read-only memory with the update data.

Description

Electronic device and updating method

Technical Field

Embodiments of the present invention relate to an electronic device with a connector supporting multiple connection standards, and more particularly, to an electronic device and an updating method.

Background

Conventionally, the standard display device has an extended display capability recognition read-only memory, and the extended display capability recognition read-only memory stores therein extended display capability recognition data (Extended Display Identification Data, EDID). When the image source device is connected with the standard display device, the image source device can read the extended display capability identification data in the standard display device to obtain the display information of the standard display device, so as to provide the consistent image to the standard display device.

However, in the special display device, the extended display capability identification read only memory is not provided, but is instead provided in the image source device. In this case, if the extended display capability identification data for a specific display device is to be updated, it is necessary to perform the updating through the image source device.

In addition, conventionally, when the image source device is to support multiple connection standards, a corresponding connector is required to be set for each connection standard. However, the more connectors that are required, the more bulky and costly the image source device becomes.

Furthermore, although the image source device may use a Displayport (Displayport) connector with a custom mounting pin to connect to a special display device, the Displayport connector has a large occupied area in the input/output panel, and the Displayport connector discards a standard high-resolution multimedia interface-display data channel Bus (HDMI-DDC Bus) due to the pin limitation of the Displayport connector, so that the image source device cannot be connected to a standard display device using a standard Displayport connector or a standard high-resolution multimedia interface (HDMI) connector. Thus, the application of the system end user is not flexible.

Disclosure of Invention

The invention provides an electronic device and an updating method, which can realize that a controller can update extended display capacity identification read-only memory built in the electronic device with a connector supporting multiple connection standards under the updating state by updating data.

In a first aspect, an embodiment of the present invention provides an electronic device having a connector supporting multiple connection standards. An electronic device having a connector supporting multiple connection standards includes a connector, a processor, a controller, an extended display capability identification read only memory, a first multiplexing circuit, and a second multiplexing circuit. The connector includes at least one signal pin. The controller is coupled to the processor. The extended display capability identification read-only memory is used for storing the extended display capability identification data. The first multiplexing circuit is coupled to at least one signal pin, the processor and the controller. The second multiplexing circuit is coupled to the extended display capability identification ROM, the first multiplexing circuit, the processor and the controller. In the update state, the controller is electrically connected to the extended display capability recognition read-only memory through the second multiplexing circuit, and updates the extended display capability recognition data in the extended display capability recognition read-only memory with the update data.

In a second aspect, an embodiment of the present invention provides a method for updating an electronic device having a connector supporting multiple connection standards. The updating method comprises the following steps: in the update state, the extended display capability identification read-only memory is updated with update data via the second multiplexing circuit by the controller.

In summary, the electronic device with the connector supporting multiple connection standards and the updating method thereof according to the embodiments of the present invention can establish the link path between the controller and the extended display capability recognition read-only memory by switching the multiplexing circuit, so that the controller can update the extended display capability recognition read-only memory built in the electronic device with the connector supporting multiple connection standards with updated data in the updated state. In addition, in the electronic device with the connector supporting multiple connection standards and the updating method thereof provided by the embodiment of the invention, the processor can be manually caused to send the updating data to the controller so as to enter the updating state, and the controller can automatically judge whether to enter the updating state according to the extended display capability identification data after receiving the device signal. In particular, after the controller enters an update state due to the judgment result, the controller can acquire corresponding update data according to the device signal and automatically update the corresponding update data. In addition, the electronic device with the connector supporting multiple connection standards and the updating method thereof provided by the embodiment of the invention switch the transmission path of at least one signal pin of the connector according to whether the device signal is received, so that a single connector can support multiple connection standards, and the electronic device can transmit with the standard device or a special device through the single connector, and can select one application from the multiple connection standards.

The detailed features and advantages of the present invention will be readily apparent to those skilled in the art from that description, that is, the objects and advantages of the invention will be readily apparent to those skilled in the art from the following detailed description, claims, and drawings.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device connected to an external device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating an update method according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating another updating method according to an embodiment of the present invention;

FIG. 5 is a flowchart of another method for updating according to an embodiment of the present invention;

fig. 6 is a flowchart of step S06 of the update method according to the embodiment of the present invention;

FIG. 7 is a flowchart of a further updating method according to an embodiment of the present invention;

fig. 8 is a schematic diagram of an execution flow of the update method according to the embodiment of the present invention after determining that the specification is not met in step S10;

fig. 9 is a schematic flow chart after step S22 of the update method according to the embodiment of the present invention;

Fig. 10 is a schematic diagram of an execution flow of the update method according to the embodiment of the present invention after determining that the specification is not met in step S10;

fig. 11 is a schematic diagram of an execution flow of the update method provided in the embodiment of the present invention after step S31;

fig. 12 is a schematic diagram of a power supply circuit according to an embodiment of the present invention;

fig. 13 is a schematic diagram of another power supply circuit according to an embodiment of the invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings. .

Fig. 1 is a schematic structural diagram of connection between an electronic device and an external device according to an embodiment of the present invention, where the embodiment is applicable to a case of updating an extended display capability recognition rom. Referring to fig. 1, an electronic device 100 with a connector supporting multiple connection standards includes a connector 101, a processor 102, a controller 103, an extended display capability recognition read only memory 104, and at least two multiplexing circuits (hereinafter referred to as a first multiplexing circuit 105 and a second multiplexing circuit 106, respectively). Wherein the controller 103 is coupled to the processor 102. The first multiplexing circuit 105 is coupled to the connector 101, the processor 102, and the controller 103. And, the second multiplexing circuit 106 is coupled to the extended display capability recognition ROM 104, the first multiplexing circuit 105, the processor 102 and the controller 103.

The connector 101 is disposed in a housing of the electronic device 100 and is adapted to be connected to an external device having a corresponding connector, so that transmission between the electronic device 100 and the external device is enabled. In some embodiments, the external device may be another electronic device with a corresponding connector and be connected to or disconnected from the connector 101 of the electronic device 100 by plugging, but the invention is not limited thereto. In other embodiments, the external device 300 may be an external device 300, and the external device 300 is connected to one end of the transmission line 200 and is connected to or disconnected from the electronic device 100 by plugging the other end of the transmission line 200 into or out of the connector 101. Hereinafter, the external device is described as an example in which the external device 300 is connected to or separated from the electronic device 100 through the transmission line 200, but this is not a limitation of the present invention.

The connector 101 includes at least one signal pin P1. The processor 102 may include a first interface CPU_I1 and a second interface CPU_I2 that employ different connection standards. Also, the controller 103 includes a first interface mcu_i1 and a second interface mcu_i2 employing different connection standards.

Here, the first multiplexing circuit 105 is coupled to the signal pin P1 of the connector 101, the first interface cpu_i1 of the processor 102, the first interface mcu_i1 of the controller 103, the second interface mcu_i2 of the controller 103, and the second multiplexing circuit 106, and the first multiplexing circuit 105 can selectively electrically connect the signal pin P1 to the first interface cpu_i1 of the processor 102, the first interface mcu_i1 of the controller 103, the second interface mcu_i2 of the controller 103, or the second multiplexing circuit 106 according to the selection signal SEL1 from the controller 103. In addition, the second multiplexing circuit 106 is coupled to the second interface cpu_i2 of the processor 102, the first interface mcu_i1 of the controller 103, the extended display capability recognition read-only memory 104 and the first multiplexing circuit 105, and the second multiplexing circuit 106 can selectively electrically connect the second interface cpu_i2 of the processor 102 to the extended display capability recognition read-only memory 104 or the first multiplexing circuit 105, or selectively electrically connect the first interface mcu_i1 of the controller 103 to the extended display capability recognition read-only memory 104.

Fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. Referring to fig. 2, in some embodiments, the second multiplexer circuit 106 may include at least two multiplexers (hereinafter referred to as a first multiplexer 106A and a second multiplexer 106B, respectively). The first multiplexer 106A is coupled to the first multiplexer 105, the extended display capability recognition ROM 104 and the controller 103, and the second multiplexer 106B is coupled to the first multiplexer 106A, the second interface CPU_I2 of the processor 102 and the first interface MCU_I1 of the controller 103. The first multiplexer 106A may selectively electrically connect the second multiplexer 106B to the extended display capability recognition read only memory 104 or the first multiplexer circuit 105 according to the selection signal SEL2 from the controller 103, and the second multiplexer 106B may selectively electrically connect the second interface cpu_i2 of the processor 102 or the first interface mcu_i1 of the controller 103 to the first multiplexer 106A according to the selection signal SEL3 from the controller 103.

In the initial state of the electronic device 100, the controller 103 may normally generate the selection signal SEL1 having the first setting value to the first multiplexing circuit 105, so as to control the first multiplexing circuit 105 to normally control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the first interface mcu_i1 of the controller 103. In addition, the controller 103 may normally generate the selection signal SEL2 having the first selection value to the first multiplexer 106A of the second multiplexer 106 to control the first multiplexer 106A to normally electrically connect the second multiplexer 106B to the extended display capability recognition read only memory 104, and normally generate the selection signal SEL3 having the second selection value to the second multiplexer 106B of the second multiplexer 106 to control the second multiplexer 106B to normally electrically connect the processor 102 to the first multiplexer 106A, so that the second interface cpu_i2 of the processor 102 may be sequentially electrically connected to the extended display capability recognition read only memory 104 through the second multiplexer 106B and the first multiplexer 106A.

In some implementations, the first selection value may be a logic "0" and the second selection value may be a logic "1", but the present invention is not limited thereto, and the first selection value and the second selection value may be designed according to the use requirement.

In some embodiments, the electronic device 100 may further include a voltage Level shifter (Level Shift) 107, and the voltage Level shifter 107 is coupled between the second interface cpu_i2 of the processor 102 and the second multiplexer 106B of the second multiplexer circuit 106. In other words, the second multiplexer 106B of the second multiplexer 106 may also be coupled to the second interface cpu_i2 of the processor 102 via the voltage level shifter 107.

In some embodiments, the voltage level shifter 107 may be used to shift the voltage level. For example, when the second interface cpu_i2 of the processor 102 is electrically connected to the connection path between the signal pin P1 through the voltage level shifter 107 and the second multiplexing circuit 106 to be used as a display data channel, the external device 300 can transmit an extended display capability identification data to the processor 102 through the connection path, and the voltage level shifter 107 can perform voltage level conversion (e.g. 5 v to 3 v) on the received extended display capability identification data, and then transmit the converted extended display capability identification data to the processor 102.

In some embodiments, the connector 101 may further include an image pin P5, and the voltage level shifter 107 may be further coupled to the image pin P5 and the controller 104. Here, the voltage level shifter 107 may be used as a Repeater (Repeater). The voltage level shifter 107 receives the selection signal SEL3 from the controller 103 and selectively generates a notification signal hdmi_hpd to the processor 102 according to the selection signal SEL 3. Wherein, when the selection signal SEL3 has a first selection value, the voltage level shifter 107 does not output the notification signal hdmi_hpd, and when the selection signal SEL3 has a second selection value, the voltage level shifter 107 outputs the notification signal hdmi_hpd to the processor 102. After receiving the notification signal hdmi_hpd, the processor 102 outputs the image data D2 to the voltage level shifter 107, and the voltage level shifter 107 enhances the image data D2, and outputs the enhanced image data D2 to the external device 300 through the image pin P5 of the connector 101, so that the external device 300 displays the corresponding image and audio. However, the invention is not limited thereto, and in other embodiments, the processor 102 may directly output the image data D2 to the image pin P5 of the connector 101 according to the instruction of the controller 103.

In some embodiments, the electronic device 100 may be a digital image recorder (Digital Video Recorder) or a computer, and the external device 300 may be various screens, such as a touch screen, a display screen, etc. The connector 101 may be a standard High-resolution multimedia interface (High-Definition Multimedia Interface AType, HDMIAType) port, the signal pin P1 may be a 15 th pin and a 16 th pin of the standard High-resolution multimedia interface port as display data channels (Display Data Channel, DDC), and the image pin P5 may be a 1 st pin to a 12 th pin of the standard High-resolution multimedia interface port for transmitting minimized differential signals (Time Minimized Differential Signal, TMDS). The processor 102 may be implemented by a System on Chip (SoC), a central processing unit (Central Processing Unit, CPU), a Microprocessor (Microprocessor), an application processor (Application Processor, AP), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or a combination thereof, but the invention is not limited thereto, and the processor 102 may be any suitable core circuit in the electronic device 100 for performing various operations and functions. The controller 103 may be implemented by a microcontroller (Micro Controller Unit, MCU), a keyboard controller (Keyboard Controller, KBC) or an embedded controller (Embedded Controller, EC), but the invention is not limited thereto, and the controller 103 may be any suitable control circuit for performing specific tasks. In addition, the voltage level shifter 107 can be implemented by an integrated chip to have both voltage level conversion and signal enhancement functions.

In some embodiments, the first interface MCU_I1 of the controller 103 may be a transmission interface using an integrated circuit bus (Inter-Integrated Circuit, I2C) connection standard, and the second interface MCU_I2 of the controller 103 may be a transmission interface using a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) connection standard. In addition, the first interface cpu_i1 of the processor 102 may be a transmission interface using a universal serial bus (Universal Serial Bus, USB) 2.0 connection standard, but the invention is not limited thereto.

The EDID ROM 104 is used to store an EDID. In some embodiments, when the external device 300 connected to the electronic device 100 does not have the extended display capability identification data, the processor 102 of the electronic device 100 can read the extended display capability identification read-only memory 104 to generate the image data D2 with the corresponding display specification according to the extended display capability identification data for displaying to the external device 300.

In some embodiments, the electronic device 100 may perform the updating method of any of the embodiments to update the extended display capability identification data in the extended display capability identification read only memory 104. In one embodiment, the update may be to update the old version of the extended display capability identification data stored in the extended display capability identification read-only memory 104 to a new version of the extended display capability identification data. In another embodiment, the updating may be to change the extended display capability identification data that does not conform to the specification of the external device 300 to the extended display capability identification data that conforms to the specification of the external device 300.

Fig. 3 is a flowchart of an update method according to an embodiment of the present invention. Referring to fig. 1 to 3, in some embodiments, in step S31, the electronic device 100 may update the extended display capability identification data in the extended display capability identification rom 104 with the update data D1 via the second multiplexing circuit 106 by the controller 103 in an updated state. The update data D1 may be new version of the extended display capability identification data or the extended display capability identification data conforming to the specification of the external device 300.

Fig. 4 is a flowchart of another updating method according to an embodiment of the present invention. Referring to fig. 1 to 4, in some embodiments, in step S22, the electronic device 100 may obtain an update data D1 by using the processor 102, and the processor 102 may transmit the update data D1 to the controller 103 via the bus B1 to update the rom 104 by the controller 103. In step S23, when the controller 103 receives the update data D1 from the processor 102, the controller 103 can control the second multiplexing circuit 106 to electrically connect the first interface mcu_i1 of the controller 103 to the extended display capability recognition read only memory 104, and then execute step S31, so that the controller 103 updates the extended display capability recognition read only memory 104 with the update data D1. Thus, in some embodiments, when the controller 103 receives the update data D1 from the processor 102, the electronic device 100 enters the update state. Here, the controller 103 in the updated state controls the second multiplexing circuit 106 to electrically connect the controller 103 to the rom 104, and updates the rom 104 with the updated data D1.

In one embodiment of step S22, the processor 102 may obtain the update data D1 upon receiving an update command. The update command may be generated by a user issuing a manual update through the input device. In some embodiments, the update data D1 may be stored in a storage device, and the processor 102 may access the storage device according to the update command to obtain the update data D1. In some embodiments, the storage device may be a hard disk or a flash drive. In addition, the bus B1 may be an integrated circuit bus, but the invention is not limited thereto.

In one embodiment of step S23, the controller 103 may generate the selection signal SEL2 with the first selection value and the selection signal SEL3 with the first selection value to the second multiplexing circuit 106. The first multiplexer 106A of the second multiplexer 106 electrically connects the extended display capability identification rom 104 to the second multiplexer 106B of the second multiplexer 106 according to the selection signal SEL2 having the first selection value, and the second multiplexer 106B electrically connects the controller 103 to the first multiplexer 106A according to the selection signal SEL3 having the first selection value, so that the controller 103 can be electrically connected to the extended display capability identification rom 104 through the second multiplexer 106B and the first multiplexer 106A in sequence.

In some embodiments, as shown in fig. 1, the connector 101 may further include a detection pin P2. The controller 103 is coupled to the detection pin P2 of the connector 101. Here, the controller 103 may monitor the detection pin P2 and determine whether the external device 300 is connected to the connector 101 through the transmission line 200 according to whether the hot plug signal HPD is present on the detection pin P2. In some embodiments, the detection pin P2 may be the 19 th pin for hot plug detection in a standard high resolution multimedia interface port.

Fig. 5 is a flow chart of another updating method according to an embodiment of the present invention. Referring to fig. 1 to 5 and fig. 7, in some embodiments, in step S04, before step S22, the electronic device 100 may utilize the controller 103 to monitor the detection pin P2 to determine whether the external device 300 is connected to the connector 101. In step S05, when the controller 103 detects that the hot plug signal HPD is present on the detection pin P2, it indicates that the external device 300 is connected to the connector 101 through the transmission line 200, and the controller 103 can issue a confirmation command C1 through the first interface mcu_i1 and transmit the confirmation command C1 through the first multiplexing circuit 105 and the signal pin P1 to request the external device 300 to restore the device signal DEV. In this way, the controller 103 can determine whether the external device 300 is a standard device or a special device according to whether the device signal DEV is received.

In some embodiments, the specific device is an electronic device with a controller, and the controller of the specific device generates a device signal DEV with corresponding content according to the connection standard adopted when the controller of the specific device transmits the device signal DEV, and returns the device signal DEV to the electronic device 100. The standard device is an electronic device without a controller, and does not generate a device signal DEV corresponding to the confirmation command C1. In some embodiments, the acknowledge instruction C1 may be an instruction addressed using an integrated circuit bus connection standard. In addition, the special device may use an integrated circuit bus connection standard, a universal asynchronous receiver transmitter connection standard or a universal serial bus 2.0 connection standard for transmission, but the invention is not limited thereto.

In some embodiments, after performing step S05, if the controller 103 can indicate that the external device 300 connected to the connector 101 is a special device when the first interface mcu_i1 receives the device signal DEV from the external device 300 via the first multiplexing circuit 105 and the signal pin P1. In contrast, after step S05 is performed, if the controller 103 does not receive the device signal DEV from the external device 300 at the first interface mcu_i1, it indicates that the external device 300 connected to the connector 101 is a standard device. In some embodiments, the controller 103 may wait a predetermined time after executing the step S05, and determine that the external device 300 is a standard device when the device signal DEV is not received before the predetermined time is over. In other embodiments, the controller 103 may repeatedly execute the step S05 and wait for a predetermined time, and determine that the external device 300 is a standard device after exceeding a predetermined number of times. In some embodiments, the predetermined number of times may be between 3 and 10 times, but the invention is not limited thereto, and the predetermined number of times may be any suitable number.

In some embodiments, as shown in fig. 5, the aforementioned step S04, step S05 may be performed before step S22. In the present embodiment, in step S06, when the controller 103 determines that the external device 300 is a special device after executing step S05, the controller 103 can learn what the connection standard adopted by the external device 300 is according to the content of the device signal DEV, and then selectively control the first multiplexing circuit 105 to electrically connect the signal pin P1 of the connector 101 to the first interface mcu_i1 of the controller 103, the second interface mcu_i2 of the controller 103 or the first interface cpu_i1 of the processor 102 according to the connection standard, and control the second multiplexing circuit 106 to electrically connect the processor 102 to the extended display capability recognition rom 104. In step S07, when the controller 103 determines that the external device 300 is a standard device after executing step S05, the controller 103 can control the first multiplexing circuit 105 to electrically connect the signal pin P1 of the connector 101 to the second multiplexing circuit 106, and control the second multiplexing circuit 106 to electrically connect the processor 102 to the first multiplexing circuit 105, so that the signal pin P1 of the connector 101 can be electrically connected to the processor 102 through the first multiplexing circuit 105 and the second multiplexing circuit 106 in sequence.

Fig. 6 is a flowchart of step S06 of the update method according to the embodiment of the present invention. Referring to fig. 1 to 6, in one embodiment of step S06, step S061 and the controller 103 may identify the device signal DEV. In step S062, when the controller 103 recognizes the device signal DEV as the first content, the controller 103 can maintain generating the selection signal SEL1 with the first set value to the first multiplexing circuit 105 to control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the first interface mcu_i1 of the controller 103, and generate the selection signal SEL2 with the first selection value to the first multiplexer 106A and the selection signal SEL3 with the second selection value to the second multiplexer 106B to control the second multiplexing circuit 106 to electrically connect the extended display capability recognition rom 104 to the processor 102. In step S063, when the controller 103 recognizes the device signal DEV as the second content, the controller 103 can generate the selection signal SEL1 with the second setting value to the first multiplexing circuit 105 to control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the first interface cpu_i1 of the processor 102, and generate the selection signal SEL2 with the first selection value to the first multiplexer 106A and generate the selection signal SEL3 with the second selection value to the second multiplexer 106B to control the second multiplexing circuit 106 to electrically connect the extended display capability recognition rom 104 to the processor 102. In step S064, when the controller 103 recognizes the device signal DEV as the third content, the controller 103 can generate the selection signal SEL1 with the third setting value to the first multiplexing circuit 105 to control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the second interface mcu_i2 of the controller 103, and generate the selection signal SEL2 with the first selection value to the first multiplexer 106A and generate the selection signal SEL3 with the second selection value to the second multiplexer 106B to control the second multiplexing circuit 106 to electrically connect the extended display capability recognition rom 104 to the processor 102.

In one embodiment of step S07, the controller 103 may generate the selection signal SEL1 with the fourth setting value to the first multiplexing circuit 105 to control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the second multiplexing circuit 106, and the controller 103 may generate the selection signal SEL2 with the second selection value and the selection signal SEL3 with the second selection value to the second multiplexing circuit 106 to control the second multiplexing circuit 106 to electrically connect the first multiplexing circuit 105 to the processor 102.

In some embodiments, the first content of the device signal DEV may be an integrated circuit bus connection standard, the second content of the device signal DEV may be a universal serial bus 2.0 connection standard, and the third content of the device signal DEV may be a universal asynchronous receiver/transmitter connection standard, but the invention is not limited thereto. In addition, the processor 102 may also have a transmission interface CPU_I3 that employs the UART connection standard. Therefore, in step S064, the controller 103 may also control the first multiplexing circuit 105 to electrically connect the signal pin P1 of the connector 101 to the transmission interface cpu_i3 of the processor 102 using the universal asynchronous receiver transmitter connection standard.

In some embodiments, the second interface mcu_i2 of the controller 103 and the transmission interface cpu_i3 of the processor 102 may exist simultaneously. While in other embodiments, only either of the second interface mcu_i2 of the controller 103 and the transmission interface cpu_i3 of the processor 102 may exist.

Fig. 7 is a flowchart of another updating method according to an embodiment of the present invention. Referring to fig. 1 to 7, in some embodiments, the electronic device 100 may sequentially execute the foregoing step S04 and step S05. Here, in step S08, when the controller 103 determines that the external device 300 is a special device after executing in step S05, the controller 103 may first control the second multiplexing circuit 106 to electrically connect the controller 103 to the extended display capability recognition rom 104, step S09, so that the controller 103 may read the extended display capability recognition data in the extended display capability recognition rom 104 through the second multiplexing circuit 106. In one embodiment of step S08, the controller 103 can generate the selection signal SEL2 with the first selection value and the selection signal SEL3 with the first selection value to the second multiplexer 106B and the first multiplexer 106A of the second multiplexer 106, respectively, so that the controller 103 can be electrically connected to the extended display capability recognition read only memory 104 through the second multiplexer 106B and the first multiplexer 106A in sequence.

Step S10, following step S09, the controller 103 may determine whether the extended display capability identification data meets the specification of the external device 300 according to the extended display capability identification data and the device signal DEV. In one embodiment of step S10, the controller 103 may determine whether the extended display capability identification data is suitable for the external device 300 according to whether the Identity (ID) information contained in the extended display capability identification data matches the identity information contained in the device signal DEV, but the invention is not limited thereto. In another embodiment of step S10, the controller 103 may further determine whether the extended display capability identification data is suitable for the external device 300 according to the version information in the extended display capability identification data and the device signal DEV.

When the controller 103 determines in step S10 that the extended display capability identification data does not conform to the specification of the external device 300, it indicates that the extended display capability identification data is not applicable to the external device 300 and should be updated. At this time, the controller 103 performs step S31 to update the extended display capability recognition rom 104 with the update data D1. Accordingly, in some embodiments, the electronic device 100 may enter the updated state when the controller 103 determines that the extended display capability identification data does not conform to the specification of the external device 300. Here, the controller 103 in the updated state may update the extended display capability recognition rom 104 with the update data D1 directly via the second multiplexing circuit 106.

Fig. 8 is a schematic diagram of an execution flow of the update method according to the embodiment of the present invention after determining that the specification is not met in step S10. Referring to fig. 1 to 8, in some embodiments, after determining that the extended display capability identification data does not meet the specification of the external device 300, the controller 103 may request the processor 102 to transmit the corresponding update data D1 to the controller 103 according to the device signal DEV in step S11. Then, the controller 103 acquires the update data D1 from the processor 102 and then sequentially executes step S31. However, the invention is not limited thereto. In other embodiments, after determining that the extended display capability identification data does not meet the specification of the external device 300 in step S12, the controller 103 may also obtain the corresponding update data D1 from the internal storage unit according to the device signal DEV, and execute step S31 sequentially with the update data D1 obtained from the internal storage unit. In one embodiment of step S12, the controller 103 may obtain the updated data D1 with the corresponding identity information from the internal storage unit according to the identity information in the device signal DEV. In some embodiments, the internal storage unit may be, but is not limited to, a cache (cache) of the controller 103.

In some embodiments, as shown in fig. 7, when the controller 103 determines in step S10 that the extended display capability identification data meets the specification of the external device 300, it indicates that no update is necessary. At this time, the controller 103 may execute step S06 to control the first multiplexing circuit 105 and the second multiplexing circuit 106 to switch out the corresponding connection paths according to the content of the device signal DEV.

In some embodiments, when the controller 103 determines that the external device 300 is a standard device after executing the step S05, the controller 103 may execute the step S07 and the subsequent steps (as shown in fig. 5 and 4).

Fig. 9 is a flowchart of the update method provided in the embodiment of the present invention after step S22, and fig. 10 is a flowchart of the update method provided in the embodiment of the present invention after determining that the specification is not met in step S10. Referring to fig. 1 to 10, in some embodiments, step S24, before the execution of step S31, the controller 103 may generate the selection signal SEL1 with the fourth setting value to the first multiplexing circuit 105, so that the first multiplexing circuit 105 electrically connects the at least one signal pin P1 of the connector 101 to the second multiplexing circuit 106. In some embodiments, step S23 and step S24 in fig. 9 may be performed sequentially, in reverse order, or synchronously. Further, step S14 in fig. 10 may be performed before step S12 or step S13 is performed, or may be performed in synchronization with step S12 or step S13.

Fig. 11 is a schematic diagram of an execution flow of the update method provided in the embodiment of the present invention after step S31. Referring to figures 1 to 11 of the drawings,

in some embodiments, in step S32, after the controller 103 completes updating the rom 104 with the update data D1, the controller 103 sequentially executes a pull-out control procedure and a plug-in control procedure. In some embodiments, the controller 103 performs step S32 after step S31 only after the external device 300 has determined to be a specific device.

In some embodiments of step S32, the controller 103 can control the first multiplexing circuit 105 to electrically connect the signal pin P1 to the first interface mcu_i1 of the controller 103 and control the second multiplexing circuit 106 to electrically connect the processor 102 to the extended display capability recognition rom 104 in the pull-out control procedure, so as to restore to the initial state of the electronic device 100.

In some embodiments, as shown in fig. 2, the electronic device 100 further includes a power supply circuit 108, the connector 101 further includes a power pin P3, and the power supply circuit 108 is coupled to the power pin P3 and the controller 103. The power supply circuit 108 can be used for providing the first voltage V1 or the second voltage V2 to the power pin P3 according to the control of the controller 103.

In some embodiments, when the controller 103 outputs the first enable signal EN1 to the power supply circuit 108, the power supply circuit 108 can output the first voltage V1 to the power pin P3. When the controller 103 outputs the second enable signal EN2 to the power supply circuit 108, the power supply circuit 108 outputs the second voltage V2 to the power pin P3. Wherein the second voltage V2 is higher than the first voltage V1.

In some embodiments, the power pin P3 of the connector 101 may be the 18 th pin of the standard high-resolution multimedia interface port for providing power. The first voltage V1 may be, but is not limited to, 5 volts (V), and the second voltage V2 may be, but is not limited to, 12 volts, 14 volts, 18 volts, 24 volts, or 48 volts, and the values of the first voltage V1 and the second voltage V2 may be set according to the requirements of the external device 300.

In some embodiments, under the initial state of the electronic device 100, the controller 103 may normally output the first enable signal EN1 to the power supply circuit 108, so that the power supply circuit 108 normally provides the first voltage V1 to the power pin P3 according to the first enable signal EN 1.

Fig. 12 is a schematic diagram of a power supply circuit according to an embodiment of the present invention. Referring to fig. 1-12, in some embodiments, the power supply circuit 108 may include a power conversion circuit 108A and a power load switch 108B. The power conversion circuit 108A is coupled to the controller 103 and the power pin P3, and the power load switch 108B is coupled to the controller 103 and the power pin P3. The power conversion circuit 108A converts the first voltage V1 according to the second voltage V2, and outputs the converted first voltage V1 to the power pin P3 when receiving the first enable signal EN1 generated by the controller 103. The power load switch 108B is configured to receive the second voltage V2, and output the second voltage V2 to the power pin P3 when receiving the second enable signal EN2 generated by the controller 103.

In some embodiments, the power conversion circuit 108A may be implemented with, but is not limited to, a linear regulator (Low Dropout Linear Regulator, LDO). In addition, power load switch 108B may be implemented using, but is not limited to, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a bipolar junction transistor (Bipolar Junction Transistor, BJT), a gallium nitride field effect transistor (GaN FET), or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT).

Fig. 13 is a schematic diagram of another power supply circuit according to an embodiment of the invention. Referring to fig. 1-13, in other embodiments, the power supply circuit 108 may include a power conversion circuit 108C and a power load switch 108B. The power conversion circuit 108C is coupled to the controller 103 and the power pin P3, and the power load switch 108B is coupled to the controller 103 and the power pin P3. The power conversion circuit 108C converts the second voltage V2 according to the first voltage V1, and outputs the converted second voltage V2 to the power pin P3 when receiving the second enable signal EN2 generated by the controller 103. The power load switch 108B is configured to receive the first voltage V1, and output the first voltage V1 to the power pin P3 when receiving the first enable signal EN1 generated by the controller 103. In some embodiments, the power conversion circuit 108C may be implemented with, but is not limited to, a Buck Converter (Buck Converter).

In some embodiments, the electronic device 100 further includes a discharging circuit 109, and the discharging circuit 109 is coupled to the power pin P3. The discharging circuit 109 may be configured to discharge the power pin P3 or stop discharging the power pin P3 according to the discharging signal DG1 of the controller 103. In some embodiments, when the discharge signal DG1 is at a high level, the discharge circuit 109 can discharge the power pin P3. While the discharging circuit 109 does not discharge the power pin P3 or stops discharging the power pin P3 when the discharging signal DG1 is at a low level, the invention is not limited thereto, and the discharging circuit 109 may also discharge the power pin P3 when the discharging signal DG1 is at a low level, and does not discharge the power pin P3 or stop discharging the power pin P3 when the discharging signal DG1 is at a high level.

In some embodiments of step S32, in the pull-out control procedure, the controller 103 may not output the first enable signal EN1 and the second enable signal EN2 to cause the power supply circuit 108 to stop supplying power to the power pin P3, and the controller 103 may output the discharge signal DG1 to cause the discharge circuit 109 to discharge the power pin P3. After the discharging is performed for a preset period of time, the controller 103 stops outputting the discharging signal DG1 to cause the discharging circuit 109 to stop discharging the power pin P3, and outputs the first enable signal EN1 to control the power supply circuit 108 to resume providing the first voltage V1 to the power pin P3. In some embodiments, the predetermined time may be several hundred milliseconds, but the present invention is not limited thereto.

In some embodiments of step S32, in the insertion control procedure, the controller 103 may monitor the detection pin P2, and issue an acknowledge command C1 to request the recovery device signal DEV via the first multiplexing circuit 105 and the signal pin P1 when the hot insertion signal HPD is detected on the detection pin P2. When the device signal DEV is received, the controller 103 selectively controls the first multiplexing circuit 105 to electrically connect the signal pin P1 of the connector 101 to the first interface mcu_i1 of the controller 103, the second interface mcu_i2 of the controller 103 or the first interface cpu_i1 of the processor 102 according to the content of the device signal DEV, and controls the second multiplexing circuit 106 to electrically connect the processor 102 to the extended display capability recognition rom 104. When the device signal DEV is not received, the controller 103 may control the first multiplexing circuit 105 to electrically connect the signal pin P1 of the connector 101 to the second multiplexing circuit 106, and control the second multiplexing circuit 106 to electrically connect the processor 102 to the first multiplexing circuit 105, so that the signal pin P1 of the connector 101 may be electrically connected to the processor 102 through the first multiplexing circuit 105 and the second multiplexing circuit 106 in sequence.

In some embodiments, when the external device 300 is a special device, the controller 103 can switch the first multiplexing circuit 105 and the second multiplexing circuit 106 to the correct link paths by sequentially executing the pull-out control program and the insert control program after completing the update of the extended display capability identification rom 104 (since the controller 103 can perform corresponding control according to the device signal DEV in the insert control program). Moreover, the controller 103 may cause the processor 102 to output the image data D2 to the image pin P5 through the selection signal SEL3 having the second selection value, so that the electronic device 100 enters the display state. In the case that the external device 300 is a standard device, the controller 103 may switch the selection signal SEL3 from the first selection value to the second selection value and switch the selection signal SEL2 from the first selection value to the second selection value after completing the update of the extended display capability identifying rom 104, such that the second multiplexing circuit 106 electrically connects the processor 102 to the first multiplexing circuit 105 (in this case, the first multiplexing circuit 105 electrically connects the signal pin P1 to the second multiplexing circuit 106), and the processor 102 outputs the image data D2 to the image pin P5, such that the electronic device 100 enters the display state.

In some embodiments, as shown in fig. 2, the electronic device 100 further includes a third multiplexing circuit 110, the connector 101 further includes a control pin P4, and the third multiplexing circuit 110 is coupled to the control pin P4, the processor 102 and the controller 103. The third multiplexing circuit 110 is configured to selectively electrically connect the control pin P4 of the connector 101 to the processor 102 or the controller 103 according to the selection signal SEL 2. Here, when the select signal SEL2 has the first selection value, the third multiplexing circuit 110 electrically connects the control pin P4 to the controller 103. When the select signal SEL2 has the second selection value, the third multiplexing circuit 110 electrically connects the control pin P4 to the processor 102.

In some embodiments, when the external device 300 is a special device, the external device 300 can output an activation signal to the control pin P4 of the connector 101. In some embodiments, the activation signal may be generated using a power button. However, the present invention is not limited thereto, and in other embodiments, the activation signal may be generated when the external device 300 is activated. In other embodiments, when the external device 300 is a standard device, standard consumer electronic control signals can be transmitted between the electronic device 100 and the external device 300 at the control pin P4 of the connector 101.

In some embodiments, control pin P4 of connector 101 may be pin 13 of a standard high resolution multimedia interface port for consumer electronics control (Consumer Electronics Control, CEC).

In summary, in the electronic device 100 with the connector 101 supporting multiple connection standards and the updating method thereof according to the embodiments of the invention, the link path between the controller 103 and the EDROM 104 can be established by switching the second multiplexing circuit 106 in the updated state, so that the controller 103 can update the EDROM 104 built in the electronic device 100 with the connector 101 supporting multiple connection standards by the updated data D1. In addition, in the electronic device 100 with the connector 101 supporting multiple connection standards and the updating method thereof according to the embodiments of the present invention, the processor 102 may be manually caused to send the update data D1 to the controller 103 so as to enter the update state, and the controller 103 may also automatically determine whether to enter the update state according to the extended display capability identification data after receiving the device signal DEV. In particular, after the controller 103 enters the update state according to the determination result, the controller 103 can further obtain the corresponding update data D1 according to the device signal DEV and automatically update the update data D1. In addition, the electronic device 100 with the connector 101 supporting multiple connection standards and the updating method thereof according to the present invention switch the transmission path of at least one signal pin P1 of the connector according to whether the device signal DEV is received, so that a single connector 101 can support multiple connection standards, and the electronic device 100 can transmit with a standard device or a special device through the single connector 101 and can select one application from multiple connection standards.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. An electronic device having a connector supporting multiple connection standards, comprising:

the connector comprises at least one signal pin;

a processor;

a controller coupled to the processor;

an extended display capability identification read-only memory for storing the extended display capability identification data;

the first multiplexing circuit is coupled with the at least one signal pin, the processor and the controller; and

a second multiplexing circuit coupled to the extended display capability recognition ROM, the first multiplexing circuit, the processor, and the controller;

In the update state, the controller is electrically connected to the extended display capability identification read-only memory through the second multiplexing circuit, and updates the extended display capability identification data in the extended display capability identification read-only memory with update data.

2. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic devices,

the controller also receives device signals transmitted by an external device through the first multiplexing circuit and the at least one signal pin;

when the controller receives the device signal, the controller controls the second multiplexing circuit to electrically connect the controller to the extended display capability identification read-only memory, so that the controller reads the extended display capability identification data of the extended display capability identification read-only memory through the second multiplexing circuit, and judges whether the extended display capability identification data accords with the specification of the external device according to the extended display capability identification data and the device signal; and

when it is judged that the extended display capability identification data does not conform to the specification of the external device, the controller updates the extended display capability identification read only memory with the update data via the second multiplexing circuit.

3. The electronic device of claim 2, wherein the controller requests the processor to transmit the update data to the controller according to the device signal, or the controller obtains the update data from an internal storage unit of the controller according to the device signal.

4. The electronic device of claim 2, wherein the connector further comprises a detection pin, the controller monitors the detection pin, and when the detection pin is detected to generate a hot plug signal, a confirmation command is sent via the first multiplexing circuit and the at least one signal pin to request the external device to reply to the device signal.

5. The electronic device of claim 4, wherein when the controller issues the confirmation instruction without receiving the device signal, the controller controls the second multiplexing circuit to electrically connect the controller to the extended display capability recognition read-only memory when the controller receives the update data from the processor, such that the controller updates the extended display capability recognition read-only memory with the update data via the second multiplexing circuit.

6. The electronic device of claim 1, wherein the controller, upon receiving the update data from the processor, controls the second multiplexing circuit to electrically connect the controller to the extended display capability recognition read only memory such that the controller updates the extended display capability recognition read only memory with the update data via the second multiplexing circuit.

7. The electronic device of claim 1, wherein the controller further controls the first multiplexing circuit to electrically connect the at least one signal pin to the second multiplexing circuit.

8. The electronic device of claim 1, wherein the second multiplexing circuit comprises:

a first multiplexer coupled to the first multiplexing circuit and the extended display capability recognition ROM; and

a second multiplexer coupled to the first multiplexer, the processor and the controller;

wherein in a display state, the second multiplexer electrically connects the processor to the first multiplexer, and the first multiplexer electrically connects the second multiplexer to the first multiplexer circuit or the extended display capability identification read-only memory, such that the processor is electrically connected to the first multiplexer circuit or the extended display capability identification read-only memory via the second multiplexer and the first multiplexer; and

In the updated state, the second multiplexer electrically connects the controller to the first multiplexer, and the first multiplexer electrically connects the second multiplexer to the extended display capability identification read-only memory, such that the controller is electrically connected to the extended display capability identification read-only memory via the second multiplexer and the first multiplexer.

9. The electronic device of claim 8, further comprising:

a voltage level shifter, the second multiplexer being coupled to the processor via the voltage level shifter.

10. The electronic device of claim 1, further comprising:

the second multiplexing circuit is coupled to the processor via the voltage level shifter.

11. The electronic device of claim 1, wherein in a display state, the controller controls the first multiplexing circuit to electrically connect the at least one signal pin to the controller, the processor, or the second multiplexing circuit, and controls the second multiplexing circuit to electrically connect the processor to the extended display capability recognition read only memory or the first multiplexing circuit.

12. The electronic device of claim 2, wherein the controller sequentially executes the pull-out control program and the insert control program after the controller completes the rom update with the update data.

13. The electronic device of claim 12, wherein in the pull-out control procedure, the controller controls the first multiplexing circuit to electrically connect the at least one signal pin to the controller, and controls the second multiplexing circuit to electrically connect the processor to the extended display capability recognition read only memory.

14. The electronic device of claim 12, wherein the connector further comprises a power pin, the electronic device further comprising:

the power supply circuit is coupled with the power pin and provides a first voltage to the power pin; and

the discharging circuit is coupled with the power supply pin;

when the device signal is received, the controller controls the power supply circuit to provide a second voltage higher than the first voltage to the power pin; and

and when the controller is in the pull-out control program, the controller controls the power supply circuit to stop supplying power and controls the discharging circuit to discharge the power supply pin, and after the discharging is performed for a preset period of time, the controller controls the discharging circuit to stop discharging and controls the power supply circuit to provide the first voltage to the power supply pin.

15. The electronic device of claim 12, wherein the connector further comprises a detection pin, and wherein the controller monitors the detection pin and issues a confirmation command via the first multiplexing circuit and the at least one signal pin to request the device signal to be recovered when the hot plug signal is detected on the detection pin in the plug control procedure, and wherein the controller controls the first multiplexing circuit to electrically connect the at least one signal pin to the controller or the processor and controls the second multiplexing circuit to electrically connect the processor to the extended display capability recognition read only memory when the device signal is received.

16. A method for updating an electronic device having a connector supporting multiple connection standards, comprising:

in the update state, the extended display capability identification read-only memory is updated with update data via the second multiplexing circuit by the controller.

17. The method as recited in claim 16, further comprising:

when a device signal transmitted by an external device is received through at least one signal pin of the first multiplexing circuit and the connector, the controller is electrically connected to the extended display capability identification read-only memory by utilizing the second multiplexing circuit;

Reading, with the controller, extended display capability identification data of the extended display capability identification read only memory via the second multiplexing circuit;

judging whether the extended display capability identification data accords with the specification of the external device or not according to the extended display capability identification data and the device signal by utilizing the controller; and

when it is judged that the extended display capability identification data does not conform to the specification of the external device, an operation of updating the extended display capability identification read only memory with the update data via the second multiplexing circuit by the controller is performed.

18. The method as recited in claim 17, further comprising:

and requesting a processor to transmit the update data to the controller by the controller according to the device signal.

19. The method as recited in claim 17, further comprising:

in the update state, the controller is utilized to acquire the update data from an internal storage unit of the controller according to the device signal.

20. The method as recited in claim 17, further comprising:

monitoring a detection pin position of the connector by using the controller; and

When the detection pin is detected to generate a hot plug signal, the controller is utilized to send a confirmation instruction through the first multiplexing circuit and the at least one signal pin so as to request the external device to recover the device signal.

21. The method as recited in claim 20, further comprising:

when the controller receives the update data from the processor, the controller is used for controlling the second multiplexing circuit to electrically connect the controller to the extended display capability identification read-only memory and executing the operation of updating the extended display capability identification read-only memory by the update data through the second multiplexing circuit by the controller.

22. The method as recited in claim 16, further comprising:

transmitting the update data to the controller with a processor; and

when the controller receives the update data, the controller is used for controlling the second multiplexing circuit to electrically connect the controller to the extended display capability identification read-only memory, and the operation of updating the extended display capability identification read-only memory by the update data through the second multiplexing circuit by using the controller is executed.

23. The method as recited in claim 16, further comprising:

at least one signal pin of the connector is electrically connected to the second multiplexing circuit by the first multiplexing circuit.

24. The method of claim 16, wherein in the display state a first multiplexer of the second multiplexing circuit electrically connects the extended display capability identification read-only memory to a second multiplexer of the second multiplexing circuit and the second multiplexer electrically connects the first multiplexer to a processor, and in the update state the first multiplexer electrically connects the extended display capability identification read-only memory to the second multiplexer and the second multiplexer electrically connects the first multiplexer to the controller.

25. The method of claim 24, wherein the second multiplexer is coupled to the processor via a voltage level shifter.

26. The method as recited in claim 16, further comprising:

in a display state, electrically connecting at least one signal pin of a connector to the controller, the processor or the second multiplexing circuit by using a first multiplexing circuit; and

And in the display state, the processor is electrically connected to the extended display capability identification read-only memory or the first multiplexing circuit by using the second multiplexing circuit.

27. The method as recited in claim 17, further comprising:

after the update of the extended display capability identification read-only memory by the update data is completed, the controller is utilized to sequentially execute a pull-out control program and a plug-in control program.

28. The method of claim 27, wherein the extraction control program comprises:

electrically connecting the at least one signal pin to the controller using the first multiplexing circuit; and

and electrically connecting the processor to the extended display capability identification read-only memory by using the second multiplexing circuit.

29. The method as recited in claim 27, further comprising:

providing a first voltage to a power pin of the connector by using a power supply circuit; and

when the device signal is received, the power supply circuit is utilized to provide a second voltage higher than the first voltage to the power pin;

wherein the pull-out control program includes:

Controlling the power supply circuit to stop supplying power;

the discharging circuit is controlled to discharge the power supply pin; and

after the discharging is performed for a preset period of time, the discharging circuit is controlled to stop discharging, and the power supply circuit is controlled to provide the first voltage to the power pin.

30. The method of claim 27, wherein the insertion control procedure comprises:

monitoring a detection pin position of the connector by using the controller;

when the hot plug signal is detected to appear on the detection pin, the controller is utilized to send a confirmation instruction through the first multiplexing circuit and the at least one signal pin so as to request to restore the device signal; and

when the device signal is received, the controller is used for controlling the first multiplexing circuit to electrically connect the at least one signal pin to the controller or the processor, and controlling the second multiplexing circuit to electrically connect the processor to the extended display capability identification read-only memory.