CN116184776A - Wafer exposure method and system - Google Patents
Wafer exposure method and system Download PDFInfo
- Publication number
- CN116184776A CN116184776A CN202310185221.XA CN202310185221A CN116184776A CN 116184776 A CN116184776 A CN 116184776A CN 202310185221 A CN202310185221 A CN 202310185221A CN 116184776 A CN116184776 A CN 116184776A
- Authority
- CN
- China
- Prior art keywords
- exposure
- wafer
- complete
- units
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70508—Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
Abstract
The application discloses a wafer exposure method and a wafer exposure system. The wafer exposure method comprises the following steps: dividing a plurality of exposure units on the surface of the wafer, wherein the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer; acquiring a focal length energy matrix table of a photoetching layer to be exposed; obtaining the pattern morphology and line width of each complete exposure unit after exposure under the initial exposure condition; correcting the exposure condition of each complete exposure unit according to the focal length energy matrix table to ensure that the pattern morphology and the line width of each complete exposure unit accord with the specification; and correcting the exposure condition of the incomplete exposure unit according to the exposure condition after the complete exposure unit adjacent to the incomplete exposure unit is corrected. The method and the device can greatly improve the pattern morphology and the line width uniformity in the wafer surface by correcting the exposure conditions of the complete exposure unit according to the pattern morphology and the line width of the complete exposure unit and correcting the exposure conditions of the incomplete exposure unit according to the exposure conditions of the complete exposure units adjacent to the incomplete exposure unit.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a wafer exposure method and system.
Background
The photolithography process is a critical process in the semiconductor manufacturing process, and the smaller the critical dimension of the photolithographic pattern, the smaller the chip size that is manufactured. However, as the critical dimension of the pattern decreases, the process window of the photolithography process will decrease greatly, thereby deteriorating the uniformity of the photolithography pattern in the wafer surface, reducing the process fault tolerance, and failing to meet the production requirements.
With the development of semiconductor manufacturing processes, the production of first-generation semiconductors (silicon-based semiconductors) and second-generation semiconductors (compound semiconductors such as gallium arsenide, indium phosphide, etc.) is gradually tending to use larger-sized wafers to reduce product cost. While larger wafer sizes will cause problems such as wafer warpage and poor flatness, which will also reduce the process window of the lithographic process, thereby deteriorating the uniformity of the lithographic pattern in the wafer plane. In addition, in the photolithography process of the third generation semiconductor (such as silicon carbide, gallium nitride and other wide bandgap semiconductors), the process window of the photolithography process is reduced due to the problems of light transmittance, refractive index and the like, so that the uniformity of the photolithography pattern in the wafer surface is deteriorated, and the production requirement cannot be met. The uniformity deterioration of the photoetching pattern can cause the critical dimension, morphology and other parameters of the pattern to generate serious differences in the wafer surface, so that the problems of large product performance difference, low yield and the like are caused.
Therefore, there is a need for a new wafer exposure method and system that addresses the above-described issues.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a wafer exposure method and system for solving the problem of poor uniformity of a lithographic pattern in a wafer surface in the prior art.
To achieve the above and other related objects, the present application provides a wafer exposure method, comprising the steps of:
dividing a plurality of exposure units on the surface of a wafer, wherein the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer;
acquiring a focal length energy matrix table of a photoetching layer to be exposed;
obtaining the pattern morphology and line width of each complete exposure unit after exposure under the initial exposure condition;
correcting the exposure condition of each complete exposure unit according to the focal length energy matrix table to enable the pattern morphology and line width of the complete exposure unit to accord with the specification;
and correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit.
As an alternative of the present application, after obtaining the corrected exposure conditions of the plurality of exposure units, partitioning the plurality of exposure units, and correcting the exposure conditions of the exposure units in the same partition so that the exposure units in the same partition have the same exposure conditions.
As an alternative of the present application, the pattern morphology and line width of the complete exposure unit are obtained by measuring the process control monitoring unit in the complete exposure unit.
As an alternative of the present application, the method of correcting the exposure condition of the incomplete exposure unit includes: and carrying out weighted average calculation on a plurality of exposure conditions of the complete exposure units adjacent to the incomplete exposure unit.
As an alternative of the present application, the method of correcting the exposure condition of the incomplete exposure unit includes: and calculating linear variation trend of a plurality of exposure conditions of a plurality of complete exposure units from the incomplete exposure unit to the center of the wafer.
As an alternative scheme of the application, after obtaining the corrected exposure conditions of the plurality of exposure units, the method further comprises the steps of exposing each exposure unit by adopting the exposure conditions, and obtaining the pattern morphology and the line width of the complete exposure unit so as to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again.
As an alternative scheme of the application, in the photoetching exposure process of different batches of products, the pattern morphology and the line width of the complete exposure unit of the previous batch are obtained, the exposure conditions of the complete exposure unit and the incomplete exposure unit are corrected, and the exposure conditions are used in the photoetching exposure of the next batch of products.
As an alternative of the present application, a method for obtaining a focal length energy matrix table of a lithography layer to be exposed includes: and establishing a focal length energy matrix table library aiming at different products and different lithography levels, and calling the focal length energy matrix table according to the product and lithography level information.
The application also provides a wafer exposure system, comprising:
the data storage module is used for storing focal length energy matrix tables of different products and lithography levels;
the photoetching exposure module divides a plurality of exposure units on the surface of the wafer, the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer, and the photoetching exposure module performs exposure treatment on each exposure unit of the wafer according to input exposure conditions and outputs the pattern morphology and line width of the exposure units;
the data processing module is used for acquiring the focus energy matrix table stored in the data storage module according to the information of the product and the photoetching hierarchy, correcting the exposure condition of each complete exposure unit according to the focus energy matrix table, enabling the pattern morphology and the line width of the complete exposure unit to accord with the specification, correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit, and outputting the corrected exposure condition to the photoetching exposure module.
As an alternative, the data processing module divides the plurality of exposure units into areas after obtaining the corrected exposure conditions of the plurality of exposure units, corrects the exposure conditions of each exposure unit in the same area, and makes each exposure unit in the same area have the same exposure condition.
As an alternative scheme of the application, after obtaining corrected exposure conditions of a plurality of exposure units, the data processing module outputs the exposure conditions to the lithography exposure module to expose each exposure unit, and obtains pattern morphology and line width of the complete exposure unit from the lithography exposure module to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again.
As described above, the wafer exposure method and system provided by the application can be used for correcting the exposure conditions of the complete exposure unit according to the pattern morphology and the line width of the complete exposure unit, and correcting the exposure conditions of the incomplete exposure unit through the exposure conditions of the complete exposure unit adjacent to the incomplete exposure unit, so that the uniformity of the pattern morphology and the line width in the wafer surface can be greatly improved.
Drawings
Fig. 1 is a flowchart illustrating a wafer exposure method according to a first embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a specific process of the wafer exposure method according to the first embodiment of the present application.
FIG. 3 is a flow chart showing a partitioning exposure process of a compound algorithm provided in a first embodiment of the present application.
Fig. 4 is a flowchart of an exposure compensation algorithm provided in the first embodiment of the present application.
Fig. 5 shows a flowchart of an edge compensation algorithm provided in the first embodiment of the present application.
Fig. 6 shows a flowchart of a partitioning algorithm provided in a first embodiment of the present application.
Fig. 7 shows a line width distribution diagram of an exposure unit using an initial exposure condition provided in the first embodiment of the present application.
FIG. 8 shows a partitioning distribution diagram of an exposure unit after a partitioning algorithm as provided in embodiment one of the present application.
Fig. 9 shows a line width distribution diagram of an exposure unit using the corrected exposure condition provided in the first embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. As used in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of illustration, and the schematic diagram is merely an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
Please refer to fig. 1 to 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
Referring to fig. 1 to 9, the present embodiment provides a wafer exposure method, which includes the following steps:
1) Dividing a plurality of exposure units on the surface of a wafer to be processed, wherein the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer;
2) Acquiring a focal length energy matrix table of a photoetching layer to be exposed;
3) Obtaining the pattern morphology and line width of each complete exposure unit after exposure under the initial exposure condition;
4) Correcting the exposure condition of each complete exposure unit according to the focal length energy matrix table to enable the pattern morphology and line width of the complete exposure unit to accord with the specification;
5) And correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit.
In step 1), referring to step S1 of fig. 1 and fig. 7, a plurality of exposure units (shots) are divided on the surface of the wafer to be processed, wherein the exposure units include a complete exposure unit 101 located in an inner area of the wafer (i.e., a center of the wafer) and an incomplete exposure unit 102 located in an edge area of the wafer. In fig. 7, the area covered by the circle represents the area occupied by the wafer subjected to the photolithography process, and the plurality of rectangular areas of the same size represent the area subjected to exposure by the stepper at a time, i.e., the exposure unit. The light-colored rectangular area has an area overlapping with the wafer, which is an effective exposure unit that actually performs the exposure operation, and the shadow area is an ineffective exposure unit 103, and since it does not overlap with the wafer or overlaps with the wafer so little as to be negligible, the exposure operation is not actually performed. In the light-colored rectangular area, the light-colored rectangular area marked with a number is located entirely inside the wafer, which is defined as a complete exposure unit 101, and the marked number represents the feature size, also referred to as line width, measured by a process control monitor (PCM, process control monitor) unit of the exposure unit. The process control monitoring unit is a unit in a wafer for monitoring whether each process step in the semiconductor manufacturing process meets an expected area, and has a plurality of structures designed for process monitoring. For monitoring the photolithography process, the line width measurement is generally performed, that is, a pattern structure (generally, an L-bar pattern structure or a hole pattern structure) specially used for line width measurement is arranged on a photolithography mask plate, and the line width of the line width measurement structure is measured after photolithography exposure to represent the line width characteristics of the photolithography pattern of the exposure unit. The line width measuring structure of the process control and monitoring unit is generally arranged in the scribing groove of the edge area of the single exposure unit. When the exposure unit is located in the wafer edge area, it is defined as an incomplete exposure unit 102, which may be defective in the line width measurement structure, thereby making it impossible to measure the feature size through the process control monitor unit. In fig. 7, the light-colored rectangular area, which is not marked with a number, is the incomplete exposure unit 102, which cannot directly measure the feature size of the lithography pattern by the process control and monitoring unit.
In step 2), please refer to step S2 of fig. 1 and fig. 2, a focal length energy matrix table of the lithography layer to be exposed is obtained. A Focus Energy Matrix (FEM) is a test method for inspecting a photolithography process window and determining an optimal exposure condition by employing different exposure focal lengths (Focus) and exposure energies (Energy) on exposure units at different positions on a wafer, generating a conditional combination of the different exposure focal lengths and exposure energies, and obtaining pattern topography and line widths at the different exposure focal lengths and exposure energies, the combination of the above data constituting a Focus Energy Matrix table. The focus energy matrix table can determine the optimal exposure focus and exposure energy under specific specification requirements. In the test of the focus energy matrix, for the exposure unit in the wafer plane, as shown in the X-axis and Y-axis directions of fig. 7, the exposure focus is generally fixed in the X-axis direction to set different exposure energies, and the exposure energy is fixed in the Y-axis direction to set different exposure focuses. Thus, different exposure units in the wafer surface are exposed under different exposure focal lengths and exposure energy combinations, and the pattern feature sizes are measured to obtain a focal length energy matrix table. As an example, a focal length energy matrix table library is established for different products and different lithography levels, and the focal length energy matrix table is retrieved according to the product and lithography level information. For different lithography levels of different products, a corresponding focus energy matrix table is obtained and stored, a focus energy matrix table base is established, and the corresponding focus energy matrix table can be directly called according to the product and lithography level information in the subsequent lithography process, so that the better lithography exposure condition can be rapidly determined, and the test collection of the focus energy matrix is not required to be repeated.
Fig. 2 is an exemplary flowchart of a specific process of the wafer exposure method provided in the present embodiment. After the start of the nodes, the product information and the process layer information of the wafer to be exposed are sequentially acquired at the node 201 and the node 202, so that the stored lithography process information and the focus energy matrix table are searched according to the information, or the stored lithography process information and the focus energy matrix table are used as search labels when the focus energy matrix table is stored. At node 203, photolithography process information is obtained, which should include, but is not limited to, parameters such as the type of photoresist used in the layer photolithography process, the thickness of the photoresist, the design linewidth of the photomask, the target linewidth of the photolithographic pattern, the actual linewidth, etc. These parameters directly affect the pattern linewidth and morphology of the photoresist after the photolithography process is subjected to different exposure conditions, and thus directly affect the data of the focal length energy matrix table. After the lithography process information is obtained, it is determined whether the existing database has the same lithography process information, and if not, new Focus Energy Matrix (FEM) table data is created at node 204, where the FEM data obtaining method is as described above. If there is the same lithography process information in the existing database, then existing Focus Energy Matrix (FEM) table data is directly recalled at node 205 and the composite algorithm partition exposure is performed at node 206 in accordance with the Focus Energy Matrix (FEM) table data. The specific algorithmic processes of the composite algorithm zone exposure include an exposure compensation algorithm, an edge compensation algorithm, and a zone algorithm, which are performed in sequence, and the three algorithmic processes are described in detail below.
In step 3), referring to step S3 of fig. 1 and fig. 3 and 7, the pattern morphology and line width of each of the complete exposure units after exposure under the initial exposure conditions are obtained. The initial exposure condition can be obtained by retrieving a focal length energy matrix table. As shown in fig. 7, the data distribution diagram of the specific lithography level of the specific product after the feature size measurement of each exposure unit is performed after the lithography exposure. The numbers marked on the complete exposure unit 101 are the feature size values obtained by measurement. By way of example, the exposed wafer in fig. 7 uses a 4 inch silicon carbide substrate with an overlying epitaxial layer comprising GaN, alN, alGaN, gaN or SiN material. The size of a single exposure unit is 10.4mm long and 96mm wide, the photoresist used is SPR series, the thickness of the photoresist is 1 μm, the uniformity of the thickness of the photoresist is 0.1%, and the designed line width is 1.8 μm. As an example, the present embodiment uses a nikon nsi 11 lithography machine as an example, and in other embodiments of the present invention, other possible stepper lithography machines with partitioned exposure conditions, scanning lithography machines, immersion lithography machines, etc. may also be used.
As shown in FIG. 7, the minimum value of the line width dimension in the wafer surface is 0.35 μm, the uniformity is poor, the specification requirements are not met, and the product yield is seriously affected. As shown in fig. 3, a flow chart of the composite algorithm partition exposure method of fig. 2 is shown. After the start of the node, focal length energy matrix (FEM) information is retrieved at node 301 and initial exposure conditions are determined from FEM information at node 302. The wafer to be exposed is subjected to photolithography processes such as photoresist coating, exposure and development at node 303 according to the initial exposure conditions. The line width and topography of each exposure cell, and in particular, the Process Control Monitor (PCM) cell of each complete exposure cell, is measured at node 304 to determine the line width and topography. A determination is made at node 305 as to whether all exposure units meet the specification requirements. If the pattern line width and the pattern of each exposure unit (shot) meet the specification requirements, ending the partition exposure of the compound algorithm. If the exposure unit does not meet the specification requirements, such as the case of poor uniformity shown in fig. 7, the exposure compensation algorithm, the edge compensation algorithm, and the partitioning algorithm may be sequentially performed at node 306, and corrected exposure conditions may be obtained at node 307. After the new modified exposure conditions are obtained at node 307, the wafer is stripped and reworked, and the wafer is returned to node 303 for glue application, exposure and development again until all exposure units meet the specification requirements.
In step 4), referring to step S4 of fig. 1 and fig. 4 and 7, the exposure conditions of each complete exposure unit are modified according to the focal length energy matrix table, so that the pattern morphology and line width of the complete exposure unit meet the specification. In fig. 7, after exposure to the initial exposure conditions, all complete exposure units 101 measure line widths for Process Control Monitor (PCM) units. Compared with a specification value of 1.8 mu m, the value of the central area of the wafer is larger (> 1.9 mu m), the value of the edge area of the wafer is smaller (< 1.7 mu m), and the step corrects the exposure condition of each complete exposure unit by executing an exposure compensation algorithm so that the pattern morphology and the line width of the complete exposure unit meet the specification. The units of line width numbers in fig. 7 and 9 are both μm. Specifically, as shown in fig. 4, a flowchart of the exposure compensation algorithm in fig. 3 is shown. After the start of the node, the coordinates of the current exposure unit (shot) to be corrected are acquired at node 401, and the parameters (such as exposure conditions, line width, and topography) of the current exposure unit are acquired at node 402. Judging whether the pattern morphology of the current exposure unit meets the specification requirement at the node 403, if not, compensating the exposure focus (focus) according to a Focus Energy Matrix (FEM) table at the node 404 and the node 405 in sequence, and storing the compensated condition. Whether the pattern line width of the current exposure unit meets the specification requirement is judged at the node 406, if not, the exposure energy (focus) is compensated at the node 407 and the node 408 in sequence according to a Focus Energy Matrix (FEM) table, and the compensated condition is saved. If both node 403 and node 406 determine that the specification requirements are met, then the current exposure conditions are saved at node 409. For an I-line stepping projection type photoetching machine, when positive photoresist is adopted, the exposure is sufficient, and the focal length is a main reason for influencing the appearance of the graph; when the pattern morphology is normal, namely the side wall of the structure after photoresist development is vertical, the main factor influencing the linewidth of the photoresist pattern is exposure energy. Therefore, the exposure focal length is generally adjusted to adjust the pattern appearance, and the exposure energy is adjusted to adjust the pattern line width. The actual pattern linewidth and the specification linewidth can be compared with the corresponding linewidth in a Focus Energy Matrix (FEM) table to obtain a compensation value of the exposure focus or energy required to reach the specification linewidth. In other embodiments of the present invention, the exposure focal length and the exposure energy may be adjusted simultaneously to adjust the pattern morphology or line width. Judging whether the currently processed exposure unit is the last one at a node 410, and ending the exposure compensation algorithm process if the currently processed exposure unit is the last one; if not the last, the coordinates of the next exposure unit to be processed are acquired at node 411 and looped to exposure compensation for the next exposure unit at node 402.
In step 5), please refer to step S5 of fig. 1 and fig. 5 and 7, the exposure condition of the incomplete exposure unit is modified according to the modified exposure condition of the complete exposure unit adjacent to the incomplete exposure unit. As shown in fig. 7, the line width of the photolithographic pattern of the incomplete exposure unit 102 cannot be known by direct measurement due to the missing Process Control Monitor (PCM) unit. In the present embodiment, the exposure conditions of the incomplete exposure unit 102 are corrected according to the corrected exposure conditions of the adjacent complete exposure unit 101 by the edge compensation algorithm. Optionally, the method for correcting the exposure condition of the incomplete exposure unit includes: carrying out weighted average calculation on a plurality of exposure conditions of the complete exposure units adjacent to the incomplete exposure unit; or when the number of the complete exposure units on the periphery is not large, calculating the linear variation trend of the exposure conditions of the complete exposure units from the incomplete exposure units to the center of the wafer.
As shown in fig. 5, a flow chart of the edge compensation algorithm of fig. 3 is shown. After the start of the node, a list of coordinates of incomplete exposure units of the edge is obtained at node 501, and coordinates of the initial exposure units are picked from the list at node 502. Exposure condition information for a complete exposure unit surrounding the current incomplete exposure unit is obtained at node 503. For example, in fig. 7, the peripheral complete exposure units of the incomplete exposure unit 102 on the upper right side of the wafer are three complete exposure units arranged in the Y direction with a left line width of 1.6329 μm, 1.6842 μm, 1.6845 μm, and the like, respectively. In node 504, the exposure conditions of the current incomplete exposure unit are calculated from the acquired exposure conditions of the peripheral complete exposure unit. For example, the exposure conditions of the incomplete exposure unit may be obtained by a weighted average calculation, and weights of the weighted average calculation of the left complete exposure unit, the upper left complete exposure unit, and the lower left complete exposure unit may be set to 0.4:0.3:0.3, respectively, for the incomplete exposure unit 102 in fig. 7. In other embodiments of the present invention, the selection range of the peripheral complete exposure unit can be enlarged, and the weights calculated according to the weighted average different from the distance setting of the incomplete exposure unit can be set. In addition, in other embodiments of the present invention, the linear variation trend calculation of the multiple exposure conditions of the incomplete exposure unit to the multiple complete exposure units in the center of the wafer may also be obtained. For example, in fig. 7, the line widths of the complete exposure units from the left side to the center of the wafer of the incomplete exposure unit 102 are 1.6842 μm, 1.7385 μm, 1.7324 μm, 1.8361 μm, 1.9537 μm and 1.9871 μm in this order, the complete exposure unit can obtain the compensation value of the exposure condition thereof by the exposure compensation algorithm in fig. 4, and the compensation value of the exposure condition of the incomplete exposure unit can be deduced by linearly fitting the exposure condition. In the node 505, the exposure condition after the compensation of the current exposure unit is saved, and whether the current exposure unit is the last one is judged at the node 506, if so, the current edge compensation algorithm is ended; if not the last, the coordinates of the next exposure unit are obtained in node 507 and returned to node 503 where the edge compensation algorithm continues for the next exposure unit.
The exposure conditions of each complete exposure unit and each incomplete exposure unit in the wafer surface can be respectively compensated and calculated by an exposure compensation algorithm and an edge compensation algorithm, so as to obtain the exposure conditions after the correction of each exposure unit. However, if different exposure conditions are used for each exposure unit during the photolithography process, redundancy is caused by excessive exposure conditions, and the photolithography machine cannot support the use of such a large number of exposure conditions during a single photolithography process in the actual production process. For this reason, the exposure conditions with similar parameters must be approximately unified according to the partition, so that the number of exposure conditions used in a single photolithography process is reduced to several. After the corrected exposure conditions of the exposure units are obtained, the exposure units are partitioned by a partitioning algorithm, and the exposure units in the same partition have the same exposure conditions.
As an example, after obtaining the corrected exposure conditions of the plurality of exposure units, partitioning the plurality of exposure units, and correcting the exposure conditions of the exposure units in the same partition so that the exposure units in the same partition have the same exposure conditions. As shown in fig. 6, is a flow chart of the partitioning algorithm of fig. 3. After the start of the node, the exposure conditions for all exposure units on the wafer are acquired at node 601, and the evaluation of the exposure conditions is normalized at node 602, for example for the main parameters in the exposure conditions: and (3) giving different weights to focal length and energy during normalization processing to obtain a distribution diagram of the normalized exposure condition in the wafer surface. At node 603, the distribution of normalized exposure conditions is subjected to blurring and partitioning, so that exposure conditions with similar values are partitioned into the same partition, and the exposure conditions of the partition are determined by calculating an average value or the like. As shown in fig. 8, according to the partitioning algorithm, the exposure units in the wafer are divided into five partitions, the exposure units marked with numbers 1 to 5 respectively belong to first to fifth partitions, each partition has different and unique exposure conditions, and the photolithography process is performed on the exposure units in the partitions by adopting uniform exposure conditions. The partitioned normalized exposure conditions are denormalized at node 604 to obtain specific parameters of exposure conditions such as focus and energy. The exposure conditions for all exposure units on the wafer are saved at node 605. And carrying out a photoetching process according to the stored corrected exposure conditions. As shown in fig. 9, the profile of the line width measured by the in-plane exposure unit after the photolithography process using the corrected exposure conditions is shown. As can be seen from fig. 9, after the partition exposure of the compound algorithm in this embodiment is adopted, the range of the line width measured by the exposure unit in the wafer surface is reduced to 0.04 μm, and compared with the range of fig. 7, the range is greatly reduced, which can greatly improve the stability of the photolithography process and ensure the yield of the product.
As an example, after obtaining the corrected exposure conditions of the plurality of exposure units, the method further includes a step of exposing each of the exposure units with the exposure conditions, and obtaining pattern morphology and line width of the complete exposure unit to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again. Through the negative feedback process, dynamic cyclic correction of exposure conditions can be established in the production process of the quantitative product, so that the appearance and line width result of the exposure pattern are stabilized within the specification range. Optionally, in the actual mass production process, in the photolithography exposure process of the products in different batches, the pattern morphology and the line width of the complete exposure unit in the previous batch are obtained, the exposure compensation algorithm, the edge compensation algorithm and the partition algorithm described in the embodiment are adopted to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit, and the exposure conditions are used in the photolithography exposure of the products in the next batch, so that the photolithography process result of the products is continuously stabilized within the set specification range.
Example two
The present embodiment provides a wafer exposure system, including:
the data storage module is used for storing focal length energy matrix tables of different products and lithography levels;
the photoetching exposure module divides a plurality of exposure units on the surface of the wafer, the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer, and the photoetching exposure module performs exposure treatment on each exposure unit of the wafer according to input exposure conditions and outputs the pattern morphology and line width of the exposure units;
the data processing module is used for acquiring the focus energy matrix table stored in the data storage module according to the information of the product and the photoetching hierarchy, correcting the exposure condition of each complete exposure unit according to the focus energy matrix table, enabling the pattern morphology and the line width of the complete exposure unit to accord with the specification, correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit, and outputting the corrected exposure condition to the photoetching exposure module.
As an example, the wafer exposure system in the present embodiment may be used to perform the wafer exposure method in the first embodiment. The photoetching exposure module divides a plurality of exposure units on the surface of the wafer and can carry out photoetching process according to the input exposure conditions; the data processing module is connected with the data storage module and the photoetching exposure module, can acquire a focal length energy matrix table from the data storage module, and outputs corrected exposure conditions to the photoetching exposure module. The data processing module can correct the exposure condition of each complete exposure unit according to the focal length energy matrix table, so that the pattern morphology and the line width of the complete exposure unit accord with the specification, and correct the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit. The algorithm processing procedure is as described in the first embodiment, and is not described herein.
As an example, the data processing module may partition the plurality of exposure units after obtaining the corrected exposure conditions of the plurality of exposure units, and correct the exposure conditions of the exposure units in the same partition so that the exposure units in the same partition have the same exposure conditions. The partitioning process is shown in the partitioning algorithm flow chart of fig. 6, and the partitioning result shown in fig. 8 is obtained.
As an example, the data processing module outputs the exposure conditions to the lithography exposure module to expose each exposure unit after obtaining the corrected exposure conditions of a plurality of exposure units, and obtains the pattern morphology and the line width of the complete exposure unit from the lithography exposure module to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again. The data processing module may continuously correct the exposure conditions of each of the exposure units by establishing a negative feedback loop, as described in the first embodiment.
In summary, the present application provides a wafer exposure method and system, where the wafer exposure method includes the following steps: dividing a plurality of exposure units on the surface of a wafer, wherein the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer; acquiring a focal length energy matrix table of a photoetching layer to be exposed; obtaining the pattern morphology and line width of each complete exposure unit after exposure under the initial exposure condition; correcting the exposure condition of each complete exposure unit according to the focal length energy matrix table to enable the pattern morphology and line width of the complete exposure unit to accord with the specification; and correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit. The method and the device can greatly improve the uniformity of the pattern morphology and the line width in the wafer surface by correcting the exposure conditions of the complete exposure unit according to the pattern morphology and the line width of the complete exposure unit and correcting the exposure conditions of the incomplete exposure unit according to the exposure conditions of the complete exposure unit adjacent to the incomplete exposure unit.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (11)
1. A wafer exposure method, comprising the steps of:
dividing a plurality of exposure units on the surface of a wafer, wherein the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer;
acquiring a focal length energy matrix table of a photoetching layer to be exposed;
obtaining the pattern morphology and line width of each complete exposure unit after exposure under the initial exposure condition;
correcting the exposure condition of each complete exposure unit according to the focal length energy matrix table to enable the pattern morphology and line width of the complete exposure unit to accord with the specification;
and correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit.
2. The wafer exposure method according to claim 1, wherein after the corrected exposure conditions of the plurality of exposure units are obtained, the plurality of exposure units are partitioned, and the exposure conditions of the exposure units in the same partition are corrected so that the exposure units in the same partition have the same exposure conditions.
3. The wafer exposure method according to claim 1, wherein the pattern topography and line width of the complete exposure unit are obtained by measuring a process control monitor unit in the complete exposure unit.
4. The wafer exposure method according to claim 1, wherein the method of correcting the exposure condition of the incomplete exposure unit includes: and carrying out weighted average calculation on a plurality of exposure conditions of the complete exposure units adjacent to the incomplete exposure unit.
5. The wafer exposure method according to claim 1, wherein the method of correcting the exposure condition of the incomplete exposure unit includes: and calculating linear variation trend of a plurality of exposure conditions of a plurality of complete exposure units from the incomplete exposure unit to the center of the wafer.
6. The wafer exposure method according to claim 1, further comprising the steps of exposing each of the exposure units using the exposure conditions after obtaining the corrected exposure conditions of the plurality of exposure units, and obtaining pattern morphology and line width of the complete exposure unit to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again.
7. The method according to claim 6, wherein during the photolithography exposure of different batches of products, the pattern morphology and line width of the complete exposure unit of the previous batch are obtained, and the exposure conditions of the complete exposure unit and the incomplete exposure unit are corrected, and the exposure conditions are used in the photolithography exposure of the next batch of products.
8. The method of claim 1, wherein the step of obtaining a table of a focal energy matrix of the lithography layer to be exposed comprises: and establishing a focal length energy matrix table library aiming at different products and different lithography levels, and calling the focal length energy matrix table according to the product and lithography level information.
9. A wafer exposure system, comprising:
the data storage module is used for storing focal length energy matrix tables of different products and lithography levels;
the photoetching exposure module divides a plurality of exposure units on the surface of the wafer, the exposure units comprise complete exposure units positioned in the inner area of the wafer and incomplete exposure units positioned in the edge area of the wafer, and the photoetching exposure module performs exposure treatment on each exposure unit of the wafer according to input exposure conditions and outputs the pattern morphology and line width of the exposure units;
the data processing module is used for acquiring the focus energy matrix table stored in the data storage module according to the information of the product and the photoetching hierarchy, correcting the exposure condition of each complete exposure unit according to the focus energy matrix table, enabling the pattern morphology and the line width of the complete exposure unit to accord with the specification, correcting the exposure condition of the incomplete exposure unit according to the corrected exposure condition of the complete exposure unit adjacent to the incomplete exposure unit, and outputting the corrected exposure condition to the photoetching exposure module.
10. The wafer exposure system of claim 9, wherein the data processing module, after obtaining the corrected exposure conditions for the plurality of exposure units, partitions the plurality of exposure units, corrects the exposure conditions for each of the exposure units in the same partition so that each of the exposure units in the same partition has the same exposure conditions.
11. The wafer exposure system of claim 9, wherein the data processing module outputs the exposure conditions to the lithography exposure module to expose each of the exposure units after obtaining the corrected exposure conditions for the plurality of exposure units, and obtains a pattern profile and a line width of the complete exposure unit from the lithography exposure module to correct the exposure conditions for the complete exposure unit and the incomplete exposure unit again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310185221.XA CN116184776A (en) | 2023-03-01 | 2023-03-01 | Wafer exposure method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310185221.XA CN116184776A (en) | 2023-03-01 | 2023-03-01 | Wafer exposure method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116184776A true CN116184776A (en) | 2023-05-30 |
Family
ID=86448466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310185221.XA Pending CN116184776A (en) | 2023-03-01 | 2023-03-01 | Wafer exposure method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116184776A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116859680A (en) * | 2023-07-14 | 2023-10-10 | 江苏影速集成电路装备股份有限公司 | Exposure method and exposure device for wafer |
| CN116954039A (en) * | 2023-09-21 | 2023-10-27 | 合肥晶合集成电路股份有限公司 | Method and device for determining photoetching process window, storage medium and electronic equipment |
-
2023
- 2023-03-01 CN CN202310185221.XA patent/CN116184776A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116859680A (en) * | 2023-07-14 | 2023-10-10 | 江苏影速集成电路装备股份有限公司 | Exposure method and exposure device for wafer |
| CN116859680B (en) * | 2023-07-14 | 2024-04-30 | 江苏影速集成电路装备股份有限公司 | Exposure method and exposure device for wafer |
| CN116954039A (en) * | 2023-09-21 | 2023-10-27 | 合肥晶合集成电路股份有限公司 | Method and device for determining photoetching process window, storage medium and electronic equipment |
| CN116954039B (en) * | 2023-09-21 | 2023-12-08 | 合肥晶合集成电路股份有限公司 | Method and device for determining photoetching process window, storage medium and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116184776A (en) | Wafer exposure method and system | |
| US10739688B2 (en) | Method and apparatus for fabricating wafer by calculating process correction parameters | |
| US8046722B2 (en) | Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device | |
| US8440475B2 (en) | Alignment calculation | |
| US7933015B2 (en) | Mark for alignment and overlay, mask having the same, and method of using the same | |
| US7760931B2 (en) | Apparatus and method for measuring at least one of arrangement and shape of shots on substrate, exposure apparatus, and device manufacturing method | |
| KR101492317B1 (en) | Method of optimizing design for manufacturing(dfm) | |
| EP2620976A1 (en) | Overlay model for aligning and exposing semiconductor wafers | |
| CN115309005A (en) | Method and apparatus for optimizing a lithographic process | |
| US6948149B2 (en) | Method of determining the overlay accuracy of multiple patterns formed on a semiconductor wafer | |
| US11378891B2 (en) | Method for determining contribution to a fingerprint | |
| US7463333B2 (en) | Multi-exposure lithography system providing increased overlay accuracy | |
| US6136478A (en) | Mask pattern correction method and exposure mask to be used for such a method | |
| US11366397B2 (en) | Method and apparatus for simulation of lithography overlay | |
| JP2023507780A (en) | Wafer exposure method and wafer fabrication assembly using wafer model | |
| CN110568726B (en) | Exposure focusing compensation method | |
| JP2011044554A (en) | Exposure control apparatus, and method of manufacturing semiconductor device | |
| US20060026550A1 (en) | Mask for fabricating semiconductor devices and method for designing the same | |
| CN114077166B (en) | Method for obtaining critical dimension rocking curve of photoetching technology | |
| US7164960B2 (en) | Apparatus for correcting a plurality of exposure tools, method for correcting a plurality of exposure tools, and method for manufacturing semiconductor device | |
| JP2023053800A (en) | Method for determining arrangement of a plurality of shot areas on substrate, exposure method, exposure device, article production method, program and information processing device | |
| US20200310254A1 (en) | Method for controlling a manufacturing apparatus and associated apparatuses | |
| CN114326313B (en) | Method for simultaneously monitoring multiple lighting conditions | |
| US20230043696A1 (en) | Method and apparatus for manufacturing semiconductor device and method and system for exposing semiconductor | |
| US10809633B1 (en) | Overlay control with corrections for lens aberrations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |