CN116170160A - Physical unclonable function circuit and application thereof - Google Patents
Physical unclonable function circuit and application thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- G—PHYSICS
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- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2103—Challenge-response
Abstract
The invention provides a physical unclonable function circuit and application thereof, belonging to the technical field of novel storage and calculation. The invention minimizes the hardware cost required to complete the exclusive-or/exclusive-or operation required by the PUF in a single device by non-monotonic bipolar transfer characteristics and non-volatile threshold voltage modulation. The invention not only utilizes the physical random mechanism of voltage modulation of the threshold-adjustable transistor after programming, namely, the same transistor has certain random difference in the middle threshold state after undergoing the same pre-programming twice, thus realizing the reconfigurable capability of challenge-response; the most common multi-row multi-column transistor array is also directly integrated into the PUF structure, greatly simplifying circuit design and working steps.
Description
Technical Field
The invention relates to the technical field of physical unclonable function design, in particular to a circuit structure of a novel nonvolatile device-based low-power consumption reconfigurable physical unclonable function and a reconfigurable registration and verification method.
Background
With the rapid development of modern information technology and integrated circuit manufacturing technology, the demands of people on hardware security in the fields of national defense and military, commercial confidentiality, civil medical use and the like are more remarkable. Particularly, in the present day of the explosive expansion of the internet of things, the number of access of global internet of things devices is over 200 hundred million, and more edge hardware devices become key endpoints vulnerable to external attack. To cope with potential security risks, applications using Physical Unclonable Functions (PUFs) for user authentication, key generation, etc. have been proposed. As a physical entity, a PUF can be subjected to an externally undetectable, mathematically unpredictable black box processing of a given input signal (challenge signal) and thus converted into an output signal (response signal). The mapping of the input-output signal (challenge-response pair) of the PUF as a "fingerprint" of the physical entity can be used to confirm the legal identity of the device or user.
Since the "fingerprint" is determined only by physical differences and manufacturing variations inside the PUF, and it has tamper-proof, non-modelable, collision-resistant, reproducible properties, etc., PUFs have received high attention from researchers in the field of hardware security when they were proposed. Traditional CMOS device schemes such as an Arbiter Arbiter-PUF based on delay and a ring oscillator RO-PUF based on oscillation frequency are sequentially proposed; novel nonvolatile NVM device schemes based on resistive random access memory RRAM-PUF, magnetic random access memory MRAM-PUF, ferroelectric transistor FeFET-PUF and the like.
However, the existing PUF implementation technologies all have certain disadvantages: in one aspect, CMOS-based schemes require more complex circuit designs, with hardware and power consumption overhead limiting their deployment at the edge end of the internet of things device, which also presents a challenge-response non-reconfigurable problem based on manufacturing process bias randomness (because the process random mechanism is non-reconfigurable); on the other hand, existing NVM-based schemes are complex in steps at programming and registration, and physical fluctuations introduce large verification errors. These problems all present new challenges for PUF implementations, especially for edge-side applications. By combining the analysis, the high-stability and strong PUF circuit structure design with low power consumption, low circuit overhead and good reconfigurable capability is realized, and has very remarkable significance.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a physical unclonable function based on a threshold-adjustable field effect transistor array with bipolar characteristics and a challenge-response pair generation method thereof, and compared with PUF structures based on various CMOS or NVM device designs reported before, the invention reduces the required hardware cost to the minimum (one device) by completing the exclusive-or operation required by the PUF in a single device through non-monotonic bipolar transfer characteristics and nonvolatile threshold voltage modulation. The invention not only utilizes the physical random mechanism of voltage modulation of the threshold-adjustable transistor after programming (the same transistor has a certain random difference in the middle threshold state after undergoing the same pre-programming twice) as an entropy source to realize the reconfigurable capability of challenge-response, but also directly integrates the most common multi-row and multi-column transistor array into a PUF structure, thereby greatly simplifying the circuit design and the working steps.
A Physically Unclonable Function (PUF) circuit, the PUF circuit comprising: the array of transistors, and peripheral decoding circuit, drive circuit, read circuit (including multiplexer and differential amplifier), characterized by that, the said array of transistors forms the array structure of multiple rows and multiple columns by the bipolar characteristic field effect transistor that is connected each other, the word line WL of each row of transistors in the said array of transistors is connected to decoding circuit; the bit line BL of each column transistor is connected to the driving circuit, and the sense line SL is connected to the reading circuit; the drain electrode of the bipolar characteristic field effect transistor is connected with the bit line BL, the grid electrode of the bipolar characteristic field effect transistor is connected with the word line WL, the source electrode of the bipolar characteristic field effect transistor is connected with the sensing line SL, the bipolar characteristic field effect transistor adopts a semiconductor material with electron and hole bipolar conductive characteristics as a channel or substrate material, or adopts metal or metal silicide as a source drain material, so that the field effect transistor with a source drain symmetrical structure shows a non-monotonic bipolar transfer characteristic curve, and meanwhile, a layer of storage layer is inserted into a grid electrode stacking layer of the bipolar characteristic field effect transistor, and the storage layer adopts a semiconductor material formed by a floating gate/capturing layer and a tunneling dielectric layer, and modulates the threshold voltage of the transistor through capturing/capturing charges of the channel; or a layer of ferroelectric material is adopted, and the threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric material, so that the field effect transistor with bipolar characteristic and the modulated threshold voltage is formed.
The gate stack in the bipolar characteristic field effect transistor is based on a metal-ferroelectric layer-semiconductor, metal-ferroelectric layer-insulating layer-semiconductor, metal-ferroelectric layer-metal-insulating layer-semiconductor or other structure, wherein the ferroelectric layer serves as a storage layer of the transistor.
The semiconductor material in the bipolar characteristic field effect transistor gate stack is small organic molecules, polymers, two-dimensional materials, oxides and organic-inorganic hybrid materials.
The ferroelectric material in the bipolar characteristic field effect transistor gate stack adopts HfO doped with a certain proportion of Zr, al, si, la and other elements 2 Multi-domain ferroelectric materials and other perovskite ferroelectric materials.
The decoding circuit is used for decoding the externally input challenge signals into the corresponding word lines WL of the transistor array and addresses of the multiplexer MUX in the reading circuit; the driving circuit is used for providing programming voltage, reading voltage and power supply voltage required in the reconfigurable registering and verifying process, and comprises the step of providing driving voltage V for bit line BL of bipolar characteristic field effect transistor array dd Providing a read voltage V for the word line WL read And a programming voltage V prg Etc.; the reading circuit is used for selecting, reading out and comparing the array current and generating response signals.
Further, there is provided a challenge-response pair generating method of the above-mentioned Physical Unclonable Function (PUF) circuit for a reconfigurable enrollment and verification process of the PUF, the steps of which include:
1) After an n+m-bit challenge signal is input to the PUF circuit, the decoding circuit maps N bits to N rows WL word line levels of an array size n×k; the M bits will be translated to the address of the multiplexer MUX in the read circuit. After the challenge signal is input into the transistor array, each transistor performs XNOR operation of integrating input value and storage value, the essence of the array layer is that N-bit challenge signal and a binary matrix of N rows and K columns are subjected to XNOR operation bit by column, and the XNOR result of each column is subjected to Hamming weight summation and reflected as column current on SL;
2) The multiplexer will select two column currents from the K column currents according to the values corresponding to the M bits and input them into the differential amplifier SA to effect the generation of the response signal: when the first column current is greater than the second column current, the SA generates a high level as a response signal '1' output; when the first column current is smaller than the second column current, the SA generates a low level as a response signal "0" output. Finally, the MUX and SA in the read circuit together achieve conversion of the current domain analog signal to the output digital signal, which together with the input signal forms the CRP.
Further, a random state generating method of the physical unclonable function PUF circuit is provided, which is used for a reconfigurable enrollment and verification process of the PUF, and the steps include:
1) And (5) state erasure. Fixing all bit lines BL and sense lines SL to low level; and applying negative voltage with a first preset high level for a first preset time period on all word lines WL, and equivalently, completely erasing the states of the bipolar characteristic field effect transistor array to a high threshold state.
2) Pre-programming. Fixing all bit lines BL and sense lines SL to low level; applying a positive voltage of a second preset high level for a second preset duration to all word lines WL, and equivalently, changing the state of the bipolar characteristic field effect transistor array from a high threshold to an intermediate threshold state. According to the random fluctuation characteristics of the transistors, the same transistor has a certain random difference between the pre-programmed intermediate threshold states after being subjected to the same pre-programming twice.
3) And comparing the currents. Fix all bit lines BL to the driving voltage V dd The method comprises the steps of carrying out a first treatment on the surface of the Applying a positive voltage with a third preset time length and a third preset high level to word lines WL of one row, wherein the word lines WL of other rows are all low level; on the premise of not changing the state of the threshold corresponding to the storage layer, reading the drain current corresponding to the transfer characteristic curve of the transistor on the sensing line SL, and recording the drain current as the on-state current after the first pre-programming; repeatedly executing the steps 1 to 3 to obtain the current of the transistor on the sensing line SL for the new time, and recording the current as the on-state current after the second pre-programming; comparing the on-currents after the two pre-programming, if the first on-current is larger, the transistor is marked as "1", and if the first on-current is smaller, the transistor is marked as "0".
4) Programming. Bit lines BL and sense lines SL corresponding to all transistors marked as "1" are fixedAt a low level (zero voltage), the bit line BL and sense line SL corresponding to the transistor marked as "0" are fixed at an intermediate level (optionally 1/3V dd 、1/2V dd Preventing write crosstalk); applying a positive voltage of a fourth preset high level for a fourth preset duration to the word line WL of the certain row, equivalently, programming all the transistor states marked as "1" in the bipolar characteristic field effect transistor array to a low threshold state, while the transistor states marked as "0" will remain unchanged. Then, symmetrical operation is performed, the bit lines BL and the sense lines SL corresponding to all the transistors marked as '0' are fixed to be low level, and the bit lines BL and the sense lines SL corresponding to the transistors marked as '1' are fixed to be medium level; applying a negative voltage of a fourth preset high level for a fourth preset time period to the word line WL of the certain row, equivalently, programming all the transistor states marked as "0" in the bipolar characteristic field effect transistor array to a high threshold state, while the transistor states marked as "1" are unchanged.
The invention aims to provide a three-terminal or four-terminal field effect transistor with bipolar characteristics and symmetric source and drain, and the modulation of the threshold voltage of the transistor is completed by inserting a storage layer between a gate dielectric layer and a control gate, and compared with the prior art, the invention has the following beneficial effects:
1. the invention utilizes non-monotonic bipolar transfer characteristic and non-volatile threshold voltage modulation to complete linear inseparable exclusive-or/exclusive-or operation on a single transistor, so that the hardware cost of a single PUF unit is reduced to a theoretical minimum value; the circuit has a simple structure, so that the complexity and the energy consumption in the registration and verification process are greatly reduced;
2. the invention uses the physical random mechanism of voltage modulation after programming pulse is applied to the grid electrode of the transistor as an entropy source, and does not use the process random mechanism of the traditional PUF as the entropy source, thereby realizing erasure and reconstruction of challenge-response, greatly increasing the use scene of the PUF and realizing high-randomness challenge-response on the premise of ensuring high process consistency;
3. the invention directly integrates the common multi-row multi-column memory array into the PUF circuit, and utilizes the high-energy-efficiency low-delay advantage of the integrated architecture; through the design scheme of column comparison, the one-dimensional cascade of units of the conventional PUF design thought is expanded to two dimensions, and the modeling attack resistance of the PUF is greatly improved.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a physical unclonable function;
fig. 2 is a schematic diagram of a Physical Unclonable Function (PUF) array structure and a cell structure provided by an embodiment of the present invention, including transfer characteristic curves (drain-source current-gate-source voltage) of the threshold-adjustable field effect transistor with bipolar characteristics before and after threshold voltage modulation;
FIG. 3 is a diagram showing a bipolar transfer characteristic of a Physical Unclonable Function (PUF) cell structure in two threshold voltage states, according to an embodiment of the present invention, implementing an exclusive-OR operation of an input level and stored information in a single transistor cell;
fig. 4 is a schematic diagram of the operation of a challenge signal and a schematic diagram of the generation of a response signal when the PUF circuit provided in the embodiment of the present invention performs verification;
fig. 5 is a flowchart illustrating the operation of a PUF circuit according to an embodiment of the present invention, including state erase, pre-programming, read current, compare current, and program, on registering or reconstructing a transistor cell.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to fig. 1 to 5. While specific embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Fig. 1 is a schematic diagram of the operation of a physical unclonable function, which is a physical entity that processes an input challenge signal into a response signal for input. According to the Challenge-response Pair (CRP) of the PUF, it can be used as its unique identity code for subsequent hardware security requirements. The complexity in PUF design ensures that it is difficult to predict and model the CRP relationship, and CRP relationships between the same PUF are all distinct and unique, which ensures the CRP relationship as collision resistance of the PUF fingerprint. When the PUF is applied, the CRPs are often classified into strong PUFs (exponential type) and weak PUFs (polynomial type and the like) according to the growing speed of the CRPs along with the size of the PUFs, wherein the application scenario of the weak PUFs is extremely limited, so that the embodiment is designed for CRP requirements of the strong PUFs.
PUFs often operate as secure authentication chips for edge devices embedded therein during legal identity authentication prior to the devices establishing communication. In some scenarios, there is a need to re-register the end-device, or to change the device owner or device information, which requires that the fingerprint of the PUF is erasable and reconfigurable in certain situations, otherwise the fingerprint does not change before and after re-registration, which would present a significant security risk. The present embodiment will thus be designed towards the reconfigurable requirements of PUFs.
Fig. 2 details a schematic diagram of a PUF array structure provided according to one embodiment of the present invention.
In this embodiment, a schematic diagram of a transistor structure having non-monotonic bipolar transfer characteristics and non-volatile threshold voltage modulation is shown on the right side of fig. 2. In one aspect, the transistor uses a semiconductor material with electron and hole bipolar conductive characteristics as a channel or substrate material (or uses metal or metal silicide as a source-drain material), so that the field effect transistor with a source-drain symmetrical structure shows a non-monotonic bipolar transfer characteristic curve; in another aspect, a memory layer is inserted in the gate stack of the transistor, the memory layer being formed of a semiconductor material comprising a floating gate/trapping layer and a tunneling dielectric layer, the non-monotonic bipolar transfer characteristic being shifted by modulating the threshold voltage of the transistor (or modulating the threshold voltage of the transistor by changing the polarization state of the ferroelectric material, using a layer of ferroelectric material) by trapping/de-trapping charges to the channel.
When the states corresponding to the memory layers are different, the threshold voltages of the transistors are different, resulting in a transfer curve (I ds -V gs ) A shift as shown in the lower right of fig. 2 occurs, i.e. a modulation of the threshold voltage after a programming pulse applied to the corresponding gate. In particular, when the device is in the intermediate threshold voltage state, there is a relatively significant random fluctuation in the transfer curve of the transistor, i.e., after the same transistor is subjected to the same pre-programming twice, there is a certain random difference in the intermediate threshold state (even if the initial state, the pre-programmed preset duration, the preset level, etc. are identical). In this embodiment, this physical randomness is exploited as an entropy source for the PUF, rather than the process randomness exploited by conventional CMOS. The benefits are obvious: the process randomness is determined when leaving the factory, the fingerprint is non-reconfigurable, and the physical randomness of the device can be reflected and utilized through a larger programming signal when being registered in each reconfigurable way; when a step such as verification is performed without randomness, the effect on the PUF fingerprint is avoided by non-destructive small signal reading.
In this embodiment, the circuit structure for implementing PUF based on the threshold-adjustable field effect transistor array with bipolar characteristics is shown in the left side of fig. 2. The drain electrode of the transistor is connected with a bit line BL, the grid electrode of the transistor is connected with a word line WL, and the source electrode of the transistor is connected with a sense line SL; the word line WL of each row of transistors in the transistor array is connected to a decoding circuit; the bit line BL of each column transistor is connected to the driving circuit, and the sense line SL is connected to the reading circuit; the decoding circuit is used for decoding the externally input challenge signals into the corresponding word lines WL of the transistor array and addresses of the multiplexer MUX in the reading circuit. The driving circuit is used for providing programming voltage, reading voltage and power supply voltage required in the reconfigurable registering and verifying process, and comprises the step of providing driving voltage V for bit line BL of bipolar characteristic field effect transistor array dd Providing a read voltage V for the word line WL read And a programming voltage V prg Etc. The reading circuit is used for selecting, reading out and comparing the array current and generating response signals.
According to the inventionFig. 3 depicts a schematic diagram of the logical operation of a PUF pattern for use in the verification process of a PUF. In the fields of cryptography and hardware security, encryption of data, generation of a data stream, etc. are often performed by bitwise exclusive-or operations, so in this embodiment a scheme is provided for implementing the exclusive-or operation on a single transistor for the PUF verification process. The non-monotonic bipolar transfer characteristic enables the transistor to have a symmetrical transfer characteristic curve, and the non-volatile threshold voltage modulation enables the transfer characteristic curve of the transistor to be shifted; the high and low threshold voltage states correspond to "0" and "1" stored by the transistor, respectively. If the gate read voltage (word line voltage V) WL ) The high level represents an input "1", the low level represents an input "0", and when the input level and the stored information are the same, the transistor is turned on and outputs an on-state current I at the sense line SL H And if the two are different, the off-state current I is output S The operation of the same or XNOR can be completed by the method of the same or XNOR; if the definition is reversed, an exclusive-or XOR operation may be completed.
Fig. 2 and 4 describe in detail the challenge-response pair generation method of a PUF for the verification process of the PUF according to one embodiment of the invention.
As shown in fig. 2, after an n+m-bit challenge signal is input to the PUF, the decoding circuit compiles it, where: n bits will map to N rows WL word line levels of array size N K; the M bits will be translated into the address of the multiplexer MUX. After the challenge signal is input into the array, each transistor unit performs an XNOR operation with integrated input value and storage value, and the essence at the array level is that the N-bit challenge signal and a binary matrix of N rows and K columns are subjected to a bitwise XNOR operation by columns, and the XNOR result of each column is subjected to hamming weight summation, which is reflected as the column current magnitude on SL, that is, the processing procedure of the input challenge signal inside the PUF.
Then, the multiplexer will select two column currents from the K column currents according to the values corresponding to the M bits, and input them into the differential amplifier SA to realize the generation of the response signal: when the first column current is greater than the second column current, the SA generates a high level as a response signal '1' output; when the first column current is smaller than the second column current, the SA generates a low level as a response signal "0" output. Finally, the MUX and SA in the read circuit together achieve conversion of the current domain analog signal to the output digital signal, which together with the input signal forms the CRP.
According to the described embodiment, the PUF implements processing of the n+m-bit challenge signal, resulting in a 1-bit binary response signal that is output. Based on the challenge-response relationship, the validity of the PUF can be authenticated if the agreement is higher than a certain percentage after comparison with the CRP relationship registered at enrollment.
The number of CRPs corresponding to the PUF provided in this embodiment increases exponentially with the size (nxk) of the PUF circuit. Assuming that the PUF array is an array structure of g×g transistors, the corresponding challenge signals total about 2 G * G log G, whereas the response signal is only 1 bit, and the PUF size is G 2 Thus, the CRP quantity of the examples was related to scale as G.about.2 G * log, an exponentially growing relation of strong PUF requirements.
As a specific example, the CRP relationship of the PUF is given in fig. 4. Since the 0/1 value of 12 bits in the challenge signal is arbitrary, N bits correspond to 2 12 A possible challenge signal; while 4 bits determine the two columns selected by the MUX, essentially ordering the 4 column currents with a temporal complexity of O (4 2 ) Or O (4 x log 4).
Fig. 5 details a method of random state generation of a PUF for use in a reconfigurable enrolment process of a PUF, according to one embodiment of the invention.
Before the edge device delivers the user, the cloud assigns a random ID to each device and initializes and registers the PUF of the device. The cloud end inputs a large number of random challenge signals to the PUF, records corresponding response signals and establishes a CRP library corresponding to the equipment ID. After delivery, if the edge device needs to authenticate its legal identity, the cloud end will arbitrarily select a large number of challenge signals from the CRP library of the device and collect the response signals of the PUF, and compare with the previous result to complete device authentication. If the device needs to be replaced by a user or reset, the cloud will erase and randomly reconstruct the CRP of the PUF, assign a new ID, and re-complete the library establishment and library comparison process.
Accordingly, the reconfigurable enrollment process requires erasure and random reconstruction of CRPs of the PUF, with completely random rewriting of all CRP relationships by the entropy source of the PUF. In the embodiment of the invention, the random fluctuation characteristic of the voltage modulation of the transistor after the programming pulse is applied to the gate electrode is utilized, namely, after the same transistor is subjected to the same pre-programming twice, the intermediate threshold state also has certain random difference (even if the conditions of the initial state, the pre-programmed preset time period, the preset level and the like are completely the same). At this time, the read operation is performed, that is, fluctuation of the intermediate threshold state is represented as a difference in current, and the program operation is performed according to the difference in current, so that random differences in current are newly fixed as "0" and "1" of the stored data. Because of the unpredictability of intermediate threshold state fluctuations, the data stored in the transistor array within the PUF is also completely random and unpredictable, and the input challenge signal is subjected to XOR/XNOR operations with these random numbers, and the hamming weights are compared by column to generate a random response signal, comprising the steps of:
1) And (5) state erasure. Fixing all bit lines BL and sense lines SL to low level; and applying negative voltage with a first preset high level for a first preset time period on all word lines WL, and equivalently, completely erasing the states of the bipolar characteristic field effect transistor array to a high threshold state.
2) Pre-programming. Fixing all bit lines BL and sense lines SL to low level; the state of the bipolar characteristic field effect transistor array is changed from a high threshold state to a middle threshold state by applying positive voltages of a second preset high level for a second preset duration on all word lines WL.
3) And (5) reading the current. Fix all bit lines BL to the driving voltage V dd The method comprises the steps of carrying out a first treatment on the surface of the Applying a third preset high level for a third preset time period to the word line WL of a certain rowThe word lines WL of the other rows are all low level at positive voltage; on the premise of not changing the threshold state corresponding to the storage layer, the drain current corresponding to the transistor transfer characteristic curve on the sensing line SL is read.
4) Repeating the steps 1-3 to obtain a new drain current on the sensing line SL. According to the random fluctuation characteristic of the voltage modulation of the transistor after the programming pulse is applied to the grid electrode, after the same transistor is subjected to the same pre-programming twice, certain random difference exists in the middle threshold state, and even if the conditions of the initial state, the pre-programmed preset time length, the preset level and the like are identical.
5) Current comparison and programming. Transistors with a current greater than the second time after the first pre-programming are noted as "1" and transistors with a current less than the second time after the first pre-programming are noted as "0". Further, the bit line BL and the sense line SL corresponding to all the transistors marked as "1" are fixed to a low level (zero voltage), and the bit line BL and the sense line SL corresponding to the transistors marked as "0" are fixed to an intermediate level (alternatively 1/3V dd 、1/2V dd Preventing write crosstalk to these transistors); applying a positive voltage with a fourth preset time period and a fourth preset high level to the word line WL of the certain row, equivalently, programming all the transistor states marked as '1' in the bipolar characteristic field effect transistor array to a low threshold state, and keeping the transistor states marked as '0'. Further, the bit lines BL and the sense lines SL corresponding to all the transistors marked as "0" are fixed to a low level (zero voltage), and the bit lines BL and the sense lines SL corresponding to the transistors marked as "1" are fixed to an intermediate level (alternatively 1/3V) dd 、1/2V dd Preventing write crosstalk to these transistors); applying a negative voltage with a fourth preset time period and a fourth preset high level to the word line WL of the certain row, equivalently, programming all the transistor states marked as '0' in the bipolar characteristic field effect transistor array to a high threshold state, and keeping the transistor states marked as '1'.
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (7)
1. A physically unclonable function, PUF, circuit, the PUF circuit comprising: the array of transistors, and peripheral decoding circuit, drive circuit and read circuit, characterized by that, the said array of transistors forms the multi-row multi-column array structure by the bipolar characteristic field effect transistor that is connected each other, the word line WL of each row of transistors in the said array of transistors is connected to the decoding circuit; the bit line BL of each column transistor is connected to the driving circuit, and the sense line SL is connected to the reading circuit; the drain electrode of the bipolar characteristic field effect transistor is connected with the bit line BL, the grid electrode of the bipolar characteristic field effect transistor is connected with the word line WL, the source electrode of the bipolar characteristic field effect transistor is connected with the sensing line SL, the bipolar characteristic field effect transistor adopts a semiconductor material with electron and hole bipolar conductive characteristics as a channel or substrate material, or adopts metal or metal silicide as a source drain material, so that the field effect transistor with a source drain symmetrical structure shows a non-monotonic bipolar transfer characteristic curve, and meanwhile, a layer of storage layer is inserted into a grid electrode stacking layer of the bipolar characteristic field effect transistor, and the storage layer adopts a semiconductor material formed by a floating gate/capturing layer and a tunneling dielectric layer, and modulates the threshold voltage of the transistor through capturing/capturing charges of the channel; or a layer of ferroelectric material is adopted, and the threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric material, so that the field effect transistor with bipolar characteristic and the modulated threshold voltage is formed.
2. The physically unclonable function PUF circuit of claim 1, wherein the gate stack in the bipolar junction field effect transistor is a metal-ferroelectric layer-semiconductor, metal-ferroelectric layer-insulator-semiconductor, metal-ferroelectric layer-metal-insulator-semiconductor structure with the ferroelectric layer as an interposed memory layer.
3. The physically unclonable function PUF circuit of claim 2, wherein the semiconductor material in the bipolar junction field effect transistor gate stack is small organic molecules, polymers, two-dimensional materials, oxides, and organic-inorganic hybrid materials.
4. The physically unclonable function PUF circuit of claim 2, wherein the ferroelectric layer in the bipolar characteristic field effect transistor gate stack is Zr, al, si, la element doped HfO 2 Multi-domain ferroelectric materials and other perovskite ferroelectric materials.
5. The physically unclonable function PUF circuit of claim 1, wherein the decoding circuit is configured to decode an externally input challenge signal into addresses of a word line WL corresponding to the transistor array and a multiplexer MUX in the reading circuit; the driving circuit is used for providing programming voltage, reading voltage and power supply voltage required in the reconfigurable registration and verification process; the read circuit is used for selecting, reading out and comparing the array current and generating response signals, and comprises a multiplexer and a differential amplifier.
6. A method of generating a challenge-response pair for a physically unclonable function, PUF, circuit, characterized by a reconfigurable enrollment and verification process for a physically unclonable function, PUF, circuit according to claim 1, comprising the steps of:
1) After an n+m-bit challenge signal is input to the PUF circuit, the decoding circuit maps N bits to N rows WL word line levels of an array size n×k; after the challenge signal is input into the transistor array, each transistor performs XNOR operation of integrating the input value and the storage value, namely N-bit challenge signal and a binary matrix of N rows and K columns are subjected to XNOR operation bit by column, and the XNOR result of each column is subjected to Hamming weight summation and reflected as the column current on SL;
2) The multiplexer in the read circuit will select two column currents from the K column currents according to the values corresponding to the M bits and input them into the differential amplifier SA in the read circuit to effect the generation of the response signal: when the first column current is greater than the second column current, the differential amplifier SA generates a high level as a response signal "1" output; when the first column current is smaller than the second column current, the differential amplifier SA generates a low level as a response signal "0" output.
7. A method of generating a random state of a physically unclonable function, PUF, circuit, for use in the reconfigurable enrollment and verification process of a physically unclonable function, PUF, circuit of claim 1, comprising the steps of:
1) State erasure: fixing all bit lines BL and sense lines SL to low level; applying a negative voltage with a first preset time length and a first preset high level to all word lines WL, and completely erasing the states of the bipolar characteristic field effect transistor array to a high threshold state;
2) Pre-programming: fixing all bit lines BL and sense lines SL to low level; applying positive voltage with a second preset high level for a second preset duration on all word lines WL, and equivalently changing the state of the bipolar characteristic field effect transistor array from a high threshold to a middle threshold state;
3) Comparing the current: fix all bit lines BL to the driving voltage V dd The method comprises the steps of carrying out a first treatment on the surface of the Applying a positive voltage with a third preset time length and a third preset high level to word lines WL of one row, wherein the word lines WL of other rows are all low level; on the premise of not changing the state of the threshold corresponding to the storage layer, reading the drain current corresponding to the transfer characteristic curve of the transistor on the sensing line SL, and recording the drain current as the on-state current after the first pre-programming; repeatedly executing the steps 1 to 3 to obtain the current of the transistor on the sensing line SL for the new time, and recording the current as the on-state current after the second pre-programming; comparing the on-state currents after the two pre-programming, if the on-state current of the first time is larger, the transistor is marked as '1', and if the on-state current of the first time is smaller, the transistor is marked as '0';
4) Programming: the bit lines BL and the sense lines SL corresponding to all the transistors marked as "1" are fixed to low level, and the bit lines BL and the sense lines SL corresponding to the transistors marked as "0" are fixed to intermediate level; applying a positive voltage with a fourth preset time period and a fourth preset high level to the word line WL of the certain row, programming all transistor states marked as '1' in the bipolar characteristic field effect transistor array to a low threshold state, and keeping the transistor states marked as '0' unchanged; then, symmetrical operation is performed, the bit lines BL and the sense lines SL corresponding to all the transistors marked as '0' are fixed to be low level, and the bit lines BL and the sense lines SL corresponding to the transistors marked as '1' are fixed to be medium level; applying a negative voltage of a fourth preset high level for a fourth preset time period on the word line WL of the certain row, programming all transistor states marked as "0" in the bipolar characteristic field effect transistor array to a high threshold state, while the transistor states marked as "1" are unchanged.
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