CN116166178A - Basic storage unit management circuit and basic storage unit management method - Google Patents

Basic storage unit management circuit and basic storage unit management method Download PDF

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Publication number
CN116166178A
CN116166178A CN202111412802.XA CN202111412802A CN116166178A CN 116166178 A CN116166178 A CN 116166178A CN 202111412802 A CN202111412802 A CN 202111412802A CN 116166178 A CN116166178 A CN 116166178A
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Prior art keywords
storage unit
idle
basic
basic storage
bit
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CN202111412802.XA
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Chinese (zh)
Inventor
陆志豪
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202111412802.XA priority Critical patent/CN116166178A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A basic memory cell management circuit and a basic memory cell management method. The basic memory cell management circuit comprises a receiving circuit, a transmitting circuit, a first buffer and an idle basic memory cell controller. The first buffer is used for storing a bit table, wherein the bit table comprises a plurality of first bits which respectively correspond to a plurality of basic memory cells, and each first bit in the plurality of first bits is used for marking whether a corresponding basic memory cell is an idle basic memory cell or not. The idle basic memory cell controller is coupled to the receiving circuit, the transmitting circuit and the first buffer, and is used for managing the bit table stored in the first buffer and processing at least one basic memory cell corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table.

Description

Basic storage unit management circuit and basic storage unit management method
Technical Field
The present invention relates to data management, and more particularly, to a basic storage unit management circuit and a basic storage unit management method for an idle (idle) basic storage unit (basic storage unit).
Background
In a conventional switch, router or media access control (media access control, MAC), a memory, such as a static random access memory (static random access memory, SRAM), is typically divided into a plurality of basic memory cells, and a multi-bit (multi-bit) idle basic memory cell link list (link list) may be used to manage idle basic memory cells in the plurality of basic memory cells, however, some problems may occur. Since the address of an idle basic memory cell in the multi-bit idle basic memory cell link list is stored in the previous idle basic memory cell, the size of a memory (e.g., sram) having the multi-bit idle basic memory cell link list may be increased by the number of basic memory cells, which may increase the cost and the read time, and the throughput (throughput) of the acquire/release idle basic memory cell may be limited by the bandwidth of the memory, so a novel architecture is highly required to replace the idle basic memory cell link list.
Disclosure of Invention
It is therefore one of the objectives of the present invention to provide a basic memory cell management circuit and related basic memory cell management method, so as to solve the above-mentioned problems.
At least one embodiment of the present invention provides a basic storage unit management circuit, wherein the basic storage unit management circuit may include a receiving circuit, a transmitting circuit, a first buffer, and an idle basic storage unit controller. The first buffer is used for storing a bit table, wherein the bit table comprises a plurality of first bits which respectively correspond to a plurality of basic memory cells, and each first bit in the plurality of first bits is used for marking whether a corresponding basic memory cell is an idle basic memory cell or not. The idle basic storage unit controller is coupled to the receiving circuit, the transmitting circuit and the first buffer, and is configured to manage the bit table stored in the first buffer, and process at least one basic storage unit corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table, wherein when one basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit to a first logic value; and when the basic storage units of the basic storage units are not idle basic storage units, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit as a second logic value.
At least one embodiment of the present invention provides a basic storage unit management method. The basic storage unit management method may include: storing a bit table, wherein the bit table comprises a plurality of first bits corresponding to a plurality of basic memory cells, respectively, and each of the plurality of first bits is used for indicating whether a corresponding basic memory cell is an idle basic memory cell; and processing at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit according to the bit table by using an idle basic storage unit controller, and managing the bit table, wherein when one basic storage unit of the basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit as a first logic value, and when the basic storage unit of the basic storage units is not the idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit as a second logic value.
The present invention provides a basic storage unit management circuit, which can utilize a memory buffer storing a bit table and a register buffer to manage idle basic storage units, wherein the idle basic storage unit controller of the basic storage unit management circuit firstly finds a target second bit with a first logic value (e.g. 1) from a plurality of second bits of the register buffer to obtain a read address, reads a target effective idle storage unit marking field in the bit table of the memory buffer according to the read address, and finds at least one target first bit with a first logic value (e.g. 1) from the target effective idle storage unit marking field to obtain at least one idle basic storage unit, so that the time for reading the memory buffer can be greatly reduced.
Drawings
FIG. 1 is a diagram illustrating a correspondence between bits in a memory buffer and bits in a register buffer according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a basic memory cell management circuit according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a basic memory cell management circuit according to another embodiment of the present invention.
FIG. 4 is a flowchart of a basic storage unit management method according to an embodiment of the invention.
Symbol description
100,200,300: static random access memory buffer
101,201,301: bit table
110,210,310: buffer for temporary storage
a to d: effective idle memory cell indicator field
e-h: second bit
20,30: basic memory cell management circuit
220,320: idle basic memory cell controller
230,330: receiving circuit
240,340: transmission circuit
350: releasing basic memory cell buffers
B10, B21, B22, B27: first bit
S400, S402: step (a)
Detailed Description
FIG. 1 is a diagram illustrating a correspondence between bits in a memory buffer and bits in a register buffer according to an embodiment of the present invention. As shown in fig. 1, a memory buffer (e.g., SRAM buffer 100; for brevity, labeled "SRAM buffer" in fig. 1) may be used to store a bit table 101, where the bit table 101 may include 32 first bits (corresponding to 32 basic memory cells, respectively), and each of the 32 first bits may be used to indicate whether a corresponding basic memory cell is an idle basic memory cell, e.g., when a basic memory cell of the 32 basic memory cells is an idle basic memory cell, a first bit corresponding to the basic memory cell is a first logic value (e.g., 1); and when one basic memory cell in the 32 basic memory cells is not an idle basic memory cell, a first bit corresponding to the basic memory cell is a second logic value (e.g. 0). In addition, in order to save time for reading the memory buffer and to more quickly find the idle basic memory cells, the bit table may be divided into a plurality of valid idle memory cell indication fields (fields) in units of a plurality of bits, for example, mxN (e.g., mxn=32) first bits in the bit table 101 may be divided into N (e.g., n=4) valid idle memory cell indication fields (e.g., valid idle memory cell indication field a to valid idle memory cell indication field d) in units of M (e.g., m=8) bits.
The register buffer 110 may be configured to store 4 second bits (e.g., second bits e-h, which respectively correspond to valid idle memory location indication fields a-d) in the bit table 101, where each of the 4 second bits may be configured to indicate whether a corresponding valid idle memory location indication field includes at least one first bit having a first logic value (e.g., 1) (i.e., indicate whether 8 basic memory cells corresponding to 8 first bits in the corresponding valid idle memory location indication field include at least one idle basic memory cell). When one of the 4 active idle memory cell indicator fields includes at least one first bit having a first logic value (e.g., 1), the second bit corresponding to the active idle memory cell indicator field is the first logic value (e.g., 1); and when all the first bits included in one of the 4 valid idle memory cell indicator fields have a second logic value (e.g., 0) (i.e., there are no idle basic memory cells in the 8 basic memory cells corresponding to the 8 first bits in the valid idle memory cell indicator field), the second bit corresponding to the valid idle memory cell indicator field is the second logic value (e.g., 0). For example, since the valid idle_cell_flag field a in the bit table 101 includes 4 first bits having a first logic value (e.g., 1), the second bit e corresponding to the valid idle_cell_flag field a is the first logic value (e.g., 1). For another example, since all the first bits included in the valid idle memory cell indicator field c in the bit table 101 have the second logic value (e.g., 0), the second bit g corresponding to the valid idle memory cell indicator field c is the second logic value (e.g., 0).
FIG. 2 is a schematic diagram of a basic memory cell management circuit 20 according to an embodiment of the invention. As shown in FIG. 2, the basic memory cell management circuit 20 may include a memory buffer (e.g., SRAM buffer 200; labeled as "SRAM buffer" in FIG. 2 for brevity), a buffer 210, an idle basic memory cell controller 220, a receiving circuit 230, and a transmitting circuit 240, wherein the SRAM buffer 200 and the buffer 210 may be implemented by the SRAM buffer 100 and the buffer 110 shown in FIG. 1, respectively. The sram buffer 200 may be configured to store a bit table 201, in this embodiment, the bit table 201 may include 32 first bits (corresponding to 32 basic memory cells respectively), and the 32 first bits in the bit table 201 may be divided into 4 valid idle memory cell indication fields (e.g. valid idle memory cell indication field a-valid idle memory cell indication field d) in 8 bits, however, this is merely an example, and not a limitation of the present invention, and the size of the bit table 201 and the valid idle memory cell indication field division may be adjusted according to the requirement. The register buffer 210 may be configured to store 4 second bits (e.g., the second bits e-h, which respectively correspond to the valid idle_cell_flag field a-d in the bit table 201), however, this is only for illustration, and is not a limitation of the present invention, in practice, the number of the second bits stored in the register buffer 210 may depend on the number of the valid idle_cell_flag fields in the bit table 201. For brevity, similar contents of the sram buffer 200 and the buffer 210 are not repeated here.
The idle basic storage unit controller 220 is coupled to the sram buffer 200, the receiving circuit 230 and the transmitting circuit 240, and is configured to manage the bit table 201 stored in the sram buffer 200, and process at least one basic storage unit of at least one packet received by the receiving circuit 230 or transmitted by the transmitting circuit 240 according to the bit table 201, wherein when one basic storage unit of the 32 basic storage units corresponding to the 32 first bits of the bit table 201 is the idle basic storage unit, the idle basic storage unit controller 220 may set the first bit corresponding to the basic storage unit to a first logic value (e.g. 1); and when one of the 32 basic memory cells corresponding to the 32 first bits of the bit table 201 is not an idle basic memory cell, the idle basic memory cell controller 220 may set the first bit corresponding to the basic memory cell to a second logic value (e.g., 0). In addition, the idle basic storage unit controller 220 may be further coupled to the register buffer 210, wherein when one of the 4 valid idle storage unit indication fields of the bit table 201 includes at least one first bit having a first logic value (e.g. 1), the idle basic storage unit controller 220 may set a second bit corresponding to the valid idle storage unit indication field to the first logic value (e.g. 1); and when all the first bits included in one valid idle memory cell indicator field of the 4 valid idle memory cell indicator fields of the bit table 201 have the second logic value (e.g., 0), the idle basic memory cell controller 220 may set the second bit corresponding to the valid idle memory cell indicator field to the second logic value (e.g., 0).
When the receiving circuit 230 receives a received packet, the idle basic storage unit controller 220 may obtain at least one idle basic storage unit for buffering the received packet through the sram buffer 200 and the buffer 210, for example, the idle basic storage unit controller 220 may first find a target second bit (e.g., the second bit e, the second bit f or the second bit h) having a first logic value (e.g., 1) from among 4 second bits (e.g., the second bit e-the second bit h) of the buffer 210 to obtain a read address, and read a target valid idle storage unit indicator (e.g., the valid idle storage unit indicator a corresponding to the second bit e, the valid idle storage unit indicator b corresponding to the second bit f or the valid idle storage unit indicator d corresponding to the second bit h) in the bit table 201 of the sram buffer 200 according to the read address, and finally find at least one target idle storage unit having the first logic value (e.g., the first idle storage unit indicator 1) from the target idle storage unit indicator.
It should be noted that, after the at least one idle basic storage unit is used to temporarily store the received packet, the idle basic storage unit controller 220 may be further configured to update the at least one target first bit corresponding to the at least one idle basic storage unit from a first logic value (e.g. 1) to a second logic value (e.g. 0), and, when the at least one target first bit corresponding to the at least one idle basic storage unit is updated by the idle basic storage unit controller 220, the target valid idle storage unit flag containing the at least one target first bit has a second logic value (e.g. 0), the idle basic storage unit controller 220 may be further configured to update the second bit corresponding to the target valid idle storage unit flag in the buffer 210 from the first logic value (e.g. 1) to the second logic value (e.g. 0), and, on the other hand, when the at least one target valid storage unit flag containing the at least one target first bit corresponding to the at least one idle basic storage unit 220 is updated by the idle basic storage unit controller 220 has a second logic value (e.g. 1) and the at least one target valid storage unit flag containing the at least one target valid storage unit in the buffer 210 has a second logic value (e.g. 1). The idle basic unit controller 220 may implement updating of 32 first bits in the bit table of the sram buffer 200 and 4 second bits of the buffer 210 by pipeline (pipeline), but the present invention is not limited thereto.
When the transmission circuit 240 finishes transmitting a transmission packet, the transmission circuit 240 releases (releases) at least one basic storage unit corresponding to the transmission packet to the idle basic storage unit controller 220, and the idle basic storage unit controller 220 is configured to update at least one target first bit in at least one target valid idle storage unit indicator field in the bit table 201 of the sram buffer 200 from a second logic value (e.g. 0) to a first logic value (e.g. 1), that is, at least one basic storage unit corresponding to the at least one target first bit is at least one idle basic storage unit according to the at least one basic storage unit of the transmission packet. In addition, in the case that at least one target first bit in the original at least one target valid idle memory location indicator field has a second logic value (e.g., 0) (i.e., the original at least one target valid idle memory location indicator field does not have an idle basic memory location), when the at least one target first bit is updated by the idle basic memory location controller 220, the at least one target valid idle memory location indicator field containing the at least one target first bit contains at least one first bit having a first logic value (e.g., 1), the idle basic storage unit controller 220 may be further configured to update at least one second bit in the register buffer 210 corresponding to the at least one target valid idle storage unit indicator field from a second logic value (e.g. 0) to a first logic value (e.g. 1), and on the other hand, in case the original at least one target valid idle storage unit indicator field already includes at least one first bit having the first logic value (e.g. 1) (i.e. the original at least one target valid idle storage unit indicator field already has an idle basic storage unit), the idle basic storage unit controller 220 may be further configured to maintain the at least one second bit in the register buffer 210 corresponding to the at least one target valid idle storage unit indicator field to the first logic value (e.g. 1).
In addition, in order to reduce the power consumption of the memory buffer and save the bandwidth of the memory buffer, a release basic memory cell buffer may be used to reduce the number of accesses to the memory buffer, and fig. 3 is a schematic diagram of the basic memory cell management circuit 30 according to another embodiment of the present invention. As shown in FIG. 3, the basic memory cell management circuit 30 may include a memory buffer (e.g., SRAM buffer 300; labeled as "SRAM buffer" in FIG. 3 for brevity), a temporary memory buffer 310, an idle basic memory cell controller 320, a receiving circuit 330, a transmitting circuit 340, and a free basic memory cell buffer 350, wherein the basic memory cell management circuit 30 shown in FIG. 3 is different from the basic memory cell management circuit 20 shown in FIG. 2 in that the basic memory cell management circuit 30 may further include a free basic memory cell buffer 350. The free base unit buffer 350 may be coupled to the free base unit controller 320 and the transmission circuit 340, and may be configured to temporarily store at least one base unit corresponding to a transmission packet released by the transmission circuit 340 when the transmission of a transmission packet is completed, wherein the free base unit controller 320 may obtain at least one base unit corresponding to the transmission packet from the free base unit buffer 350 as the free base unit. In this way, when the receiving circuit 330 receives a received packet, the idle basic storage unit controller 320 can read and release at least one basic storage unit corresponding to the transmission packet temporarily stored in the basic storage unit buffer 350 in advance for the received packet, without obtaining the idle basic storage unit through the sram buffer 300 and the buffer 310 (which reduces the access times of the sram buffer 300).
In the present embodiment, the free basic memory cell corresponding to the first bit B10 in the sram buffer 300 (which is buffered in the free basic memory cell buffer 350 with 5 bits of decimal value 10 and marked as "5'd10" in fig. 3), the free basic memory cell corresponding to the first bit B21 (which is buffered in the free basic memory cell buffer 350 with 5 bits of decimal value 21 and marked as "5'd21" in fig. 3), the free basic memory cell corresponding to the first bit B22 (which is buffered in the free basic memory cell buffer 350 with 5 bits of decimal value 22 and marked as "5'd22" in fig. 3), and the free basic memory cell corresponding to the first bit B27 (which is buffered in the free basic memory cell buffer 350 with 5 bits of decimal value 27 and marked as "5'd27" in fig. 3) are buffered in the free basic memory cell buffer 350. It should be noted that when at least one of the basic storage units corresponding to the transmission packet temporarily stored in the free basic storage unit buffer 350 is occupied (i.e., no idle basic storage unit in the free basic storage unit buffer 350), the idle basic storage unit controller 320 may find a target second bit having a first logic value (e.g., 1) from the 4 second bits of the buffer 310 to obtain a read address, and read a target valid idle storage unit indication field in the bit table 301 of the sram buffer 300 according to the read address, and find at least one target first bit having a first logic value (e.g., 1) from the target valid idle storage unit indication field to obtain at least one idle basic storage unit for receiving the packet. In other words, if the free basic storage unit buffer 350 has free basic storage units available, the free basic storage unit controller 320 will read the free basic storage unit buffer 350 preferentially, and if the desired free basic storage units cannot be obtained from the free basic storage unit buffer 350, the free basic storage unit controller 320 will obtain the free basic storage units through the temporary storage buffer 310 and the sram buffer 300.
In the above embodiments, the idle basic storage unit controller 220 (or the idle basic storage unit controller 320) can quickly find the first bit indicating the idle basic storage unit from the bit table of the sram buffer 200 (or the sram buffer 300) by the second bit stored in the buffer 210 (or the buffer 310), however, the buffer may be an optional element, for example, in some embodiments of the present invention, the data management circuit 20 (or the data management circuit 30) may omit the buffer 210 (or the buffer 310) and search the bit table of the sram buffer 200 (or the sram buffer 300) directly to find the first bit indicating the idle basic storage unit. In summary, any data management circuit that uses bits recorded in a bit table to indicate whether the corresponding basic memory cell is an idle basic memory cell falls within the scope of the present invention.
FIG. 4 is a flowchart of a basic storage unit management method according to an embodiment of the invention. If the same result is obtained, the steps are not necessarily performed in sequence completely in accordance with the flow shown in fig. 4, for example, the basic memory cell management method shown in fig. 4 may be implemented by the data management circuit 20 shown in fig. 2 or the data management circuit 30 shown in fig. 3.
In step S400, the sram buffer may store a bit table, where the bit table may include a plurality of first bits corresponding to a plurality of basic memory cells, respectively, and each of the plurality of first bits may be used to indicate whether the corresponding basic memory cell is an idle basic memory cell.
In step S402, an idle basic storage unit controller may be used to manage the bit table, and at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit is processed according to the bit table, wherein the idle basic storage unit controller may set a first bit corresponding to a basic storage unit to a first logic value when the basic storage unit of the plurality of basic storage units is an idle basic storage unit, and the idle basic storage unit controller may set the first bit corresponding to the basic storage unit to a second logic value when the basic storage unit of the plurality of basic storage units is not the idle basic storage unit.
Since the skilled person can easily understand the operations of the steps shown in fig. 4 from the above description, the descriptions of the steps in this embodiment are not repeated here for brevity.
The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.

Claims (10)

1. A basic memory cell management circuit comprising:
a receiving circuit;
a transmission circuit;
a first buffer for storing a bit table, wherein the bit table comprises a plurality of first bits corresponding to a plurality of basic memory cells, respectively, and each of the plurality of first bits is used for indicating whether a corresponding basic memory cell is an idle basic memory cell;
an idle basic storage unit controller coupled to the receiving circuit, the transmitting circuit and the first buffer for managing the bit table stored in the first buffer, and processing at least one basic storage unit corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit as a first logic value; and when the basic storage units of the plurality of basic storage units are not the idle basic storage units, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit as a second logic value.
2. The basic memory cell management circuit of claim 1, wherein the first bits in the bit table are divided into valid idle memory cell indicator fields, and the basic memory cell management circuit further comprises:
a second buffer coupled to the idle basic memory cell controller and configured to store a plurality of second bits corresponding to the plurality of valid idle memory cell indication fields, respectively, wherein each of the plurality of second bits is configured to indicate whether a corresponding valid idle memory cell indication field includes at least one first bit having the first logic value;
when one of the plurality of effective idle memory cell indication fields comprises the at least one first bit with the first logic value, the idle basic memory cell controller sets a second bit corresponding to the effective idle memory cell indication field as one of the first logic value and the second logic value; and when all the first bits contained in the effective idle memory unit marking columns of the effective idle memory unit marking columns have the second logic value, the idle basic memory unit controller sets the second bit corresponding to the effective idle memory unit marking column as the other logic value of the first logic value and the second logic value.
3. The basic storage unit management circuit of claim 2, wherein when the receiving circuit receives a received packet, the idle basic storage unit controller first finds a target second bit with the logic value from the plurality of second bits of the second buffer to obtain a read address, reads a target valid idle storage unit indication field in the bit table of the first buffer according to the read address, and finds at least one target first bit with the first logic value from the target valid idle storage unit indication field to obtain at least one idle basic storage unit.
4. The basic storage unit management circuit of claim 3, wherein the idle basic storage unit controller is further configured to update the at least one target first bit from the first logic value to the second logic value.
5. The basic storage unit management circuit of claim 2, wherein the transmission circuit releases at least one basic storage unit corresponding to a transmission packet to the idle basic storage unit controller when the transmission circuit finishes transmitting the transmission packet.
6. The basic storage unit management circuit of claim 5, wherein the idle basic storage unit controller is further configured to update at least one target first bit in at least one target valid idle storage unit indicator field in the bit table of the first buffer from the second logic value to the first logic value according to the at least one basic storage unit of the transmission packet.
7. The basic memory cell management circuit of claim 2, further comprising:
the buffer is coupled to the transmission circuit and the idle basic storage unit controller, and is used for temporarily storing at least one basic storage unit corresponding to a transmission packet released by the transmission circuit when the transmission circuit finishes transmitting the transmission packet, wherein the idle basic storage unit controller obtains the at least one basic storage unit corresponding to the transmission packet from the buffer as an idle basic storage unit.
8. The basic storage unit management circuit of claim 7, wherein when the receiving circuit receives a received packet, the idle basic storage unit controller reads the at least one basic storage unit corresponding to the transmission packet temporarily stored in the released basic storage unit buffer for the received packet.
9. The basic storage unit management circuit of claim 8, wherein when the at least one basic storage unit corresponding to the transmission packet temporarily stored in the release basic storage unit buffer is occupied, the idle basic storage unit controller finds a target second bit with the logic value from the plurality of second bits of the second buffer to obtain a read address, reads a target valid idle storage unit marking field in the bit table of the first buffer according to the read address, and finds at least one target first bit with the first logic value from the target valid idle storage unit marking field to obtain at least one idle basic storage unit for the reception packet.
10. A basic storage unit management method, comprising:
storing a bit table, wherein the bit table comprises a plurality of first bits corresponding to a plurality of basic memory cells, respectively, and each of the plurality of first bits is used for indicating whether a corresponding basic memory cell is an idle basic memory cell; and
the bit table is managed by using an idle basic storage unit controller, and at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit is processed according to the bit table, wherein when one basic storage unit of the basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit to a first logic value, and when the basic storage unit of the basic storage units is not the idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit to a second logic value.
CN202111412802.XA 2021-11-25 2021-11-25 Basic storage unit management circuit and basic storage unit management method Pending CN116166178A (en)

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