CN116155481A - SM3 algorithm data encryption realization method and device - Google Patents

SM3 algorithm data encryption realization method and device Download PDF

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CN116155481A
CN116155481A CN202310164866.5A CN202310164866A CN116155481A CN 116155481 A CN116155481 A CN 116155481A CN 202310164866 A CN202310164866 A CN 202310164866A CN 116155481 A CN116155481 A CN 116155481A
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state
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杨森
邹望辉
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Changsha University of Science and Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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Abstract

The invention discloses a data encryption realization method and device of SM3 algorithm, the method comprises: filling the plaintext message through a state machine; grouping the filled messages, respectively expanding the filled messages, and outputting message words; and carrying out iterative compression calculation on the message word through parallel optimization of the CSA carry save adder and the CPA carry transfer adder to obtain encrypted data. The device comprises a message filling module, a plurality of groups of expansion and compression modules and a control module, wherein the control module is respectively connected with the message filling module and the expansion and compression modules, and the expansion and compression modules comprise an expansion module and a compression module. The invention solves the problems of larger circuit resource occupancy rate and higher operation power consumption of the existing SM3 algorithm implementation structure.

Description

SM3 algorithm data encryption realization method and device
Technical Field
The invention relates to the technical field of encryption, in particular to a data encryption realization method and device of an SM3 algorithm.
Background
The SM3 algorithm is a hash algorithm of a issued password of a national password administration, is applied to digital signature and verification of commercial passwords, generation and verification of message authentication codes and generation of random numbers, and has security and efficiency equivalent to SHA-256. However, in the current stage, for the hardware structural design of the SM3 algorithm, when performing 64 rounds of function iterative compression, a multi-stage pipeline structure is generally adopted, that is, the iterative compression in the SM3 algorithm is circularly expanded, the output of each round of calculation is used as the input of the next round, the calculation is continued until the current hash value has no rest content to continue to calculate, and the calculated final hash value is output. However, when the hardware is implemented, the hardware is often unsuitable for an application scenario with low power consumption because the hardware needs to occupy larger circuit resources and has higher running power consumption, and the applicability is lower.
Disclosure of Invention
First, the technical problem to be solved
Based on the problems, the invention provides a data encryption realization method and device of an SM3 algorithm, which solve the problems of larger circuit resource occupancy rate and higher operation power consumption of the conventional SM3 algorithm realization structure.
(II) technical scheme
Based on the technical problems, the invention provides a data encryption implementation method of SM3 algorithm, comprising the following steps:
s1, filling a plaintext message through a state machine;
s2, grouping the filled messages, respectively expanding the messages, and outputting message words;
s3, performing iterative compression calculation on the message word through parallel optimization of the CSA carry save adder and the CPA carry transfer adder to obtain encrypted data.
In step S3, the CSA carry save adder and the CPA carry propagate adder set in a critical path are used to perform iterative compression computation on the message word, where the critical path is a computation path with the largest operand in the iterative compression computation.
Further, the critical path is a calculation path of the word registers E and a where the intermediate variables SS1, SS2, TT1, TT2 are located in the iterative compression function.
Further, in step S3, the iterative compression calculation performed on the message word is optimized in parallel by using three CSAs and two CPAs.
Further, the first CSA calculates SS1 and the second CSA calculates GG j (E,F,G)+H+W j The third CSA calculates FF j (A,B,C)+D+W j ′ Three CSAs are calculated in parallel, then the first CPA calculates TT2 according to the calculation result of the first CSA and the second CSA, and the second CPA calculates TT2 according to the calculation result of the second CSACalculating TT1 by the SS2 obtained by the exclusive OR operation of the calculation result of the first CSA and the calculation result of the third CSA, performing parallel calculation by two CPAs, and completing the iterative compression calculation according to the calculation results of the two CPAs, wherein A, B, C, D, E, F, G, H is 8 word registers and GG j And FF (FF) j Representing a Boolean function, taking different expressions as j varies, W j And W is j ′ Representing the message word. Further, in step S1, the state machine includes 8 states: idle, normal message, last word, add 1, add 0, fill high, fill low and complete state, the state jump method of the state machine comprises:
entering an idle state after reset or power-up;
when in an idle state, entering a last word state after receiving the message valid signal and the last word signal, and entering a message normal state after only receiving the message valid signal;
when the message is in a normal state, if a message valid signal and a last word signal are received, entering a last word state;
when the last word state is the last word state, if the counter cnt=13, namely the rest filling area is just 64 bits, the state is jumped to the filling high-order state, otherwise, the state is jumped to the 1-adding state automatically;
when the state of adding 1 is added, after the bit 1 is added to the end of the message, the state of adding 0 is automatically jumped;
when the state of 0 is added, k '0's are added to the tail end of the message, and then the message automatically jumps to a filling high-order state; k is the smallest non-negative integer satisfying l+1+k≡448mod512, l (l)<2 64 ) A bit length for the plaintext message;
filling the high-order state, namely filling the high-order 32 bits representing the binary representation of the message length, and automatically jumping to the filling low-order state after filling is completed;
filling low-order state, filling low-order 32 bits representing binary representation of message length, and automatically jumping to a completion state after filling is completed;
when the state is completed, a filling completion signal is set to 1, and then the state automatically jumps to an idle state.
Further, the steps S2 and S3 are executed in parallel by a plurality of expansion and compression modules.
The invention also discloses a data encryption realization device of the SM3 algorithm, which comprises a message filling module, a plurality of groups of expansion and compression modules and a control module, wherein the control module is respectively connected with the message filling module and the expansion and compression module, and the expansion and compression module comprises an expansion module and a compression module;
the message filling module runs a step S1 in the data encryption realization method of the SM3 algorithm;
s2 in the data encryption implementation method of the SM3 algorithm operated by the expansion module;
and the compression module runs a step S3 in the data encryption implementation method of the SM3 algorithm.
Further, the system also comprises a data caching module, wherein the data caching module is respectively connected with the plurality of groups of expansion and compression modules.
Further, the expansion and compression modules have 3 groups.
(III) beneficial effects
The technical scheme of the invention has the following advantages:
(1) According to the method, the critical path of iterative operation is optimized in parallel through the CSA and CPA adder, and the addition delay in the process of multiple inputs is reduced through parallel operation, so that the operation power consumption of SM3 is reduced, and the circuit resource occupancy rate is reduced; the addition delay is further reduced by the characteristic that the calculation delay of the CSA and CPA adder is smaller when the input is high, and the operation power consumption is further reduced;
(2) The invention sets a plurality of groups of expansion and compression modules in parallel, so that the running power consumption and occupied circuit resources are obviously smaller than those of the pipeline structural design, and the single encryption speed is improved;
(3) The device integrates the message filling module, and the message filling module is realized by an improved state machine, so that software control is simpler.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:
fig. 1 is a flowchart of an implementation method of SM3 algorithm data encryption according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a jump operation of a state machine according to an embodiment of the present invention;
FIG. 3 is a message stuffing diagram of an embodiment of the present invention;
FIG. 4 is a message extension diagram of an embodiment of the present invention;
FIG. 5 is a schematic diagram of compression logic according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating parallel operation of CSA and CPA adders according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an SM3 algorithm data encryption implementation device according to an embodiment of the present invention.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
An embodiment of the present invention is a data encryption implementation method of SM3 algorithm, as shown in fig. 1, including:
s1, filling a plaintext message through a state machine to obtain a message with the length of a multiple of 512 bits;
the state machine includes 8 states: the idle, message normal, last word, add 1, add 0, fill high, fill low, and complete states, as shown in fig. 2, the 8 states and the skip conditions for each state are as follows:
1. idle state: the idle state is entered after reset/power-up. When the idle state is reached, if the effective msg_valid and last word last_word signals of the message are received, the message is completely input, and the last word state is entered; if only the effective msg_valid signal of the message is received, representing that the message starts to be input, and entering a normal_msg state;
2. normal message, normal_msg state: receiving a message effective msg_valid and a last word last_word signal, representing that all the input of the message is completed, and entering a last word state;
3. the last word, last word state: this state is the last state to receive a clear text message. If the counter cnt=13 at this time, namely when the remaining filling area is just 64 bits, the state machine jumps to the add_length state, otherwise, the state machine automatically jumps to the add_80 state;
4. add 1, add_80 state: this state will add bit "1" to the end of the message. The state machine automatically jumps to the add_00 state thereafter;
5. add 0, add_00 state: this state will add k "0" s to the end of the message. For a length of l (l<2 64 ) The message of bits, k, is the smallest non-negative integer satisfying l+1+k≡448mod 512. Then the state machine jumps to the add_length state;
6. when filling the high-order, add_length state: this state will fill the upper 32 bits of the binary representation representing the message length. Automatically jumping to an add_lenl state after filling is completed;
7. filling the low order, add_lenl state: this state will fill the low 32 bits of the binary representation representing the message length. Automatically jumping to a finish state after filling is completed;
8. finish state: this state represents that the message filling is completed, the filling completion signal is set to 1, and then the state is automatically jumped to the idle state;
that is, the state machine is idle and idle, and enters idle after receiving a reset signal or powering up; when receiving the msg_valid signal, representing that the message starts to be input, the state machine jumps to the normal_msg state; when receiving the msg_valid and last_word signals, the representing message is completely input, and the state machine jumps to the last_word state; then the bit "1" is added to the end of the message and k more "0" s. Filling the high order bits of the bit string representing the message length, filling the position of the bit string representing the message length after the next clock cycle; after filling is finished, the state machine enters a Finish state, a signal of filling completion is sent to the control module, and then the state machine enters an idle state.
The bit "l" is added at the end of the message m by the state machine, k "0" are added again, to satisfy the minimum non-negative integer of l+1+k≡448mod512, and then a 64-bit string is added, which is a binary representation of the length l, as shown in fig. 3, where P 1 Representing a permutation function in the message extension. The bit length of the padded message m' is a multiple of 512.
S2, grouping the filled messages according to the length of 512 bits, respectively expanding the messages through 16-word shift registers, and outputting message words W j And W is j ′；
The filled message m' is numbered according to the length of 512 bits to obtain B (0) B (1) ···B (n-1) N represents the total number of groups of packets, n= (l+1+k)/512.
Through 16-word shift register W 0 ···W 15 Implemented as a buffer that generates 132 message words. Message packet B (i) Message expansion is performed to generate 132 words W 0 、W 1 、···、W 67 、W′ 0 、W′ 1 、···、W′ 63 . The first 16 word shift registers pass message packet B (i) Direct partitioning results, without computation, and then shifting one word to the left once per expansion computation. At the same time, the value of the register is extracted according to the position shown in FIG. 4 to perform logic operation, and the result is taken as W 15 Is a new value of (c). Extracting W 0 As the main wheel W j Is to extract W 0 And W is 4 Exclusive or is carried out to obtain the main wheel W j ' output. Namely:
FOR j＝16 TO 67
Figure BDA0004095681470000071
Figure BDA0004095681470000072
ENDFOR
FOR j＝0 TO 63
Figure BDA0004095681470000081
ENDFOR
s3, performing iterative compression calculation on the message word through parallel optimization of the CSA carry save adder and the CPA carry transfer adder to obtain encrypted data.
The operation efficiency of the compression function is mainly determined by the delay of a critical operation path, and the delay of the critical path is mainly caused by the delay of an addition operation, so that the iterative compression calculation of the message word is optimized in parallel by adopting the CSA carry save adder and the CPA carry transfer adder which are arranged on the critical path, wherein the critical path is the calculation path with the largest calculation amount in the iterative compression calculation and can be divided into SS1, SS2, TT1, TT2 variable generation circuits and GG j 、FF j A Boolean operation function circuit.
The logic design diagram for iterative compression is shown in FIG. 5, in which A, B, C, D, E, F, G, H is 8 word registers or a concatenation of their values, GG j Representing Boolean function, taking different expressions as j changes, FF j Representing Boolean function, taking different expressions along with the change of j, wherein SS1, SS2, TT1 and TT2 are intermediate variables, and P 0 Representing a permutation function in the compression function, < representing a 32-bit round-robin left-shifted bit operation, a 32-bit exclusive-or operation, having the following iterative compression function:
SS1←((A＜＜＜12)+E+(T j ＜＜＜j))＜＜＜7
Figure BDA0004095681470000082
TT1←FF j (A,B,C)+D+SS2+W j ′
TT2←GG j (E,F,G)+H+SS1+W j
D←C
C←B＜＜＜9
B←A
A←TT1
H←G
G←F＜＜＜19
F←E
E←P 0 (TT2)
in this embodiment, among the critical paths, the longest critical path is a portion of the calculation word register E:
SS1←((A＜＜＜12)+E+(T j ＜＜＜j))＜＜＜7
TT2←GG j (E,F,G)+H+SS1+W j
E←P 0 (TT2)
parallelizing computation of SS1 and GG using two CSA structures for the longest critical path j (E,F,G)+H+W j According to the calculation result of the two CSA structures, calculating TT2 by using the CPA structure, and according to P 0 (TT 2) calculate the word register E. In the critical path, except for the longest critical path, the operation of directly generating SS2 is exclusive OR operation, the delay is negligible, so parallel calculation is not performed, but TT1 and TT2 are calculated in parallel, and therefore three CSA structures and two CPA structures are adopted for parallel operation.
The parallel operation process of the three CSA structures and the two CPA structures in this embodiment is shown in fig. 6, and includes: the first CSA structure calculates SS1 and the second CSA structure calculates GG j (E,F,G)+H+W j The third CSA architecture calculates FF j (A,B,C)+D+W j And simultaneously calculating three CSA structures, calculating TT2 according to the calculation results of the first CSA structure and the second CSA structure by the first CPA structure, calculating TT1 according to the calculation results of the SS2 and the third CSA structure obtained by exclusive OR operation of the calculation results of the first CSA structure by the second CPA structure, simultaneously calculating the two CPA structures, and completing operation of the iterative compression function according to the calculation results of the two CPA structures.
By introducing CSA (Carry Save Adder) and CPA (Carry Propagate Adder ) structures, the addition delay at multiple inputs is reduced, and more sequential addition operations are performed in parallel, thereby reducing the delay of single iteration computations. The original 5 addition delays are shortened to 2 addition delays through optimization. The calculation delay of the compression module is further reduced by utilizing the characteristic that the calculation delay of the CSA and CPA adder is smaller than that of a conventional traveling wave adder under the condition of high input.
After all the message packets are processed, the output of the last 512-bit packet is the algorithm hash value.
The SM3 algorithm adopts a message word processing mode of combining message double words, so that the rapid diffusion and confusion of the message in a local range are realized. For a length of l (l<2 64 ) The SM3 hash algorithm generates a hash value with 256 bits after message filling and iterative compression of the bit plaintext message.
The second embodiment of the present invention is a data encryption implementation device of SM3 algorithm, as shown in fig. 7, including a message filling module, a plurality of groups of expansion and compression modules, a control module and a data buffer module, where the control module is respectively connected to the message filling module and the expansion and compression module, and the data buffer module is respectively connected to the expansion and compression modules, and the plurality of groups of expansion and compression modules are the same and include an expansion module and a compression module, and in this embodiment, three groups of expansion and compression modules are adopted.
The message filling module runs step S1 in the first embodiment, and is configured to fill an input message according to the SM3 algorithm, so as to obtain a message with a bit length being a multiple of 512; and the expansion module runs the step S2 in the first embodiment and performs word expansion on the 512bit message after filling the packet, and the compression module runs the step S3 in the first embodiment and performs iterative compression to obtain encrypted data.
The data encryption realizing device of the SM3 algorithm makes the message m packed by the message packing module, groups the message m according to 512 bits, and groups the message m ′ Input to multiple groups of expansion and compression modules for parallel calculation, and the expansion modules in each group output W under the control of the control module j And W is j ′ And (3) carrying out 64 rounds of iterative compression on the corresponding compression modules, and finally storing the data in the data cache module. Since the SM3 algorithm requires 64 rounds of computation in the iterative compression process, the embodimentThe method adopts a three-way expansion compression module and parallel calculation mode, improves the throughput of encryption operation without adding a large amount of resources, reduces time delay, occupies 550 slots as circuit resources, consumes 0.027W, and has less circuit resources and less power consumption compared with the pipeline structural design.
Moreover, the expansion compression module can calculate 3W per clk clock due to three paths of parallel expansion modules and compression modules j And W is j ′ Numerical value of W j And W is j ′ The compressed clock is delivered to the compression module for compression under the control of the control module, and compared with the design scheme adopting a multi-stage pipeline structure and a monopole structure, each clk clock can only calculate 1W j And W is j ′ The numerical value of the method improves the calculation efficiency of message expansion by 3 times, so that the time required by single encryption calculation is shorter.
In summary, the method and the device for implementing the SM3 algorithm data encryption have the following beneficial effects:
(1) According to the method, the critical path of iterative operation is optimized in parallel through the CSA and CPA adder, and the addition delay in the process of multiple inputs is reduced through parallel operation, so that the operation power consumption of SM3 is reduced, and the circuit resource occupancy rate is reduced; the addition delay is further reduced by the characteristic that the calculation delay of the CSA and CPA adder is smaller when the input is high, and the operation power consumption is further reduced;
(2) The invention sets a plurality of groups of expansion and compression modules in parallel, so that the running power consumption and occupied circuit resources are obviously smaller than those of the pipeline structural design, and the single encryption speed is improved;
(3) The device integrates the message filling module, and the message filling module is realized by an improved state machine, so that software control is simpler.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims (10)

1. A method for implementing data encryption of SM3 algorithm, comprising:
s1, filling a plaintext message through a state machine;
s2, grouping the filled messages, respectively expanding the messages, and outputting message words;
s3, performing iterative compression calculation on the message word through parallel optimization of the CSA carry save adder and the CPA carry transfer adder to obtain encrypted data.
2. The method for implementing the SM3 algorithm according to claim 1, wherein in step S3, the CSA carry save adder and the CPA carry propagate adder set in a critical path are used to perform iterative compression calculation on the message word, where the critical path is a calculation path with the largest operand in the iterative compression calculation.
3. The method for implementing data encryption of SM3 algorithm according to claim 2, wherein the critical path is a calculation path of the word registers E and a where the intermediate variables SS1, SS2, TT1, TT2 are located in the iterative compression function.
4. A method for implementing data encryption of SM3 algorithm according to claim 3, characterized in that in step S3, the iterative compression calculation of the message word is optimized by three CSAs and two CPAs in parallel.
5. The method of claim 4, wherein the first CSA calculates SS1 and the second CSA calculates GG j (E,F,G)+H+W j The third CSA calculates FF j (A,B,C)+D+W j ′ Three CSAs are calculated in parallel, then a first CPA calculates TT2 according to the calculation results of the first CSA and a second CSA, and a second CPA rootCalculating TT1 according to the SS2 obtained by the exclusive OR operation of the calculation result of the first CSA and the calculation result of the third CSA, performing parallel calculation on the two CPAs, and completing the iterative compression calculation according to the calculation results of the two CPAs, wherein A, B, C, D, E, F, G, H is an 8-word register, GG j And FF (FF) j Representing a Boolean function, taking different expressions as j varies, W j And W is j ′ Representing the message word.
6. The method for implementing data encryption of SM3 algorithm according to claim 1, wherein in step S1, the state machine comprises 8 states: idle, normal message, last word, add 1, add 0, fill high, fill low and complete state, the state jump method of the state machine comprises:
entering an idle state after reset or power-up;
when in an idle state, entering a last word state after receiving the message valid signal and the last word signal, and entering a message normal state after only receiving the message valid signal;
when the message is in a normal state, if a message valid signal and a last word signal are received, entering a last word state;
when the last word state is the last word state, if the counter cnt=13, namely the rest filling area is just 64 bits, the state is jumped to the filling high-order state, otherwise, the state is jumped to the 1-adding state automatically;
when the state of adding 1 is added, after the bit 1 is added to the end of the message, the state of adding 0 is automatically jumped;
when the state of 0 is added, k '0's are added to the tail end of the message, and then the message automatically jumps to a filling high-order state; k is the smallest non-negative integer satisfying l+1+k≡448mod512, l (l)<2 64 ) A bit length for the plaintext message;
filling the high-order state, namely filling the high-order 32 bits representing the binary representation of the message length, and automatically jumping to the filling low-order state after filling is completed;
filling low-order state, filling low-order 32 bits representing binary representation of message length, and automatically jumping to a completion state after filling is completed;
when the state is completed, a filling completion signal is set to 1, and then the state automatically jumps to an idle state.
7. The method according to claim 1, wherein the steps S2 and S3 are executed in parallel by a plurality of expansion and compression modules.
8. A data encryption implementation device of the SM3 algorithm according to any one of claims 1 to 7, comprising a message filling module, a plurality of groups of expansion and compression modules and a control module, wherein the control module is respectively connected with the message filling module and the expansion and compression module, and the expansion and compression module comprises an expansion module and a compression module;
step S1 in a data encryption implementation method of the SM3 algorithm as claimed in any one of claims 1-7 is run by the message stuffing module;
step S2 in the data encryption implementation method of the SM3 algorithm of any one of claims 1-7;
the compression module runs step S3 in the data encryption implementation method of the SM3 algorithm as claimed in any one of claims 1 to 7.
9. The apparatus for implementing data encryption of SM3 algorithm according to claim 8, further comprising a data buffer module, wherein the data buffer modules are respectively connected to the plurality of sets of expansion and compression modules.
10. The SM3 algorithm data encryption realization device of claim 9, wherein the expansion and compression module has 3 groups.
CN202310164866.5A 2023-02-24 2023-02-24 SM3 algorithm data encryption realization method and device Pending CN116155481A (en)

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