CN116155311A

CN116155311A - Correction circuit and correction method for wireless transceiver

Info

Publication number: CN116155311A
Application number: CN202111376008.4A
Authority: CN
Inventors: 李孟哲; 黄建融
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2023-05-23

Abstract

The invention discloses a correction circuit and a correction method of a wireless transceiver. The correction method comprises the following steps: setting a target gain of the radio frequency circuit according to a first gain set value; receiving a first input signal through a coupling path and the receiving path; measuring a first power of the first input signal; setting the target gain of the radio frequency circuit according to a second gain set value; receiving a second input signal through the coupling path and the receiving path; measuring a second power of the second input signal; calculating a power difference between the first power and the second power; and adjusting at least one of the baseband amplifier and the digital circuit according to the power difference.

Description

Correction circuit and correction method for wireless transceiver

Technical Field

The present invention relates to a wireless transceiver, and more particularly, to a calibration circuit and a calibration method for a wireless transceiver.

Background

The transmitting end of the wireless transceiver has a need to linearly adjust power, and the power setting of the transmitting end corresponds to a combination of gains of multiple circuits (e.g., power amplifier, mixer). However, radio frequency analog circuits are not as accurate as digital circuits. In addition, the offset and circuit board layout differences (impedance variations) may cause the transceiver to not adjust its transmit end to the desired power within the existing power settings during actual operation. Therefore, a correction circuit and a correction method are required to correct the wireless transceiver.

Disclosure of Invention

In view of the shortcomings of the prior art, it is an object of the present invention to provide a calibration circuit and a calibration method for a wireless transceiver to improve the shortcomings of the prior art.

An embodiment of the present invention provides a calibration method of a wireless transceiver including a transmission path and a reception path, the transmission path including a radio frequency circuit and a baseband amplifier, the calibration method including: (A) Setting a target gain of the radio frequency circuit according to a first gain set value; (B) Receiving a first input signal through a coupling path and the receiving path; (C) measuring a first power of the first input signal; (D) Setting the target gain of the radio frequency circuit according to a second gain set value; (E) Receiving a second input signal through the coupling path and the receiving path; (F) measuring a second power of the second input signal; (G) Calculating a power difference between the first power and the second power; and (H) adjusting at least one of the baseband amplifier and the digital circuit according to the power difference.

Another embodiment of the present invention provides a calibration circuit for a wireless transceiver, the wireless transceiver including a transmit path and a receive path, the transmit path including a radio frequency circuit and a baseband amplifier, the calibration circuit configured to perform the steps of: (A) Setting a target gain of the radio frequency circuit according to a first gain set value; (B) Receiving a first input signal through a coupling path and the receiving path; (C) measuring a first power of the first input signal; (D) Setting the target gain of the radio frequency circuit according to a second gain set value; (E) Receiving a second input signal through the coupling path and the receiving path; (F) measuring a second power of the second input signal; (G) Calculating a power difference between the first power and the second power; and (H) adjusting at least one of the baseband amplifier and the digital circuit according to the power difference.

The correction circuit and the correction method of the wireless transceiver can correct the transmitting power of the wireless transceiver so as to overcome the power error caused by the difference between the manufacturing offset and the circuit board layout.

The features, practice and efficacy of the present invention are described in detail below with reference to the examples of the invention described in the accompanying drawings.

Drawings

FIG. 1 is a functional block diagram of a wireless transceiver and calibration circuit according to an embodiment of the present invention;

FIG. 2 is a flow chart of an embodiment of a calibration method of a wireless transceiver of the present invention; and

fig. 3 is an example of a first gain setting and a second gain setting in multiple iterations of the correction method of the present invention.

Detailed Description

Technical terms in the following description refer to conventional terms in the art, and as such, a part of the terms are described or defined in the specification, and the explanation of the part of the terms is subject to the description or definition in the specification.

The present disclosure includes calibration circuits and calibration methods for wireless transceivers. Since some of the components included in the wireless transceiver of the present invention may be known components alone, the details of the known components will be omitted from the following description without affecting the full disclosure and operability of the device invention. Furthermore, some or all of the flow of the calibration method of the wireless transceiver of the present invention may be in the form of software and/or firmware and may be performed by the calibration circuit of the wireless transceiver of the present invention or an equivalent thereof, without affecting the full disclosure and operability of the method invention, the following description of the method invention will focus on the contents of the steps rather than the hardware.

Fig. 1 is a functional block diagram of a wireless transceiver and a calibration circuit thereof according to the present invention. The digital circuit 100 includes a correction circuit 110 and a storage circuit 120. The wireless transceiver 105 includes a transmit path 130 and a receive path 140. The transmit path 130 couples to antenna 171 and the receive path 140 couples to antenna 172. The wireless transceiver 105 transmits an output signal (e.g., the first output signal TS1 or the second output signal TS2, transmitted via the antenna 171) through the transmission path 130, and receives an input signal (e.g., the first input signal RS1 or the second input signal RS2, received via the antenna 172 or the attenuator 152) through the reception path 140. The transmission path 130 includes a digital-to-analog converter (DAC) 132, a baseband amplifier 134, and a radio frequency circuit 135, and the radio frequency circuit 135 includes a mixer 136 and a Power Amplifier (PA) 138. In some embodiments, receive path 140 includes analog-to-digital converter (ADC) 142, programmable gain amplifier (programmable gain amplifier, PGA) 144, and mixer 146. In other embodiments, the receive path 140 further includes a low-noise amplifier (LNA) 148. The operation principle and functions of the elements of the wireless transceiver 105 are well known to those skilled in the art, and thus will not be described in detail.

The gain g1 of the baseband amplifier 134, the gain g2 of the mixer 136, and the gain g3 of the power amplifier 138 are adjustable. The digital circuit 100 may adjust or set the gain g1, the gain g2, and the gain g3 by the control signal Ctrl1, the control signal Ctrl2, and the control signal Ctrl3, respectively. The gain g1 of the baseband amplifier 134, the gain g2 of the mixer 136, and the gain g3 of the power amplifier 138 are well known to those skilled in the art, and will not be described in detail. The target gain of the radio frequency circuit 135 is the product of the gain g2 and the gain g3.

The factors of the overall gain of the transmission path 130 include the gain g1, the gain g2, and the gain g3, in other words, the overall gain of the transmission path 130 may be adjusted by adjusting any one of the gain g1, the gain g2, and the gain g3. The digital circuit 100 sets the overall gain of the transmission path 130 according to gain settings (which may be stored in the memory circuit 120), each gain setting corresponding to a target gain of the radio frequency circuit 135 (i.e., corresponding to a combination of gain g2 and gain g 3). The following description assumes that the storage circuit 120 stores 4 gain settings: GA1, GA2, GA3, GA4.

Fig. 2 is a flowchart of an embodiment of a calibration method of a wireless transceiver according to the present invention. The following description refers to fig. 1 and 2.

Step S210: the calibration circuit 110 sets a target gain of the rf circuit 135 according to the first gain set point. When the flow of fig. 2 is performed for the first time, the first gain setting is one of GA1, GA2, GA3, GA4. The frequency response of the first output signal TS1 is related to the first gain set point. In this step, the correction circuit 110 sets the parameters of the mixer 136 by the control signal Ctrl2, and sets the parameters of the power amplifier 138 by the control signal Ctrl 3.

Step S215: the correction circuit 110 receives the first input signal RS1 through the coupling path 150 (or 160) and the receiving path 140. The first output signal TS1 becomes the first input signal RS1 through the coupling path 150 (or 160) and the receive path 140. The coupling path 150 is a wired path within the wireless transceiver 105 and is coupled between the output of the power amplifier 138 and the input of the mixer 146. In other words, the first output signal TS1 is coupled or input to the mixer 146 via the coupling path 150. The coupling path 150 comprises an attenuator 152, the attenuator 152 being arranged to attenuate the first output signal TS1 in order to avoid an excessive power of the signal input to the mixer 146. When the correction circuit 110 receives the first input signal RS1 via the coupling path 150, the correction circuit 110 controls the input terminal of the low noise amplifier 148 to be grounded and/or disables the low noise amplifier 148. Coupling path 160 is a wireless path, i.e., a wireless transmission between antenna 171 and antenna 172.

Step S220: the correction circuit 110 measures a first power P1 of the first input signal RS1. Methods for measuring the power of signals in the digital domain are well known to those skilled in the art and will not be described in detail. The circuit 110 is corrected and records the measured first power P1.

Step S225: the calibration circuit 110 sets the target gain of the rf circuit 135 according to the second gain set point. Step S225 is similar to step S210 in that the second gain setting is not equal to the first gain setting. For example, when the first gain setting is GA1, the second gain setting is GA2. The frequency response of the second output signal TS2 is related to the second gain set point.

Step S230: the correction circuit 110 receives the second input signal RS2 through the coupling path 150 (or the coupling path 160) and the receiving path 140. Step S230 is similar to step S215. The second output signal TS2 becomes the second input signal RS2 via the coupling path 150 (or 160) and the receiving path 140.

Step S235: the correction circuit 110 measures a second power P2 of the second input signal RS2. Step S235 is similar to step S220.

Step S240: the correction circuit 110 calculates a power difference between the first power P1 and the second power P2.

Step S245: the correction circuit 110 determines whether the power difference falls within a target range. More specifically, assuming that the ideal power corresponding to the first gain setting is Pi1 and the ideal power corresponding to the second gain setting is Pi2, the lower limit and the upper limit of the target range may be r1×pi1-Pi2| and r2×pi1-Pi2| (r1 < R2, for example r1=0.8, r2=1.2), respectively. Ideally, the power difference obtained in step S240 should be equal to |Pi1-Pi2|. Therefore, when the power difference |p1-p2| does not fall within the target range (i.e., no in step S245), it represents that the power difference |p1-p2| is too large from the ideal difference |pi1-pi2| (i.e., the power error is too large).

Step S250: the correction circuit 110 adjusts the baseband amplifier 134 and/or the digital circuit 100 based on the power difference. The correction circuit 110 may correct or compensate for the gain of the radio frequency circuit (e.g., correct or compensate for a gain gap between the first gain setting and the second gain setting) in the analog domain (i.e., adjust the gain of the baseband amplifier 134 via the control signal Ctrl 1) and/or in the digital domain (i.e., adjust the gain of the digital circuit 100). In some embodiments, the adjustment of one of the baseband amplifier 134 and the digital circuit 100 may achieve the purpose of correction or compensation. The gain adjustment in the digital domain is well known to those skilled in the art and will not be described in detail.

Step S255: the correction circuit 110 determines whether there is still an unprocessed gain set point. When the result of step S255 is yes, the correction circuit 110 executes step S210 to continue the iteration; when the result of step S255 is no, the correction circuit 110 ends the correction procedure (step S260).

When the correction circuit 110 performs the iteration (i.e., performs steps S210 to S255 again), the correction circuit 110 takes the second gain setting value of the previous iteration as the first gain setting value of the present iteration (e.g., takes GA2 as the first gain setting value as described above), and takes the next gain setting value of the second gain setting value of the previous iteration as the second gain setting value of the present iteration (e.g., takes GA3 as the second gain setting value as described above). For example, when the memory circuit 120 stores 4 gain setting values (GA 1, GA2, GA3, GA 4), the first gain setting value and the second gain setting value for each iteration are shown in fig. 3. When the correction circuit 110 performs step S255 for the second time, since the gain setting value GA4 is not yet processed, the result of step S255 is yes (i.e., a third iteration is required). When the correction circuit 110 performs step S255 for the third time, the result of step S255 is no because there is no unprocessed gain set value already.

As shown in fig. 3, four gain settings (GA 1, GA2, GA3, GA 4) are sequentially processed in total in three iterations. Thus, N iterations sequentially process n+1 gain settings, N being an integer greater than 1. In some embodiments, the sequentially processed gain settings (GA 1, GA2, GA3, …) are arranged in ascending or descending order (i.e., the gains to which the gain settings correspond are arranged sequentially). Thus, when the calibration procedure of fig. 2 is completed, the gain of the rf circuit 135 becomes more linear.

In some embodiments, the multiple gain set points are arranged in a power reduction (i.e., GA1> GA2> GA3 …). In step S250, when the power difference |p1-p2| is smaller than R1 Pi1-Pi2| (representing that P2 is too large), the correction circuit 110 compensates the gain gap by reducing the gain of the baseband amplifier 134 and/or the digital circuit 100; conversely, when the power difference |p1-p2| is greater than r2|p1-p2| (representing that P2 is too small), the correction circuit 110 compensates for the gain gap by increasing the gain of the baseband amplifier 134 and/or the digital circuit 100.

In other embodiments, the multiple gain set points are arranged in raised power (i.e., GA1< GA2< GA3 …). In step S250, when the power difference |p1-p2| is smaller than R1 Pi1-Pi2| (representing P2 is too small), the correction circuit 110 compensates the gain gap by increasing the gain of the baseband amplifier 134 and/or the digital circuit 100; conversely, when the power difference |p1-p2| is greater than r2|p1-p2| (representing that P2 is too large), the correction circuit 110 compensates for the gain gap by reducing the gain of the baseband amplifier 134 and/or the digital circuit 100.

In some embodiments, the correction circuit 110 may be a circuit or electronic element having programming execution capability, such as a central processing unit, microprocessor, microcontroller, micro-processing unit, digital signal processing circuit (digital signal processor, DSP) or equivalent circuit thereof. The correction circuit 110 performs the steps of fig. 2 by executing source code or programming instructions stored in the memory circuit 120. In other embodiments, one of ordinary skill in the art can design the correction circuit 110 based on the above disclosure, that is, the correction circuit 110 can be a Finite State Machine (FSM), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or a circuit or hardware implementation of a programmable logic device (Programmable Logic Device, PLD).

It should be noted that in the disclosed drawings, the shapes, sizes and proportions of the elements are merely illustrative, for the purpose of understanding the present invention by those of ordinary skill in the art, and are not intended to limit the present invention. Furthermore, in some embodiments, the steps mentioned in the disclosed flowcharts may be adjusted in order according to actual operations, and may even be performed simultaneously or partially simultaneously.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and those skilled in the art can make various changes and modifications to the features of the present invention according to the present invention, and the scope of the present invention is defined by the claims of the present invention.

Reference numerals

105 wireless transceiver

100 digital circuit

110 correction circuit

120 memory circuit

130 transport path

132 digital-to-analog converter

134 baseband amplifier

135 radio frequency circuit

136,146 mixer

138 Power Amplifier

140 receive path

142 analog to digital converter

144 programmable gain amplifier

148 low noise amplifier

150,160 coupling paths

152 attenuator

171,172 antenna

Ctrl1, ctrl2, ctrl3 control signal

TS1 first output signal

TS2 second output signal

RS1 first input signal

RS2 second input signal

S210, S215, S220, S225, S230, S235, S240, S245, S250, S255, S260, step

Claims

1. A method of calibrating a wireless transceiver, the wireless transceiver comprising a transmit path and a receive path, the transmit path comprising radio frequency circuitry and a baseband amplifier, the method comprising:

(A) Setting a target gain of the radio frequency circuit according to a first gain set value;

(B) Receiving a first input signal through a coupling path and the receiving path;

(C) Measuring a first power of the first input signal;

(D) Setting the target gain of the radio frequency circuit according to a second gain set value;

(E) Receiving a second input signal through the coupling path and the receiving path;

(F) Measuring a second power of the second input signal;

(G) Calculating a power difference between the first power and the second power; and

(H) At least one of the baseband amplifier and the digital circuit is adjusted according to the power difference.

2. The correction method of claim 1, further comprising:

performing steps (A) to (H) for the second time;

wherein the first gain setting of step (a) in the second execution is the second gain setting of step (D) in the previous execution.

3. The correction method as claimed in claim 2, wherein steps (a) to (H) are performed N times, n+1 gain setting values are sequentially processed, N is an integer greater than 1, and the gains corresponding to the n+1 gain setting values are sequentially arranged in ascending or descending order.

4. The correction method of claim 1, wherein the coupling path is coupled between the transmit path and the receive path and includes an attenuator.

5. The calibration method of claim 1, wherein the transmit path couples a first antenna and the receive path couples a second antenna, the coupling path being a wireless transmission between the first antenna and the second antenna.

6. A calibration circuit for a wireless transceiver, the wireless transceiver comprising a transmit path and a receive path, the transmit path comprising a radio frequency circuit and a baseband amplifier, the calibration circuit to perform the steps of:

(C) Measuring a first power of the first input signal;

(F) Measuring a second power of the second input signal;

7. The correction circuit of claim 6, further performing the steps of:

performing steps (A) to (H) for the second time;

8. The correction circuit of claim 7, wherein steps (a) through (H) are performed N times, n+1 gain setting values are processed in sequence, N is an integer greater than 1, and the gains corresponding to the n+1 gain setting values are arranged in ascending or descending order.

9. The correction circuit of claim 6, wherein the coupling path is coupled between the transmit path and the receive path and includes an attenuator.

10. The correction circuit of claim 6, wherein the transmit path couples a first antenna and the receive path couples a second antenna, the coupling path being a wireless transmission between the first antenna and the second antenna.