CN116155205A - Frequency doubling circuit - Google Patents

Frequency doubling circuit Download PDF

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Publication number
CN116155205A
CN116155205A CN202111407982.2A CN202111407982A CN116155205A CN 116155205 A CN116155205 A CN 116155205A CN 202111407982 A CN202111407982 A CN 202111407982A CN 116155205 A CN116155205 A CN 116155205A
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clock
delay
module
output
duty ratio
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刘敬波
胡江鸣
刘俊秀
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Arkmicro Technologies Inc
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Arkmicro Technologies Inc
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Priority to CN202111407982.2A priority Critical patent/CN116155205A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention provides a frequency multiplication circuit for a DDR2/3 clock system, which comprises: the first delay clock unit module, the first frequency multiplication clock output module and the first automatic duty ratio control module; the first delay clock unit module is used for configuring the delay time of the input clock to generate a delay interval for fixing the output clock and the input clock of the first delay clock unit module; the first frequency doubling clock output module is used for outputting frequency doubling of the input clock of the first time delay clock unit module; the first automatic duty ratio control module adjusts the delay interval of the first delay clock unit module by monitoring the change of the output clock duty ratio of the first frequency multiplication clock output module, so that the output duty ratio of the first frequency multiplication clock output module is kept unchanged. The frequency doubling circuit has simple structure, low system complexity, low cost and wide application range.

Description

Frequency doubling circuit
Technical Field
The invention relates to the technical field of frequency doubling circuits, in particular to a frequency doubling circuit for a DDR2/3 clock system.
Background
The existing frequency doubling circuit generally adopts a phase-locked loop, comprises a frequency and phase discriminator, a charge pump, a voltage-controlled oscillator, a frequency divider and other circuits, and establishes a frequency doubling clock through closed-loop negative feedback. The frequency doubling circuit adopting the phase-locked loop has large area, high cost and poor loop stability.
How to provide a frequency multiplication circuit with low cost, small area and stable performance is a current urgent problem to be solved.
Disclosure of Invention
In view of the above, the present invention provides a frequency multiplier circuit, which aims to solve the deficiencies of the prior art.
The embodiment of the application provides a frequency multiplication circuit, which comprises: the first delay clock unit module, the first frequency multiplication clock output module and the first automatic duty ratio control module;
the first delay clock unit module is used for configuring the delay time of the input clock to generate a delay interval for fixing the output clock and the input clock of the first delay clock unit module; the first frequency doubling clock output module is used for outputting frequency doubling of the input clock of the first time delay clock unit module; the first automatic duty ratio control module adjusts the delay interval of the first delay clock unit module by monitoring the change of the output clock duty ratio of the first frequency multiplication clock output module, so that the output duty ratio of the first frequency multiplication clock output module is kept unchanged.
Further, the method further comprises the following steps: the second delay clock unit module, the second frequency multiplication clock output module and the second automatic duty ratio control module;
the second delay clock unit module is used for configuring the delay time of the input clock to generate a delay interval for fixing the output clock and the input clock of the second delay clock unit module; the second frequency multiplication clock output module is used for outputting four times of the frequency of the input clock of the first time delay clock unit module; the second automatic duty ratio control module adjusts the delay interval of the second delay clock unit module by monitoring the change of the output clock duty ratio of the second frequency multiplication clock output module, so that the output duty ratio of the second frequency multiplication clock output module is kept unchanged.
Further, the first delay clock unit module adopts a structure of two-stage adjustment of thickness, wherein: the coarse adjustment is determined by the clock period of the input clock of the first delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the first automatic duty ratio control module; the second delay clock unit module adopts a structure of two-stage adjustment of thickness, wherein: the coarse adjustment is determined by the clock period of the input clock of the second delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the second automatic duty ratio control module.
Further, the delay interval of the coarse adjustment of the second delay clock unit module is 1/2 of the delay interval of the coarse adjustment of the first delay clock unit module.
Further, the coarse adjustment structures of the first delay clock unit module and the second delay clock unit module are composed of N delays with the same delay parameters and N selectors with the same specification.
Further, the output ends and the input ends of the N delayers are sequentially connected in series end to end; the output ends of the N selectors are sequentially connected with the second input port in series; the output end of each delay device is also connected with a first input port of a corresponding selector; the delay intervals of different magnitudes are output by controlling the selection switch of the selector.
Further, the fine adjustment structures of the first delay clock unit module and the second delay clock unit module are composed of a plurality of inverters with identical delay parameters and a plurality of selectors with identical specifications.
Furthermore, the first frequency multiplication clock output module and the second frequency multiplication clock output module are respectively an exclusive OR gate.
According to the frequency doubling circuit, the frequency doubling clock is generated according to the requirement through the built-in variable delay unit module, different frequency doubling numbers output 50% duty cycle clocks through the automatic duty cycle control module, and the automatic duty cycle module outputs to compensate the delay unit, so that the duty cycle of an output clock signal does not change along with working voltage and temperature. The frequency doubling circuit has simple structure, low system complexity, low cost, and good stability, and can improve the temperature and voltage application range of the system.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a frequency multiplication circuit 2 according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a 2/4 frequency doubling circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a 2/4 frequency doubling circuit according to an embodiment of the present invention;
FIG. 4 is a signal timing diagram of a 2/4 frequency doubling circuit according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a coarse adjustment structure according to an embodiment of the present invention;
fig. 6 is a circuit schematic diagram of a fine adjustment structure according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the present invention provides a 2-frequency multiplication circuit for a DDR2/3 clock system, the circuit comprising: the first delay clock unit module, the first frequency multiplication clock output module and the first automatic duty ratio control module. The first delay clock unit module can configure the input clock delay time module to generate a delay interval for fixing the output clock of the first delay clock unit module and the input clock of the first delay clock unit module. The structure of coarse adjustment and fine adjustment is adopted, wherein the coarse adjustment is determined by the clock period of the input double-frequency clock of the first time delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the first automatic duty ratio control module. The first frequency doubling clock output module is used for outputting the frequency doubling of the input clock of the first time delay clock unit module through the universal logic unit. The general logic unit may be an exclusive or gate. The first automatic duty ratio control module automatically adjusts the fine delay unit of the first delay unit module by monitoring the change of the duty ratio of the output clock of the first frequency multiplication clock output module, so that the output duty ratio of the first frequency multiplication clock output module is kept unchanged.
As shown in fig. 2, 3 and 4, the present invention provides a 2/4 frequency doubling circuit for DDR2/3 clock systems, the circuit comprising: the device comprises a first time delay clock unit module, a first frequency multiplication clock output module, a first automatic duty ratio control module, a second time delay clock unit module, a second frequency multiplication clock output module and a second automatic duty ratio control module.
The first delay clock unit module can configure the input clock delay time module to generate a delay interval for fixing the output clock of the first delay clock unit module and the input clock of the first delay clock unit module. The structure of coarse adjustment and fine adjustment is adopted, wherein the coarse adjustment is determined by the clock period of the input double-frequency clock of the first time delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the first automatic duty ratio control module.
The first frequency doubling clock output module is used for outputting the frequency doubling of the input clock of the first time delay clock unit module through the universal logic unit. The general logic unit may be an exclusive or gate.
The first automatic duty ratio control module automatically adjusts the fine delay unit of the first delay unit module by monitoring the change of the duty ratio of the output clock of the first frequency multiplication clock output module, so that the output duty ratio of the first frequency multiplication clock output module is kept unchanged.
The second delay clock unit module can configure the input clock delay time module to generate a delay interval for fixing the output clock of the second delay clock unit module and the input clock of the second delay clock unit module, and adopts a structure of coarse adjustment and fine adjustment, wherein the coarse adjustment is determined by the frequency of the input clock of the second delay clock unit module, and the fine adjustment is determined by the duty ratio range of the second automatic duty ratio control module. The coarse adjustment delay interval is configured as 1/2 delay of the first delay clock unit, when the coarse delay time of the first delay is increased, the delay time of the second delay is changed by 1/2 coarse delay increasing step length, and when the coarse delay time of the first delay is reduced, the delay time of the second delay is changed by 1/2 coarse delay decreasing step length.
The second frequency multiplication clock output module outputs the frequency multiplication of the input clock of the first time delay clock unit module through the universal logic unit. The general logic unit may be an exclusive or gate.
The second automatic duty ratio control module automatically adjusts the fine delay unit of the second delay unit module by monitoring the change of the duty ratio of the output clock of the second frequency multiplication clock output module, so that the output duty ratio of the second stage is kept unchanged.
The coarse adjustment structures of the first delay clock unit module and the second delay clock unit module are composed of N delays with the same delay parameters and N selectors with the same specification.
As shown in fig. 5, a circuit diagram of a delay coarse adjustment structure is shown, and the output ends and the input ends of the 4 delays are sequentially connected in series end to end; the output ends of the 4 selectors are sequentially connected with the second input port in series; the output end of each delay device is also connected with a first input port of a corresponding selector; the delay intervals of different magnitudes are output by controlling the selection switch of the selector. The data of the second input port is output when the selection terminal SEL of the selector is at low level 0, and the data of the first input port is output when the selection terminal SEL of the selector is at high level 1. When SEL [3:0] =0001, the output delay of the signal after passing through the 1 st delay device and the 1 st selector is t, when SEL [3:0] =0010, the output delay of the signal after passing through the 1 st and 2 nd delay devices and the 1 st and 2 nd selectors is 2t, and so on.
The fine adjustment structures of the first delay clock unit module and the second delay clock unit module are composed of a plurality of inverters with identical delay parameters and a plurality of selectors with identical specifications.
As shown in fig. 6, a circuit diagram of a delay fine adjustment structure is shown, and the output ends and the input ends of 8 inverters are sequentially connected in series end to end; the input end IN and the output end IN4 of the 4 th inverter are respectively connected with a first input port and a second input port of the first selector; the output end IN4 of the 4 th inverter and the output end IN8 of the 8 th inverter are respectively connected with the first input port and the second input port of the second selector, and the first input ports of the third selector, the fourth selector and the fifth selector are connected with the output port of the first selector; the second input ports of the third selector, the fourth selector and the fifth selector are connected with the output port of the second selector; the selection terminals SEL of the 5 selectors select the first input port output when they are at low level 0, and select the second input port output when they are at high level 1. The output end of the selector and the second input port are sequentially connected in series; the output end of each delay device is also connected with a first input port of a corresponding selector; the delay intervals of different magnitudes are output by controlling the selection switch of the selector. The data of the second input port is output when the selection terminal SEL of the selector is at low level 0, and the data of the first input port is output when the selection terminal SEL of the selector is at high level 1. When the selection bits SEL [3:0] =000, the outputs of the third selector, the fourth selector and the fifth selector are IN, IN order; when the selection bits SEL [3:0] =001, the outputs of the third selector, the fourth selector and the fifth selector are IN4, IN sequence; when the selection bits SEL [3:0] =010, the outputs of the third selector, the fourth selector and the fifth selector are IN, IN4 IN sequence; when the selection bits SEL [3:0] =011, the outputs of the third, fourth and fifth selectors are IN4, IN4 IN sequence; when the selection bits SEL [3:0] =101, the outputs of the third selector, the fourth selector, and the fifth selector are IN8, IN4 IN order; when the selection bits SEL [3:0] =110, the outputs of the third selector, the fourth selector and the fifth selector are IN4, IN8 IN sequence; when the selection bits SEL [3:0] =111, the outputs of the third, fourth and fifth selectors are IN8, IN8 IN sequence. Accurate adjustment of the delay is achieved by the above plurality of inverters and selectors.
The invention adopts a mode of configuring the delay interval of the delay clock unit module, outputs 2/4 frequency multiplication signals through the frequency multiplication clock output module, outputs frequency multiplication clock signals irrelevant to temperature and power supply voltage after compensating the duty ratio through the automatic duty ratio control module, and realizes the 2/4 frequency multiplication function. The frequency doubling circuit is applied to the DDR or DDR2/3 clock system, the duty ratio of the output 2 and 4 frequency doubling frequencies can be ensured to be 50% accurately, the complexity of the system is reduced, the cost is reduced, and the temperature and voltage application range of the system is improved.
The detailed operation of the frequency doubling circuit for DDR2/3 clock system is described as follows: after initial power-on is stabilized, DDR2/3 clock signals are input, the coarse adjustment delay interval of the first control delay clock unit module is selected according to the frequency of the input clock, the second control delay clock unit module is configured to be 1/2 of the coarse delay interval of the first control delay clock unit module, a needed 2-frequency multiplication clock is generated through the first frequency multiplication clock output module, after the clock is input into the first automatic duty ratio control module, the first automatic duty ratio control module monitors the duty ratio of the clock, a control signal is output to the first delay clock unit module, the first delay unit module adjusts the fine delay time, the duty ratio of the output clock is changed, and the first frequency multiplication clock output module outputs the 2-frequency multiplication clock with the duty ratio of 50%. The coarse adjustment delay interval of the second control delay clock unit module is automatically configured to be 1/2 of the coarse delay interval of the first control delay clock unit module, a needed 4-frequency-multiplication clock is generated through the second frequency-multiplication clock output module, after the clock is input into the second automatic duty ratio control module, the duty ratio of the four-frequency-multiplication clock is monitored through the second automatic duty ratio control module, a control signal is output to the second delay clock unit module, the fine delay time is adjusted through the second delay clock unit module, the duty ratio of the output four-frequency-multiplication clock is changed, and the second frequency-multiplication clock output module outputs the 4-frequency-multiplication clock with the duty ratio of 50%. According to the circuit, 2/4 frequency multiplication signals and clock signals with the duty ratio of about 50% are generated according to different input clock rates of DDR, and the circuit is used for a DDR2/3 clock system. Detailed description of specific implementation: FIG. 2 is a block diagram showing the steps of inputting DDR2/3 clock signals through a first delay clock unit module, generating time sequence signals required by a first frequency doubling clock output module, outputting required frequency doubling clocks through the first frequency doubling clock output module, inputting the time sequence signals to a first automatic duty ratio control module, automatically monitoring the change of the duty ratio of the clocks output by the first frequency doubling clock output module caused by the change of the power voltage and the temperature by the first automatic duty ratio control module, and automatically adjusting the fine delay time sequence of the first delay clock unit module to enable the first frequency doubling clock output module to output a 2 frequency doubling system clock irrelevant to the power voltage and the temperature. The first frequency doubling clock output module outputs a 2 frequency doubling system clock which is irrelevant to the power voltage and the temperature, the second time delay clock unit module generates a time sequence signal required by the second frequency doubling clock output module, the second frequency doubling clock output module outputs a required 4 frequency doubling clock, the time sequence signal is input to the second automatic duty ratio control module, the second automatic duty ratio control module automatically monitors the change of the duty ratio of the clock output by the second frequency doubling clock output module caused by the change of the power voltage and the temperature, and the second time delay clock unit module fine time delay time sequence is automatically adjusted, so that the second frequency doubling clock output module outputs the 4 frequency doubling system clock which is irrelevant to the power voltage and the temperature. The system needs 2/4 frequency multiplication clock, the first delay clock unit module coarse adjustment delay unit is configured to be 0.625ns, the second delay clock unit module coarse adjustment delay unit is configured to be 1/2 of the first delay unit coarse adjustment delay time, and the delay time is 0.3125ns. The input clock signal generates a 2-frequency multiplication time sequence signal through a first time delay clock unit module, the 800MHz clock signal is output through a first frequency multiplication clock output module, the duty ratio of the 800MHz clock is detected and output through a first automatic duty ratio control module, whether the duty ratio of the output clock is 50% or not is judged, if the duty ratio is larger or smaller, the time delay clock unit module is automatically adjusted, the fine adjustment time delay output clock time sequence of the fine adjustment first time delay clock unit module is controlled through the first automatic duty ratio control module, and the first frequency multiplication clock output module outputs the clock signal with the duty ratio of about 50%. The output 2 multiplied signal of the first multiplied output module enters the second delay clock unit module, and the coarse adjustment delay unit of the second delay clock unit module is configured to be 1/2 of the coarse adjustment delay time of the first delay unit, which is 0.3125ns. The input 2 frequency multiplication 800MHz clock signal generates a 2 frequency multiplication time sequence signal through a second time delay clock unit module, a 1600MHz clock signal is output through a second frequency multiplication clock output module, the duty ratio of the 1600MHz clock is detected and output through a second automatic duty ratio control module, whether the duty ratio of the output clock is 50% or not is judged, if the duty ratio is bigger or smaller, the second time delay clock unit module is automatically adjusted, the fine adjustment time delay output clock time sequence of the second time delay clock unit module is controlled and finely adjusted through the second automatic duty ratio control module, and the 1600MHz clock signal with the duty ratio of about 50% is output by the second frequency multiplication clock output module. And the system is used for a frequency doubling clock, a frequency doubling clock and a frequency quadrupling clock required by DDR 2/3. The input 400MHZ signal outputs a clock signal with a duty cycle of 50% at 800MHZ and 1600 MHZ.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. A frequency multiplier circuit, comprising: the first delay clock unit module, the first frequency multiplication clock output module and the first automatic duty ratio control module;
the first delay clock unit module is used for configuring the delay time of the input clock to generate a delay interval for fixing the output clock and the input clock of the first delay clock unit module; the first frequency doubling clock output module is used for outputting frequency doubling of the input clock of the first time delay clock unit module; the first automatic duty ratio control module adjusts the delay interval of the first delay clock unit module by monitoring the change of the output clock duty ratio of the first frequency multiplication clock output module, so that the output duty ratio of the first frequency multiplication clock output module is kept unchanged.
2. The frequency doubling circuit of claim 1, further comprising: the second delay clock unit module, the second frequency multiplication clock output module and the second automatic duty ratio control module;
the second delay clock unit module is used for configuring the delay time of the input clock to generate a delay interval for fixing the output clock and the input clock of the second delay clock unit module; the second frequency multiplication clock output module is used for outputting four times of the frequency of the input clock of the first time delay clock unit module; the second automatic duty ratio control module adjusts the delay interval of the second delay clock unit module by monitoring the change of the output clock duty ratio of the second frequency multiplication clock output module, so that the output duty ratio of the second frequency multiplication clock output module is kept unchanged.
3. The frequency doubling circuit of claim 1, wherein the first delay clock unit module adopts a structure of two-stage adjustment of thickness, wherein: the coarse adjustment is determined by the clock period of the input clock of the first delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the first automatic duty ratio control module.
4. The frequency doubling circuit of claim 2, wherein the second delay clock unit module adopts a structure of two-stage adjustment of thickness, wherein: the coarse adjustment is determined by the clock period of the input clock of the second delay clock unit module, and the fine adjustment is determined by the duty ratio range controlled by the second automatic duty ratio control module.
5. The frequency doubling circuit of claim 4, wherein the coarsely adjusted delay interval of the second delay clock unit module is 1/2 of the coarsely adjusted delay interval of the first delay clock unit module.
6. The frequency multiplier circuit of claim 4, wherein the coarse adjustment structures of the first and second delay clock unit modules are each comprised of N delays of the same delay parameter and N selectors of the same specification.
7. The frequency multiplier circuit according to claim 5, wherein the output terminals and the input terminals of the N delays are connected in series in sequence; the output ends of the N selectors are sequentially connected with the second input port in series; the output end of each delay device is also connected with a first input port of a corresponding selector; the delay intervals of different magnitudes are output by controlling the selection switch of the selector.
8. The frequency multiplier circuit of claim 4, wherein the fine tuning structures of the first and second delay clock cell modules are each comprised of a plurality of inverters of the same delay parameter and a plurality of selectors of the same specification.
9. The frequency multiplier circuit of claim 1, wherein the first frequency multiplied clock output module is an exclusive or gate.
10. The frequency multiplier circuit of claim 2, wherein the second frequency multiplied clock output module is an exclusive or gate.
CN202111407982.2A 2021-11-19 2021-11-19 Frequency doubling circuit Pending CN116155205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111407982.2A CN116155205A (en) 2021-11-19 2021-11-19 Frequency doubling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111407982.2A CN116155205A (en) 2021-11-19 2021-11-19 Frequency doubling circuit

Publications (1)

Publication Number Publication Date
CN116155205A true CN116155205A (en) 2023-05-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111407982.2A Pending CN116155205A (en) 2021-11-19 2021-11-19 Frequency doubling circuit

Country Status (1)

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CN (1) CN116155205A (en)

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