CN116153353A - Monitoring circuit, statistical method and memory - Google Patents

Monitoring circuit, statistical method and memory Download PDF

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Publication number
CN116153353A
CN116153353A CN202111408608.4A CN202111408608A CN116153353A CN 116153353 A CN116153353 A CN 116153353A CN 202111408608 A CN202111408608 A CN 202111408608A CN 116153353 A CN116153353 A CN 116153353A
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China
Prior art keywords
word line
output
line address
input end
memory cell
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Chinese (zh)
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曹先雷
范习安
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202111408608.4A priority Critical patent/CN116153353A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a monitoring circuit, a statistical method, and a memory, including: a plurality of memory units, a plurality of comparators and a plurality of counters, wherein each memory unit corresponds to one comparator and one counter; the storage judging module is used for receiving the current opened word line address, sequentially comparing whether the word line address stored by the storage unit is identical to the opened word line address or not based on a comparator corresponding to the storage unit of the stored word line address, if the storage unit identical to the opened word line address exists, indicating the count value of a counter corresponding to the storage unit to be increased by one, and if the storage unit identical to the opened word line address does not exist, storing the opened word line address into the storage unit not written with the word line address; and the processing output module is used for outputting the word line address stored in the storage unit corresponding to the counter with the largest numerical value based on the numerical comparison of the counter so as to acquire the word line address with the largest turn-on times.

Description

Monitoring circuit, statistical method and memory
Technical Field
The present disclosure relates to the field of semiconductor circuit design, and more particularly, to a monitoring circuit, a statistical method, and a memory.
Background
The DRAM (Dynamic Random Access Memory, DRAM) stores data by a structure (1T 1C) in which a transistor is connected to a memory cell, wherein the transistor is controlled by a Word Line (WL), and when the WL is turned on, the charge in the memory cell is shared with the charge of a Bit Line (BL) to read data from or write data to the target memory cell.
However, frequent or long turn-on of WL may cause charge loss in adjacent memory cells, possibly causing errors in data stored in the memory cells.
How to count the turn-on times of WL to ensure the accuracy of the data stored in each storage unit is a counting problem to be solved currently.
Disclosure of Invention
Embodiments of the present disclosure provide a monitor circuit to obtain a word line address that is turned on the most frequently.
The disclosed embodiments provide a monitoring circuit, including: each storage unit is used for storing a word line address, and corresponds to a comparator and a counter; the storage judging module is used for receiving the word line address which is started currently and is configured to: based on the comparator corresponding to the memory cell of the stored word line address, comparing whether the word line address stored by the memory cell is the same as the turned-on word line address in sequence, if the memory cell which is the same as the turned-on word line address exists, adding one to the count value of the counter corresponding to the instruction memory cell, and if the memory cell which is the same as the turned-on word line address does not exist, storing the turned-on word line address into the memory cell which is not written with the word line address; a processing output module configured to: based on the numerical comparison of the counters, the word line address stored in the memory cell corresponding to the counter with the largest numerical value is output.
The storage unit is connected with a comparator for comparing whether the word line address which is started at present is stored in the storage unit or not, the word line address which is not stored and started is stored through the storage unit, the storage unit is connected with a counter for counting the word line addresses which are started for many times, namely counting the times of the word line addresses which are started, the word line address with the largest times of being started is output through comparison among the counters, so that the monitoring of the times of starting the word line is realized, and the charge loss in the adjacent storage unit caused by frequent starting of the word line is avoided through optimizing the storage through the obtained word line address.
In some embodiments, each memory cell also has a flag bit; the flag bit comprises a valid flag bit and an invalid flag bit, wherein the valid flag bit is used for representing that the storage unit stores the word line address, and the invalid flag bit is used for representing that the storage unit does not store the word line address; the valid flag bit is also used for turning on the comparator and the counter corresponding to the memory cell. And the comparator connected with the storage unit is started through the flag bit, so that the process of comparing the storage unit which does not store the word line address with the word line address which is started currently through the comparator is saved, and the monitoring process of the word line address starting times is optimized.
In some embodiments, the plurality of storage units are arranged in the form of a linked list.
In some embodiments, the plurality of memory cells are arranged in a queue.
In some embodiments, the storage determination module includes: a receiving unit for receiving the turned-on word line address; the control unit is connected with the receiving unit, the plurality of storage units and comparators corresponding to the storage units; if the memory cell with the same address as the opened word line exists, the control unit instructs the counter corresponding to the memory cell to count one, and if the memory cell with the same address as the opened word line does not exist, the control unit stores the address of the opened word line into the memory cell without writing the address of the word line.
In some embodiments, if there is a memory cell with the same word line address as the turned-on memory cell, the control unit instructs the counter corresponding to the memory cell to count up by one, including: if the memory unit with the same address as the turned-on word line exists, the control unit generates a first control signal and a second control signal; a counter corresponding to a memory cell storing the turned-on word line address counts up by one based on the first control signal; the second control signal is used for indicating that the turned-on word line address is prevented from being stored in the memory cell.
In some embodiments, the processing output module includes: the processing unit is connected with the counters corresponding to the storage units, and is used for comparing the numerical values of the counters and outputting the counter data with the maximum numerical value; and the output unit is connected with the processing unit and the storage units and is used for outputting the word line addresses stored by the corresponding storage units according to the counter data.
In some embodiments, the processing unit includes a plurality of comparison subunits, each comparison subunit including: an output comparator and a multiplexer; the multiplexer is provided with a first input end, a second input end and an output end, wherein the first input end is used for inputting the numerical value of one counter, the second input end is used for inputting the numerical value of the other counter, and the output end is used for outputting the larger value of the numerical value of the first input end and the numerical value of the second input end; an output comparator is connected to the multiplexer and configured to control the output of the multiplexer based on a comparison of the value at the first input and the value at the second input; the plurality of comparison subunits are sequentially connected to output the maximum data in the plurality of counters.
In some embodiments, the multiplexer further comprises a third input, a fourth input, and a character output; the third input end is used for inputting the address of the counter corresponding to the numerical value input by the first input end; the fourth input end is used for inputting the address of the counter corresponding to the numerical value input by the second input end; the character output end is used for outputting the address of the counter corresponding to the numerical value output by the output end. By the address of the counter 103, the word line address stored in the memory cell 101 corresponding to the counter 103 is conveniently queried according to the address of the counter 103.
In some embodiments, the processing unit includes an output comparator, a multiplexer, and a comparison memory; the multiplexer is provided with a first input end, a second input end and an output end, wherein the first input end is used for inputting the numerical value of a counter, the second input end and the output end are connected with the comparison memory, the output end is used for outputting the numerical value of the first input end and the larger numerical value of the second input end, and the comparison memory is used for storing the output value of the output end and inputting the output value to the second input end; the output comparator is connected with the multiplexer and is configured to control the multiplexer to output a larger value of the first input end and the value of the second input end based on a comparison result of the value of the first input end and the value of the second input end; the comparison memory is also used for outputting the stored counter value.
In some embodiments, the multiplexer further comprises a third input, a fourth input, and a character output; the third input end is used for inputting the address of the counter corresponding to the numerical value input by the first input end; the fourth input end and the character output end are connected with a comparison memory, the character output end is used for outputting the address of the counter corresponding to the numerical value output by the output end, the comparison memory is also used for storing the address of the counter, and the address of the counter is input to the fourth input end. By the address of the counter 103, the word line address stored in the memory cell 101 corresponding to the counter 103 is conveniently queried according to the address of the counter 103.
In some embodiments, the output comparator is specifically configured to control the output terminal of the multiplexer to output the value of the first input terminal if the value of the first input terminal is greater than or equal to the value of the second input terminal, and otherwise control the output terminal of the multiplexer to output the value of the second input terminal; or if the value of the first input end is smaller than that of the second input end, controlling the output end of the multiplexer to output the value of the second input end, otherwise, controlling the output end of the multiplexer to output the value of the first input end.
In some embodiments, the monitoring circuit further comprises: the first switch module is connected with the storage judging module and is configured to be conducted, and the storage judging module works. The operation of the monitoring circuit is controlled through the first switch module, so that the resource consumption in the process of no monitoring is avoided.
In some embodiments, the monitoring circuit further comprises: the second switch module is connected with the processing output module and is configured to be conducted, and the processing output module works. And the second light-on module is used for controlling the output of the monitoring circuit, so that the error output of the monitoring circuit is avoided when the counting count of the unfinished word line address is started.
The embodiment of the disclosure also provides a statistical method applied to the monitoring circuit, which comprises the following steps: acquiring a word line address which is currently turned on; judging whether the opened word line address is stored in the memory cell or not, counting a counter corresponding to the memory cell if the opened word line address is stored in the memory cell, and storing the word line address in the memory cell if the opened word line address is not stored in the memory cell; and comparing the counters corresponding to all the memories storing the word line addresses, and acquiring the word line address stored by the memory cell with the largest counter.
The embodiment of the disclosure also provides a memory, which applies the monitoring circuit to protect the word line corresponding to the word line address based on the obtained word line address.
Drawings
Fig. 1 is a schematic structural diagram of a monitoring circuit according to an embodiment of the disclosure;
fig. 2 is a schematic circuit diagram of a specific circuit structure of a monitoring circuit according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a processing unit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a comparing subunit according to an embodiment of the disclosure;
FIG. 5 is a schematic diagram of another configuration of a processing unit according to an embodiment of the disclosure;
fig. 6 is a flow chart of a statistical method according to another embodiment of the disclosure.
Detailed Description
As known from the background art, the WL is turned on frequently or for a long time to cause the charge in the adjacent memory cells to be lost, which may cause errors in the data stored in the memory cells.
The embodiment of the disclosure provides a monitoring circuit to acquire a word line address with the largest turn-on times, and the charge loss in adjacent memory cells caused by frequent turn-on of the word line is avoided by optimizing a memory subsequently through the acquired word line address.
Those of ordinary skill in the art will understand that in various embodiments of the present disclosure, numerous technical details are set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic circuit diagram of a monitoring circuit according to the present embodiment, fig. 2 is a schematic circuit diagram of a specific circuit of the monitoring circuit according to the present embodiment, fig. 3 is a schematic circuit diagram of a processing unit according to the present embodiment, fig. 4 is a schematic circuit diagram of a comparing subunit according to the present embodiment, fig. 5 is a schematic circuit diagram of a processing unit according to the present embodiment, and the monitoring circuit according to the present embodiment is described in further detail below with reference to the accompanying drawings, which are specifically as follows:
referring to fig. 1, a monitoring circuit includes:
the memory comprises a plurality of memory cells 101, a plurality of comparators 102 and a plurality of counters 103, wherein each memory cell 101 is used for storing a word line address, and each memory cell 101 corresponds to one comparator 102 and one counter 103.
In fig. 1, the example of 8 memory cells 101, 8 comparators 102, and 8 counters 103 are specifically described, but the present embodiment is not limited thereto, and in other embodiments, the number of memory cells, comparators, and counters may be set according to the specific scenario of the application.
The storage unit n is correspondingly connected with the comparator n and the counter n, wherein n is a natural number which is more than or equal to 1 and less than or equal to 8; the word line address 1 is stored in the memory cell 1, the word line address 2 is stored in the memory cell 2, the word line address 3 is stored in the memory cell 3, the word line address 4 is stored in the memory cell 4, and the word line addresses are not stored in the memory cells after the memory cell 5, namely, the empty memory cells.
The storage determination module 104 is configured to receive a word line address that is currently turned on, and is configured to: based on the comparator 102 corresponding to the memory cell 101 storing the word line address, sequentially compares whether the word line address stored in the memory cell is identical to the turned-on word line address, if the memory cell 101 having the same word line address as the turned-on word line address exists, the count value of the counter 103 corresponding to the memory cell 101 storing the same word line address is incremented by one, and if the memory cell 101 having the same word line address as the turned-on word line address does not exist, the turned-on word line address is stored in the memory cell 101 having no word line address written therein.
Corresponding to fig. 1, assuming that the memory judgment module 104 receives the opened word line address, the memory cells 101 storing the word line address are the memory cells 1 to 4, and the comparators 1 to 4 corresponding to the memory cells 1 to 4 are respectively compared with the memory judgment module 104, if the comparison values are the same, the opened word line address is proved to be stored in the memory cell 101, and the counter 103 correspondingly connected to the comparator 102 is incremented by one; if the comparison values are not the same, it is verified that the turned-on word line address is not stored in the memory cell 101, and the turned-on word line address is stored in a new memory cell.
The memory cell 101 is connected to a comparator 102 for comparing whether the currently turned on word line address is stored in the memory cell 101, and storing the non-stored turned on word line address through the memory cell 101, and the memory cell 101 is connected to a counter 103 for counting the number of times of the turned on word line address, i.e., counting the number of times of the turned on word line address.
It should be noted that, in one example, the initial values of the counter 103 are all 1, that is, after the memory cell 101 stores data, the counter 103 indicates that the word line address stored in the memory cell 101 is turned on 1 time; in other embodiments, it is only necessary that the initial values of the counters be the same, and the specific initial value may be any value.
A processing output module 105 configured to: based on the numerical comparison of the counter 103, the word line address stored in the memory cell 101 corresponding to the counter 103 having the largest numerical value is output.
The word line addresses with the largest turn-on times are output through the comparison between the counters 103, so that the monitoring of the turn-on times of the word lines is realized, and the charge loss in the adjacent memory cells caused by the frequent turn-on of the word lines is avoided through the obtained word line addresses and the subsequent optimization of the memory.
In this embodiment, the counter 103 counts up in an incremental manner, and then compares the word line address stored in the memory cell 101 corresponding to the counter 103 outputting the largest value, i.e., the word line address with the largest number of turned-on times. In other embodiments, the counter may also count in a decrementing manner, and then compare the word line address stored in the memory cell corresponding to the counter outputting the smallest value, i.e. the word line address with the largest number of turned-on times.
In some embodiments, referring to fig. 2, the storage determination module 104 includes: a receiving unit 114 and a control unit 124; a receiving unit 114 for receiving the turned-on word line address; a control unit 124 connecting the reception unit 114, the plurality of storage units 101, and the comparator 102 corresponding to the storage unit 101; if there is a memory cell 101 with the same word line address as turned on, the control unit 124 instructs the counter 103 corresponding to the memory cell 101 to count up by one, and if there is no memory cell 101 with the same word line address as turned on, the control unit 124 stores the turned on word line address into the memory cell 101 with no word line address written.
Specifically, in one example, if there is a memory cell 101 with the same word line address as turned on, the control unit 124 instructs the counter 103 corresponding to the memory cell 101 to count one more, and if there is no memory cell 101 with the same word line address as turned on, the control unit 124 stores the turned on word line address into the memory cell 101 with no word line address, including:
if there is a memory cell 101 having the same word line address as the turned-on word line address, the control unit 124 generates a first control signal and a second control signal, and the counter 103 corresponding to the memory cell 101 storing the turned-on word line address is incremented by one based on the first control signal, and the second control signal is used for indicating that the turned-on word line address is prevented from being stored in the memory cell 101.
If the comparator 102 corresponding to the memory cell 101 storing the turned-on word line address does not generate the first control signal and the second control signal, it indicates that the word line address currently turned on is not stored in the memory cell 101, and the word line address currently turned on is stored in the memory cell 101.
In some embodiments, the plurality of memory cells 101 are arranged in the form of a linked list, and for fig. 1 and 2, if the linked list is arranged, then if a new word line address needs to be stored, the word line address is directly stored in the memory cell 5.
In some embodiments, the plurality of memory cells 101 employ a queue formation arrangement, for fig. 1 and 2, if a new word line address is required to be stored at this time, the memory cell 4 moves the data down to the memory cell 5, the memory cell 3 moves the data down to the memory cell 4, the memory cell 2 moves the data down to the memory cell 3, the memory cell 1 moves the data down to the memory cell 2, and the new word line address is stored in the memory cell 1; in the process of moving down the data of the storage unit 101, the comparator 102 and the counter 103 corresponding to the storage unit 101 move together with the storage unit 101.
In some embodiments, each memory cell also has a flag bit; the flag bit includes an effective flag bit and an invalid flag bit, the effective flag bit is used for indicating that the memory cell 101 has stored a word line address, the invalid flag bit is used for indicating that the memory cell 101 is storing the word line address, and the effective flag bit is also used for turning on the comparator 102 and the counter 103 corresponding to the memory cell 101. The comparator 102 connected with the memory unit 101 is started by the flag bit, so that the process that the memory unit 101 which does not store the word line address is compared with the word line address which is started currently by the comparator 102 is saved, and the monitoring process of the number of times of starting the word line address is optimized.
It should be noted that, in a specific application, the flag bit may be one bit, or may be a multi-bit flag bit, and the embodiment does not limit the bit number of the flag bit, and accords with the scheme of the setting mode of the flag bit mentioned in the disclosure, which all shall fall within the protection scope of the disclosure.
In some embodiments, referring to fig. 2, the initial output module 105 (referring to fig. 1) includes: a processing unit 115 and an output unit 125; a processing unit 115 connected to the counters 103 corresponding to the plurality of storage units 101, for comparing the values of the plurality of counters 103 and outputting counter data having the largest value; the output unit 125 is connected to the processing unit 115 and the plurality of memory units 101, and is configured to output the word line address stored in the corresponding memory unit 101 according to the counter data.
For the processing unit 115, the embodiments of the present disclosure provide two implementations of the processing unit 115, specifically as follows:
in one example, referring to fig. 3 and 4, the processing unit 115 (referring to fig. 2) includes a plurality of comparison subunits 200, each comparison subunit 200 including: an output comparator 202 and a multiplexer 201.
The multiplexer 201 has a first input terminal for inputting the value of the counter 103, a second input terminal for inputting the value of the other comparator 103, and an output terminal for outputting the larger of the value of the first input terminal and the value of the second input terminal; the output comparator 202 is coupled to the multiplexer and is configured to control the output of the multiplexer based on a comparison of the value at the first output terminal and the value at the second input terminal.
The output comparator 202 is specifically configured to control the output terminal of the multiplexer 201 to output the value of the first input terminal if the value of the first input terminal is greater than or equal to the value of the second input terminal, otherwise control the multiplexer 201 to output the value of the second input terminal, or control the output terminal of the multiplexer 201 to output the value of the second input terminal if the value of the first output terminal is less than the value of the second output terminal, otherwise control the value of the first input terminal of the output port of the multiplexer 201.
The comparing sub-units 200 are sequentially connected to output the maximum data in the counters 103. Referring to fig. 3, the outputs of the plurality of comparing sub-units 200 are compared by one comparing sub-unit 200 to perform a comparison output.
It should be noted that the number of comparison subunits 200 shown in fig. 3 is merely illustrative, and not limiting in the present embodiment, and in a specific application, the number of comparison subunits 200 is set according to the number of comparators 103.
Further, referring to fig. 4, the multiplexer 201 further includes a third input terminal, a fourth input terminal, and a character output terminal; the third input terminal is used for inputting the address of the counter 103 corresponding to the numerical value input by the first input terminal, the fourth input terminal is used for inputting the address of the counter 103 corresponding to the numerical value input by the second input terminal, and the character output terminal is used for outputting the address of the counter 103 corresponding to the numerical value output by the output terminal. By the address of the counter 103, the word line address stored in the memory cell 101 corresponding to the counter 103 is conveniently queried according to the address of the counter 103.
In one example, referring to fig. 5, the processing unit 115 (referring to fig. 2) includes an output comparator 302, a multiplexer 301, and a comparison memory 303.
The multiplexer 301 has a first input terminal, a second input terminal and an output terminal, the first input terminal is used for inputting a value of the counter 103, the second input terminal and the output terminal are connected with the comparison memory 303, the output terminal is used for outputting a larger value of the first input terminal and the value of the second input terminal, the comparison memory is used for storing an output value of the output terminal, and the output value is input to the second input terminal; the output comparator 302 is connected to the multiplexer 301 and is configured to control the multiplexer to output a larger value of the first input and the value of the second input based on a comparison result of the value of the first input and the value of the second input.
The output comparator 302 is specifically configured to control the output terminal of the multiplexer 301 to output the value of the first input terminal if the value of the first input terminal is greater than or equal to the value of the second input terminal, otherwise control the multiplexer 301 to output the value of the second input terminal, or control the output terminal of the multiplexer 301 to output the value of the second input terminal if the value of the first output terminal is less than the value of the second output terminal, otherwise control the value of the first input terminal of the output port of the multiplexer 301.
The comparison memory 303 is also used to output the stored value of the counter 103. Referring to fig. 5, a larger counter value after each comparison is stored in the comparison memory 303, and the value in the comparator memory 303 is compared with the new counter 103 value, and the maximum data in the plurality of comparators 103 is acquired after a plurality of cycles.
Further, referring to fig. 5, the multiplexer 301 further includes a third input terminal, a fourth input terminal, and a character output terminal; the third input terminal is used for inputting an address of the counter 103 corresponding to the numerical value input by the first input terminal, the fourth input terminal and the character output terminal are connected with the comparison memory 303, the character output terminal is used for outputting the address of the counter 103 corresponding to the numerical value output by the output section, the comparison memory 303 is also used for storing the address of the counter 103, and the address of the counter is input to the fourth input terminal. By the address of the counter 103, the word line address stored in the memory cell 101 corresponding to the counter 103 is conveniently queried according to the address of the counter 103.
In some embodiments, the monitoring circuit further comprises: the first switch module (not shown) is connected to the storage determination module 104 (refer to fig. 1), and is configured such that the first switch module (not shown) is turned on, and the storage determination module 104 operates. The operation of the monitoring circuit is controlled through the first switch module, so that the resource consumption in the process of no monitoring is avoided.
In some embodiments, the monitoring circuit further comprises: the second switch module (not shown) is connected to the process output module 105 (refer to fig. 2), and is configured such that the second switch module (not shown) is turned on, and the process output module 105 operates. And the second light-on module is used for controlling the output of the monitoring circuit, so that the error output of the monitoring circuit is avoided when the counting count of the unfinished word line address is started.
The memory cell 101 is connected with a comparator 102 for comparing whether the current opened word line address is stored in the memory cell 101 or not, and storing the non-stored opened word line address through the memory cell 101, and the memory cell 101 is connected with a counter 103 for counting the word line addresses opened for a plurality of times, namely counting the times of the opened word line addresses; the word line addresses with the largest turn-on times are output through the comparison between the counters 103, so that the monitoring of the turn-on times of the word lines is realized, and the charge loss in the adjacent memory cells caused by the frequent turn-on of the word lines is avoided through the obtained word line addresses and the subsequent optimization of the memory.
Each unit referred to in this embodiment is a logic unit, and in practical application, one logic unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units. Furthermore, in order to highlight the innovative part of the present disclosure, elements that are not so close to solving the technical problem presented by the present disclosure are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.
It should be noted that the features disclosed in the monitoring circuit provided in the above embodiments may be arbitrarily combined without collision, and a new circuit embodiment may be obtained.
Another embodiment of the present disclosure provides a statistical method applied to the monitoring circuit provided in the above embodiment, so as to monitor the number of times of word line turn-on, and output the word line address with the largest number of times of turn-on.
Fig. 6 is a flow chart of the statistical method provided in this embodiment, and the statistical method provided in this embodiment is described in further detail below with reference to the accompanying drawings, specifically as follows:
referring to fig. 6, a statistical method includes:
step 401, a word line address that is currently turned on is obtained.
Step 402, processing the acquired word line address.
Specifically, it is determined whether an opened word line address is already stored in the memory cell, if the opened word line address is already stored in the memory cell, the counter corresponding to the memory cell counts, and if the opened word line address is not already stored in the memory cell, the word line is mainly stored in the memory cell.
Corresponding to fig. 1, assuming that the memory judgment module 104 receives the opened word line address, the memory cells 101 storing the word line address are the memory cells 1 to 4, and the comparators 1 to 4 corresponding to the memory cells 1 to 4 are respectively compared with the memory judgment module 104, if the comparison values are the same, the opened word line address is proved to be stored in the memory cell 101, and the counter 103 correspondingly connected to the comparator 102 is incremented by one; if the comparison values are not the same, it is verified that the turned-on word line address is not stored in the memory cell 101, and the turned-on word line address is stored in a new memory cell.
The memory cell 101 is connected to a comparator 102 for comparing whether the currently turned on word line address is stored in the memory cell 101, and storing the non-stored turned on word line address through the memory cell 101, and the memory cell 101 is connected to a counter 103 for counting the number of times of the turned on word line address, i.e., counting the number of times of the turned on word line address.
In step 403, the word line address with the largest turn-on number is compared and obtained.
Specifically, the counter corresponding to the memory storing all the word line addresses is compared, and the word line address stored in the memory cell with the largest counter is obtained.
The word line addresses with the largest turn-on times are output through the comparison between the counters 103, so that the monitoring of the turn-on times of the word lines is realized, and the charge loss in the adjacent memory cells caused by the frequent turn-on of the word lines is avoided through the obtained word line addresses and the subsequent optimization of the memory.
It should be noted that the above description of the statistical method is similar to the description of the embodiment of the monitoring circuit, and has similar beneficial effects as the embodiment of the monitoring circuit, so that a detailed description is omitted. For technical details not disclosed in the statistical method of the embodiments of the present disclosure, please refer to the description of the monitoring circuit in the embodiments of the present disclosure for understanding.
The above-mentioned stage division of each statistical method is only for clarity of description, and can be combined into one statistical stage or split some statistical stages into multiple statistical stages when implemented, so long as the logic of the statistical methods is the same, they are all within the protection scope of this patent; in some embodiments, it is within the scope of this patent to add insignificant modifications or introduce insignificant designs to the above statistical methods, but not to alter the core design of the above statistical methods.
Yet another embodiment of the present disclosure provides a memory, which is applied to the monitoring circuit provided in the foregoing embodiment, and protects a word line corresponding to the word line address based on the obtained word line address. By optimizing the memory through the obtained word line address, the charge loss in the adjacent memory cells caused by the frequent opening of the word line is avoided.
In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR2 memory specifications.
In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR3 memory specifications.
In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR4 memory specifications.
In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR5 memory specifications.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims (16)

1. A monitoring circuit, comprising:
each storage unit is used for storing a word line address, and corresponds to one comparator and one counter;
the storage judging module is used for receiving the word line address which is started currently and is configured to: based on the comparator corresponding to the memory cell of the stored word line address, comparing whether the word line address stored by the memory cell is identical to the turned-on word line address or not in sequence, if the memory cell identical to the turned-on word line address exists, indicating the count value of the counter corresponding to the memory cell to be increased by one, and if the memory cell identical to the turned-on word line address does not exist, storing the turned-on word line address into the memory cell not written with the word line address;
a processing output module configured to: and outputting the word line address stored by the storage unit corresponding to the counter with the largest value based on the value comparison of the counter.
2. The monitoring circuit of claim 1, wherein each of the memory cells further has a flag bit;
the flag bit comprises a valid flag bit and an invalid flag bit, wherein the valid flag bit is used for representing that the storage unit stores word line addresses, and the invalid flag bit is used for representing that the storage unit does not store word line addresses;
the valid flag bit is also used for conducting the comparator and the counter corresponding to the storage unit.
3. The monitoring circuit of claim 1, wherein a plurality of the memory cells are arranged in the form of a linked list.
4. The monitoring circuit of claim 1, wherein a plurality of the memory cells are arranged in a queue.
5. The monitoring circuit of claim 1, wherein the memory determination module comprises:
a receiving unit for receiving the turned-on word line address;
the control unit is connected with the receiving unit, the storage units and the comparators corresponding to the storage units;
and if the memory cell with the same address as the opened word line exists, the control unit indicates the counter corresponding to the memory cell to count one more, and if the memory cell with the same address as the opened word line does not exist, the control unit stores the opened word line address into the memory cell without writing the word line address.
6. The monitor circuit according to claim 5, wherein said control unit instructs said counter corresponding to said memory cell to count up by one if there is a memory cell with the same word line address as said turned on, comprising:
if the memory unit with the same address as the turned-on word line exists, the control unit generates a first control signal and a second control signal;
a counter corresponding to a memory cell storing the turned-on word line address counts up by one based on the first control signal;
the second control signal is used for indicating that the turned-on word line address is prevented from being stored in the memory cell.
7. The monitoring circuit of claim 1, wherein the processing output module comprises:
the processing unit is connected with the counters corresponding to the storage units and is used for comparing the numerical values of the counters and outputting the counter data with the maximum numerical value;
and the output unit is connected with the processing unit and the storage units and is used for outputting the corresponding word line addresses stored by the storage units according to the counter data.
8. The monitoring circuit of claim 7, wherein the processing unit comprises a plurality of comparison subunits, each comprising: an output comparator and a multiplexer;
the multiplexer is provided with a first input end, a second input end and an output end, wherein the first input end is used for inputting the numerical value of one counter, the second input end is used for inputting the numerical value of the other counter, and the output end is used for outputting the larger one of the numerical value of the first input end and the numerical value of the second input end;
the output comparator is connected with the multiplexer and is configured to control the output of the multiplexer based on the comparison of the value of the first input end and the value of the second input end;
the plurality of comparison subunits are sequentially connected to output the maximum data in the plurality of counters.
9. The monitor circuit of claim 8, wherein the multiplexer further comprises a third input, a fourth input, and a character output;
the third input end is used for inputting an address of the counter corresponding to the numerical value input by the first input end;
the fourth input end is used for inputting an address of the counter corresponding to the numerical value input by the second input end;
the character output end is used for outputting the address of the counter corresponding to the numerical value output by the output end.
10. The monitoring circuit of claim 7, wherein the processing unit comprises an output comparator, a multiplexer, and a comparison memory;
the multiplexer having a first input, a second input and an output,
the first input end is used for inputting a numerical value of the counter, the second input end and the output end are connected with the comparison memory, the output end is used for outputting the numerical value of the first input end and a larger numerical value of the second input end, and the comparison memory is used for storing an output value of the output end and inputting the output value to the second input end;
the output comparator is connected with the multiplexer and is configured to control the multiplexer to output larger values of the first input end and the second input end based on a comparison result of the values of the first input end and the values of the second input end;
the comparison memory is also used for outputting the stored numerical value of the counter.
11. The monitor circuit of claim 10, wherein the multiplexer further comprises a third input, a fourth input, and a character output;
the third input end is used for inputting an address of the counter corresponding to the numerical value input by the first input end;
the fourth input end and the character output end are connected with the comparison memory, the character output end is used for outputting an address of the counter corresponding to the numerical value output by the output end, and the comparison memory is also used for storing the address of the counter and inputting the address of the counter to the fourth input end.
12. The monitoring circuit according to any one of claims 8 to 11, wherein the output comparator is specifically configured to,
if the value of the first input end is larger than or equal to the value of the second input end, controlling the output end of the multiplexer to output the value of the first input end, otherwise, controlling the output end of the multiplexer to output the value of the second input end;
or if the value of the first input end is smaller than the value of the second input end, controlling the output end of the multiplexer to output the value of the second input end, otherwise, controlling the output end of the multiplexer to output the value of the first input end.
13. The monitoring circuit of claim 1, further comprising: the first switch module is connected with the storage judging module and is configured to be conducted, and the storage judging module works.
14. The monitoring circuit of claim 1, further comprising: and the second switch module is connected with the processing output module and is configured to be conducted, and the processing output module works.
15. A statistical method applied to the monitoring circuit of any one of claims 1 to 14, comprising:
acquiring a word line address which is currently turned on;
judging whether the opened word line address is stored in a memory cell or not, counting a counter corresponding to the memory cell if the opened word line address is stored in the memory cell, and storing the word line address in the memory cell if the opened word line address is not stored in the memory cell;
and comparing the counters corresponding to the memories of all the stored word line addresses, and acquiring the word line address stored by the memory cell with the largest counter.
16. A memory applied to the monitor circuit according to any one of claims 1 to 14, wherein a word line corresponding to an acquired word line address is protected based on the word line address.
CN202111408608.4A 2021-11-19 2021-11-19 Monitoring circuit, statistical method and memory Pending CN116153353A (en)

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