CN116151162A - Automatic design method, device, equipment and medium for register codes and documents - Google Patents
Automatic design method, device, equipment and medium for register codes and documents Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/80—Information retrieval; Database structures therefor; File system structures therefor of semi-structured data, e.g. markup language structured data such as SGML, XML or HTML
- G06F16/81—Indexing, e.g. XML tags; Data structures therefor; Storage structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/80—Information retrieval; Database structures therefor; File system structures therefor of semi-structured data, e.g. markup language structured data such as SGML, XML or HTML
- G06F16/84—Mapping; Conversion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses an automatic design method, device, equipment and medium for register codes and documents, wherein chip level module parameters and register parameters input by a user are acquired through an interactive webpage, and a preset format file is generated according to the chip level module parameters and the register parameters; analyzing the preset format file to obtain analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode; and analyzing the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface. The method can effectively reduce uncertainty caused by repeated manual development of register codes and documents, ensure continuity and stability of each version of the register codes and documents in a design period, and has the characteristics of high automation degree, high accuracy, high efficiency, good instantaneity, easiness in debugging and the like.
Description
Technical Field
The present disclosure relates to the field of chip design technologies, and in particular, to an automated design method, apparatus, device, and medium for register codes and documents.
Background
With the rapid development of new technologies and new processes, the functions of the chip become more and more complex, and the number of registers contained in the chip becomes more and more. For example, a 32-bit single chip microcomputer generally has 700 to 1200 registers, and the design modification of the registers is performed throughout the whole process of chip design.
At present, related codes and documents of a chip register are mainly maintained manually, the register is required to be continuously modified and deleted in different stages of chip development, and a large number of manual repeated development codes and edited documents can cause great error probability and development efficiency to be reduced, so that the development period and design cost of the chip are affected. There is data showing that register design errors account for 40% to 50% of chip design errors, and their main errors are mainly concentrated on register document description errors and register function design errors, especially description errors are easily ignored, resulting in products that cannot meet user requirements, causing user complaints.
In the related art, for the design of some complex chips, word, excel, html and other design tools are mainly adopted for aided design at present, and the aided design methods have the defects of large workload, low accuracy and low efficiency, and are difficult to discover in time once errors occur.
Therefore, how to efficiently guarantee the consistency of the register file description and the register code is a technical problem to be solved.
Disclosure of Invention
The main purpose of the application is to provide an automatic design method, device, equipment and medium for register codes and documents, which aims to solve the technical problems of large maintenance workload, low accuracy and low efficiency of manually carrying out the register codes and documents.
In a first aspect, the present application provides a method for automated design of register codes and documents, the method comprising the steps of:
acquiring chip level module parameters and register parameters input by a user through an interactive webpage, and generating a preset format file according to the chip level module parameters and the register parameters;
analyzing the preset format file to obtain analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode;
and analyzing the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
In some embodiments, the chip-level module parameters include: name, base address bit width, number of sets and clock set;
the register parameters include: register name, register address, register set number, domain name, domain type, domain bit width, and domain default.
In some embodiments, the generating a preset format file according to the chip level module parameter and the register parameter includes:
calling XML read-write operation Document class through the interactive webpage, and storing the chip level module parameters and the register parameter class into an XML file according to a chip level module;
and storing the node of each chip level module in the XML file as an element with a specific name, and storing the chip level module parameters and the register parameters associated with the node of the chip level module as element attributes.
In some embodiments, the parsing the preset format file to obtain a parse chip level module parameter and a parse register parameter for generating a code corresponding to the chip universal command interface, and storing the parse chip level module parameter and the parse register parameter in a hash table style includes:
and analyzing the XML file through a dynamic node analysis library module XML:: libXML and XML:: libXML::: XPathContext in the resolver Perl to obtain analysis chip level module parameters and analysis register parameters.
In some embodiments, the parsing the preset format file to obtain a parse chip level module parameter and a parse register parameter for generating a code corresponding to the chip universal command interface, and storing the parse chip level module parameter and the parse register parameter in a hash table style includes:
storing relevant parameters of each hierarchical module in the hierarchical modules of the analysis chip as a hash table, and nesting the hash tables of the hierarchical modules according to the hierarchy to form a multi-level nested hash table for storage;
the hash table of each hierarchical module only comprises a Key Value pair Key-Value, the parameters of the module are connected and combined by a preset symbol to form a character string as a Key, and the hash table of the next-level module of the module is combined into a plurality of groups to be used as the Value.
In some embodiments, before the hash table is parsed by a preset program to automatically generate a code corresponding to the chip universal command interface, the method further includes:
determining a bottommost module in each Key-Value in the multi-level nested hash table;
and taking the multi-stage address decoding information of the bottommost module as a Key, and taking a hash table stored with parameters associated with the bottommost module as a Value so as to convert the multi-stage nested hash table into an enhanced hash table.
In some embodiments, the parsing, by a preset program, the hash table to automatically generate a code corresponding to a chip universal command interface includes:
analyzing the enhanced hash table through a flexible algorithm in a preset Perl program, and automatically generating RTL codes, driving codes, register files and verification codes;
wherein, the RTL code is generated by calling an RTL template corresponding to the domain type by the Perl program according to the domain type contained in the register;
the RTL template is preset according to different domain types in a register, and the different domain types are distinguished through a domain parameter Access.
In a second aspect, the present application also provides an automated design apparatus for register codes and documents, the apparatus comprising:
the interactive webpage is used for acquiring project level module parameters and register parameters input by a user and generating a target file in a preset format according to the project level module parameters and the register parameters;
the analysis module is used for analyzing the preset format file, obtaining analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode;
and the generation module analyzes the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
In some embodiments, the chip-level module parameters include: name, base address bit width, number of sets and clock set;
the register parameters include: register name, register address, register set number, domain name, domain type, domain bit width, and domain default.
In some embodiments, the interactive web page is further configured to:
calling XML read-write operation Document class through the interactive webpage, and storing the chip level module parameters and the register parameter class into an XML file according to a chip level module;
and storing the node of each chip level module in the XML file as an element with a specific name, and storing the chip level module parameters and the register parameters associated with the node of the chip level module as element attributes.
In some embodiments, the parsing module is further configured to:
and analyzing the XML file through a dynamic node analysis library module XML:: libXML and XML:: libXML::: XPathContext in the resolver Perl to obtain analysis chip level module parameters and analysis register parameters.
In some embodiments, the parsing module is further configured to:
storing relevant parameters of each hierarchical module in the hierarchical modules of the analysis chip as a hash table, and nesting the hash tables of the hierarchical modules according to the hierarchy to form a multi-level nested hash table for storage;
the hash table of each hierarchical module only comprises a Key Value pair Key-Value, the parameters of the module are connected and combined by a preset symbol to form a character string as a Key, and the hash table of the next-level module of the module is combined into a plurality of groups to be used as the Value.
In some embodiments, the apparatus is further to:
determining a bottommost module in each Key-Value in the multi-level nested hash table;
and taking the multi-stage address decoding information of the bottommost module as a Key, and taking a hash table stored with parameters associated with the bottommost module as a Value so as to convert the multi-stage nested hash table into an enhanced hash table.
In some embodiments, the generating module is further configured to:
analyzing the enhanced hash table through a flexible algorithm in a preset Perl program, and automatically generating RTL codes, driving codes, register files and verification codes;
wherein, the RTL code is generated by calling an RTL template corresponding to the domain type by the Perl program according to the domain type contained in the register;
the RTL template is preset according to different domain types in a register, and the different domain types are distinguished through a domain parameter Access.
In a third aspect, the present application also provides a computer device comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the automated design method of register codes and documents as described above.
In a fourth aspect, the present application also provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the automated design method for register codes and documents as described above.
The application provides an automatic design method, device, equipment and medium for register codes and documents, wherein chip level module parameters and register parameters input by a user are acquired through an interactive webpage, and a preset format file is generated according to the chip level module parameters and the register parameters; analyzing the preset format file to obtain analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode; and analyzing the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface. The method can effectively reduce uncertainty caused by repeated manual development of register codes and documents, ensure continuity and stability of each version of the register codes and documents in a design period, and has the characteristics of high automation degree, high accuracy, high efficiency, good instantaneity, easiness in debugging and the like.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an automated design method for register codes and documents provided in an embodiment of the present application;
FIG. 2 is an interactive web page style sheet;
FIG. 3 is an XML file style sheet;
FIG. 4 is a schematic block diagram of an automated design apparatus for register codes and documents provided in an embodiment of the present application;
fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present application.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The flow diagrams depicted in the figures are merely illustrative and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be further divided, combined, or partially combined, so that the order of actual execution may be changed according to actual situations.
The embodiment of the application provides an automatic design method, device, equipment and medium for register codes and documents. The device can be a computer device such as a notebook computer and a desktop computer, and the automatic design method of the register codes and the documents can be applied to the computer device.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a flow chart of an automated design method for register codes and documents according to an embodiment of the present application.
As shown in fig. 1, the method includes steps S1 to S3.
Step S1, acquiring chip level module parameters and register parameters input by a user through an interactive webpage, and generating a preset format file according to the chip level module parameters and the register parameters.
Specifically, the generating a preset format file according to the chip level module parameter and the register parameter includes: calling XML read-write operation Document class through the interactive webpage, and storing the chip level module parameters and the register parameter class into an XML file according to a chip level module; and storing the node of each chip level module in the XML file as an element with a specific name, and storing the chip level module parameters and the register parameters associated with the node of the chip level module as element attributes.
Exemplary, as shown in FIG. 2, the interactive web page includes a parameter selection box of a plurality of chip-level module parameters and register parameters. The user may dynamically edit the chip level module parameters and the register parameters in the interactive web page. After the user edits the chip level module parameters and the register parameters in the interactive webpage and performs a saving operation, the edited chip level module parameters and register parameters are updated to the webpage database in real time. And then the web page calls the XMLCoumant class, and the chip level module parameters and the register parameters are respectively saved according to the chip level module to generate XML files which are mutually related. As shown in fig. 3, each chip-level module node in the XML file exists as an element of a specific name, and parameter information associated therewith exists in the form of an element attribute.
Illustratively, the chip-level module parameters include: name, base address bit width, number of sets and clock set; the register parameters include: register name, register address, register set number, domain name, domain type, domain bit width, and domain default.
And S2, analyzing the preset format file to obtain analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode.
Specifically, the parsing the preset format file to obtain a parsing chip level module parameter and a parsing register parameter for generating a code corresponding to a chip universal command interface, and storing the parsing chip level module parameter and the parsing register parameter in a hash table style, which includes:
and analyzing the XML file through a dynamic node analysis library module XML:: libXML and XML:: libXML::: XPathContext in the resolver Perl to obtain analysis chip level module parameters and analysis register parameters.
Further, the relevant parameters of each hierarchical module in the hierarchical modules of the analysis chip are stored as a hash table, and the hash tables of the hierarchical modules are nested according to the hierarchy to form a multi-level nested hash table for storage. The hash table of each hierarchical module only comprises a Key Value pair Key-Value, the parameters of the module are connected and combined by a preset symbol to form a character string as a Key, and the hash table of the next-level module of the module is combined into a plurality of groups to be used as the Value.
It is worth to describe that the XML file generated by the interactive web page is parsed by the dynamic node parsing library module XML in the parser Perl, libXML, XML, libXML, XPathContext, and the parsed chip level module and the parsed register parameters are stored by the multi-level nested hash table. The parameter information related to each level of hierarchical module is stored as a hash table style, and the table only comprises one Key-Value pair, wherein the parameters of the module are combined into a character string by using "-" as a Key, and all hash tables storing the information related to the sub-modules at the next level are combined into a plurality of groups as values. Thus, according to the item hierarchy, each hash table is nested step by step to form a whole table, and the whole table is used as the original data structure of the subsequent Perl program.
And S3, analyzing the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
As a preferred embodiment, before the hash table is parsed by a preset program to automatically generate a code corresponding to the chip universal command interface, the method further includes: determining a bottommost module in each Key-Value in the multi-level nested hash table; and taking the multi-stage address decoding information of the bottommost module as a Key, and taking a hash table stored with parameters associated with the bottommost module as a Value so as to convert the multi-stage nested hash table into an enhanced hash table.
For example, in order to automatically generate codes of various styles, the multi-level nested hash table needs to be processed, parsed and converted into a new data structure, so that the Perl program can directly read target information. Converting and reorganizing the multi-stage nested hash table to generate an enhanced hash table which is convenient to read, wherein the enhanced hash table comprises a plurality of Key Value pairs Key-Value pairs, and each Key Value pair takes a bottommost module as a center. The multi-level address decoding information of this module serves as Key, while the hash table storing its associated information serves as Value.
Specifically, the parsing, by a preset program, the hash table to automatically generate a code corresponding to the chip universal command interface includes: and analyzing the enhanced hash table through a flexible algorithm in a preset Perl program, and automatically generating RTL codes, driving codes, register files and verification codes. And the RTL code is generated by calling an RTL template corresponding to the domain type by the Perl program according to the domain type contained in the register. The RTL template is preset according to different domain types in a register, and the different domain types are distinguished through a domain parameter Access.
The preset program is a written Perl program for analyzing the enhanced hash table, and various codes related to the chip universal command interface are automatically generated through the Perl program enhanced hash table. The RTL code mainly comprises two parts, namely address routing and register configuration. In order to realize the configuration function of the register, in this embodiment, various domain types are designed first, and are distinguished by the domain parameter Access, and each domain type corresponds to a special RTL template. Next, generalized registers are configured, one of which may contain a plurality of different domain types. When the automated script parses the register, the target parameters are parsed by the fields contained therein, and the respective templates are called respectively to generate the register codes and documents corresponding to the chip-level module parameters and the register parameters.
It should be noted that the data processing may be performed by using web tool software such as HTML instead of XML, or may be performed by using script tool software such as python instead of perl.
The embodiment of the application provides an automatic design method for register codes and documents, and a designer can dynamically maintain the hierarchical module parameters and the register parameters of a chip through a visual platform, namely an interactive webpage in the application, in each stage of logic development of the chip and the register, and the database is updated in real time, so that the method is convenient and quick, has strong fault tolerance, effectively avoids uncertainty caused by manually editing the documents, and enables the register to be consistent in the whole development period. The storage register information adopts a specific XML style, has strong readability and portability, and is convenient for perl script processing; the visualized platform in the invention calls perl script program through menu, is convenient for designer to automatically generate register code and document by one key, has short code generation response time, is fast and efficient, and can ensure continuity and stability of each version of register code and document in the design period. Compared with the prior art, the method has the characteristics of high automation degree, high reliability, high efficiency, good real-time performance, easiness in debugging and the like.
Referring to fig. 4, fig. 4 is a schematic block diagram of an automated design apparatus for register codes and documents according to an embodiment of the present application.
As shown in fig. 4, the apparatus includes:
the interactive webpage is used for acquiring project level module parameters and register parameters input by a user and generating a target file in a preset format according to the project level module parameters and the register parameters;
the analysis module is used for analyzing the preset format file, obtaining analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode;
and the generation module analyzes the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
Wherein the chip level module parameters include: name, base address bit width, number of sets and clock set;
the register parameters include: register name, register address, register set number, domain name, domain type, domain bit width, and domain default.
Wherein the interactive web page is further configured to:
calling XML read-write operation Document class through the interactive webpage, and storing the chip level module parameters and the register parameter class into an XML file according to a chip level module;
and storing the node of each chip level module in the XML file as an element with a specific name, and storing the chip level module parameters and the register parameters associated with the node of the chip level module as element attributes.
Wherein, the parsing module is further configured to:
and analyzing the XML file through a dynamic node analysis library module XML:: libXML and XML:: libXML::: XPathContext in the resolver Perl to obtain analysis chip level module parameters and analysis register parameters.
Wherein, the parsing module is further configured to:
storing relevant parameters of each hierarchical module in the hierarchical modules of the analysis chip as a hash table, and nesting the hash tables of the hierarchical modules according to the hierarchy to form a multi-level nested hash table for storage;
the hash table of each hierarchical module only comprises a Key Value pair Key-Value, the parameters of the module are connected and combined by a preset symbol to form a character string as a Key, and the hash table of the next-level module of the module is combined into a plurality of groups to be used as the Value.
Wherein the device is also used for:
determining a bottommost module in each Key-Value in the multi-level nested hash table;
and taking the multi-stage address decoding information of the bottommost module as a Key, and taking a hash table stored with parameters associated with the bottommost module as a Value so as to convert the multi-stage nested hash table into an enhanced hash table.
Wherein, the generating module is further used for:
analyzing the enhanced hash table through a flexible algorithm in a preset Perl program, and automatically generating RTL codes, driving codes, register files and verification codes;
wherein, the RTL code is generated by calling an RTL template corresponding to the domain type by the Perl program according to the domain type contained in the register;
the RTL template is preset according to different domain types in a register, and the different domain types are distinguished through a domain parameter Access.
It should be noted that the generating module includes an RTL code generating unit, a driving code generating unit, a register file generating unit, and a verification code generating unit, which are used for generating the RTL code, the driving code, the register file, and the verification code, respectively.
It should be noted that, for convenience and brevity of description, specific working procedures of the above-described apparatus and each module and unit may refer to corresponding procedures in the foregoing embodiments, and are not repeated herein.
The apparatus provided by the above embodiments may be implemented in the form of a computer program which may be run on a computer device as shown in fig. 5.
Referring to fig. 5, fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device may be a terminal.
As shown in fig. 5, the computer device includes a processor, a memory, and a network interface connected by a system bus, wherein the memory may include a non-volatile storage medium and an internal memory.
The non-volatile storage medium may store an operating system and a computer program. The computer program includes program instructions that, when executed, cause the processor to perform any of a variety of automated design methods for register code and documents.
The processor is used to provide computing and control capabilities to support the operation of the entire computer device.
The internal memory provides an environment for the execution of a computer program in a non-volatile storage medium that, when executed by a processor, causes the processor to perform any of a variety of automated design methods for register code and documentation.
The network interface is used for network communication such as transmitting assigned tasks and the like. It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
It should be appreciated that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Embodiments of the present application also provide a computer readable storage medium having a computer program stored thereon, where the computer program includes program instructions, where the method implemented when the program instructions are executed may refer to the embodiments of the present application.
The computer readable storage medium may be an internal storage unit of the computer device according to the foregoing embodiment, for example, a hard disk or a memory of the computer device. The computer readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like, which are provided on the computer device.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments. While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An automated register code and document design method, comprising:
acquiring chip level module parameters and register parameters input by a user through an interactive webpage, and generating a preset format file according to the chip level module parameters and the register parameters;
analyzing the preset format file to obtain analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode;
and analyzing the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
2. An automated register code and document design method according to claim 1, wherein:
the chip level module parameters include: name, base address bit width, number of sets and clock set;
the register parameters include: register name, register address, register set number, domain name, domain type, domain bit width, and domain default.
3. The automated register code and document design method of claim 1, wherein said generating a pre-formatted file based on said chip-level module parameters and said register parameters comprises:
calling XML read-write operation Document class through the interactive webpage, and storing the chip level module parameters and the register parameter class into an XML file according to a chip level module;
and storing the node of each chip level module in the XML file as an element with a specific name, and storing the chip level module parameters and the register parameters associated with the node of the chip level module as element attributes.
4. The automated register code and document design method of claim 3, wherein said parsing said pre-formatted file to obtain parsed chip-level module parameters and parsed register parameters for generating codes corresponding to chip universal command interfaces, and storing in a hash table style, comprises:
and analyzing the XML file through a dynamic node analysis library module XML:: libXML and XML:: libXML::: XPathContext in the resolver Perl to obtain analysis chip level module parameters and analysis register parameters.
5. The automated register code and document design method of claim 1, wherein said parsing said pre-formatted file to obtain parsed chip-level module parameters and parsed register parameters for generating codes corresponding to chip universal command interfaces, and storing in a hash table style, comprises:
storing relevant parameters of each hierarchical module in the hierarchical modules of the analysis chip as a hash table, and nesting the hash tables of the hierarchical modules according to the hierarchy to form a multi-level nested hash table for storage;
the hash table of each hierarchical module only comprises a Key Value pair Key-Value, the parameters of the module are connected and combined by a preset symbol to form a character string as a Key, and the hash table of the next-level module of the module is combined into a plurality of groups to be used as the Value.
6. The automated register code and document design method of claim 5, further comprising, prior to parsing the hash table by a pre-set program to automatically generate a code corresponding to a chip universal command interface:
determining a bottommost module in each Key-Value in the multi-level nested hash table;
and taking the multi-stage address decoding information of the bottommost module as a Key, and taking a hash table stored with parameters associated with the bottommost module as a Value so as to convert the multi-stage nested hash table into an enhanced hash table.
7. The automated register code and document design method according to claim 6, wherein said parsing said hash table by a preset program to automatically generate a code corresponding to a chip universal command interface comprises:
analyzing the enhanced hash table through a flexible algorithm in a preset Perl program, and automatically generating RTL codes, driving codes, register files and verification codes;
wherein, the RTL code is generated by calling an RTL template corresponding to the domain type by the Perl program according to the domain type contained in the register;
the RTL template is preset according to different domain types in a register, and the different domain types are distinguished through a domain parameter Access.
8. An automated register code and document design apparatus comprising:
the interactive webpage is used for acquiring project level module parameters and register parameters input by a user and generating a target file in a preset format according to the project level module parameters and the register parameters;
the analysis module is used for analyzing the preset format file, obtaining analysis chip level module parameters and analysis register parameters for generating codes corresponding to the chip universal command interface, and storing the analysis chip level module parameters and the analysis register parameters in a hash table mode;
and the generation module analyzes the hash table through a preset program to automatically generate codes corresponding to the chip universal command interface.
9. A computer device comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the automated design method for register codes and documents according to any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when being executed by a processor, implements the steps of the automated design method of register codes and documents according to any one of claims 1 to 7.
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| CN202310186519.2A CN116151162A (en) | 2023-02-28 | 2023-02-28 | Automatic design method, device, equipment and medium for register codes and documents |
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