CN116150077A - Device and method for processing outgoing port transaction of PCIe switching circuit - Google Patents
Device and method for processing outgoing port transaction of PCIe switching circuit Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The invention provides an outbound transaction processing device and method of a PCIe switching circuit, comprising a main control module, wherein the main control module is interactively connected with a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interactively connected with an analysis conversion module and two load FIFOs, the information generation and header FIFO control module is interactively connected with a load receiving and conversion module and three packet header FIFOs, the analysis conversion module is interactively connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interactively connected with an arbitration table and a loading module thereof, and the three packet header FIFOs and the two load FIFO output ends are respectively connected with a reading and sending module; the received transaction packets are classified and stored by the three packet header FIFOs and the two payload FIFOs, and the writing and reading of the transaction are simple and reliable; the problem that transactions of part of delay sensitive input ports cannot be output through the output ports in time is avoided.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to an output port transaction processing device and method of a PCIe switching circuit.
Background
PCIe bus is a third generation high performance IO bus that is pushed behind the first generation EISA, ISA, VESA bus and the second generation AGP, PCI, PCI-X bus, and is widely used in computer systems.
In a PCIe system, a PCIe switch circuit is used for interconnecting and communicating a plurality of electronic components or modules, where the PCIe switch circuit generally has two or more PCIe ports, a port for receiving a transaction from an external device is called an ingress port, and a port for pushing the transaction out of the circuit is called an egress port; transactions that need to be exchanged inside PCIe switching circuits include memory transactions, IO transactions, configuration transactions, message transactions. Wherein the memory write transaction and message transaction packets are forwarding transaction packets (Posted TLPs), the IO transaction request, the configuration transaction request, and the memory read transaction request packets are Non-forwarding transaction packets (NP TLPs), which require the receiving device to return a Completion packet (Completion TLP).
The output port is a main component of the PCIe switching circuit, however, the transaction processing procedure of the PCIe circuit in the prior art is complex, cannot judge the data integrity, and lacks a length error processing procedure of the transaction.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an output port transaction processing device and method of a PCIe switching circuit, which have the advantages of simple and reliable writing and reading control of transactions and dynamic regulation of output port storage load.
The invention is realized by the following technical scheme:
the port transaction processing device of the PCIe switching circuit is characterized by comprising a main control module, wherein the main control module is interactively connected with a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interactively connected with an analysis conversion module and two load FIFOs, the information generation and header FIFO control module is interactively connected with a load receiving and conversion module and three packet header FIFOs, the analysis conversion module is interactively connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interactively connected with an arbitration table and a loading module thereof, and the three packet header FIFOs and the two load FIFO output ends are respectively connected with a reading and sending module;
the input end of the information generation and header FIFO control module is connected with an output end capacity upper limit register signal UprC and an output end capacity lower limit register signal lowC, and outputs a forbidden request signal, the input ends of the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal is also connected with the main control module, the input end of the port arbitration logic module is connected with a switching request signal, the output end of the port arbitration logic module is connected with a response signal, the input end of the arbitration table and the loading module is connected with a PAT loading command signal and a PAT loading value signal, the output end of the arbitration table is connected with a PAT loading completion signal, the output end of the reading and sending module is connected with a sending interface signal, and the output end of the arbitration logic module is connected with a communication amount signal.
Preferably, the three packet header FIFOs include nph_fifo, ch_fifo, and ph_fifo, and the two payload FIFOs include cd_fifo and pd_fifo.
Preferably, the nph_fifo has a bit width of 165 bits, the ch_fifo and the ph_fifo have a bit width of 133 bits, 5 bits in each address unit of the three packet header FIFOs are sequence number bits, and the other bits store the transaction packet header or ECRC.
Preferably, each address unit of the two payload FIFOs sets a one-bit end bit and a one-bit end bit, the payload FIFOs have a bit width of 66 bits in the x4 link port mode and a bit width of 130 bits in the x8 link port mode;
the sequence number bit, header format Fmt, TLP Type and Length field memory bank in the header FIFO are implemented by registers, and the memory banks of other bits are implemented by memories.
Preferably, the arbitration table and the loading module thereof are configured to load the port arbitration table according to the loading command and generate a loading completion signal when the current exchange transaction receives the last clock cycle of completion or no transaction is received.
Preferably, the arbitration table and the output port of the loading module thereof are internally maintained with a 32-phase Port Arbitration Table (PAT) for use by port arbitration logic.
An egress port transaction processing method of a PCIe switching circuit, comprising the steps of:
s101, analyzing the request data of an input port by an analysis conversion module, and judging whether the cache of the corresponding type is enough to store the request data according to the transaction packet type and the data length;
s102, after the previous transaction is finished, the port arbitration logic decides whether to authorize the main control logic to respond to the current exchange request of the input port which is rotated by the internal port arbitration table according to whether the buffer memory judged by the analysis conversion module is enough to store the corresponding request data:
s103, when the receiving buffer capacity of the current transaction is insufficient to store the current transaction, not responding to the exchange request of the input port which is turned to currently, port arbitration jumps to the next phase, and processing of the next input port is started from the step S101;
s104, when the receiving buffer capacity of the current transaction can store the current transaction, responding to the exchange request of the input port which is turned to by the current transaction, writing the request data into the corresponding packet head FIFO and the load FIFO, and completing the generation and buffer writing of sequence numbers, end marks, termination bits and the like;
s105, the reading and sending module reads one of the three packet header FIFOs and one possible load FIFO according to PCIE ordering rules according to information such as the information input by the credit, the serial numbers of the packet header FIFOs and the like, and sends the read transaction packet according to the interface requirement of the sending interface.
Preferably, the step S104 includes the steps of:
a1, an analysis conversion module receives request data of an input port, and performs bit width conversion on a transaction packet head according to bit width requirements of a packet head FIFO;
a2, the information generation and header FIFO control module stores the packet header of the completion packet after the bit width conversion or the packet header of the P transaction into a corresponding transaction packet header FIFO, stores NPH_FIFO and possible data load into NPH_FIFO, generates a sequence number according to the sequence of receiving the transaction when the packet header of the transaction is stored into the corresponding transaction packet header FIFO, and writes the sequence number and the packet header of the transaction subjected to the bit width conversion into the corresponding transaction packet header FIFO;
a3, the load receiving and converting module receives the request data from the input port, and performs bit width conversion on the data load requested by the completion packet or the forwarding transaction packet according to the bit width requirement of the corresponding load FIFO according to the indication of the configuration signal;
a4, the limit generation and load FIFO control module receives the data load of the completion packet or the forwarding transaction packet output by the load receiving and converting module and caches the data load into a completion packet load FIFO or a PD_FIFO; generating an end tag and writing an end bit of the FIFO at the last data payload write of each transaction; when the data load analyzed by the transaction packet head is inconsistent with the load data quantity actually requested or ECRC check error occurs in the current transaction, generating a termination mark and writing the termination mark into a termination bit of the FIFO; when the data load analyzed by the transaction packet header is smaller than the load data volume actually requested, writing corresponding load FIFO according to the number of the data loads analyzed by the packet header, and throwing away redundant load data.
Preferably, when writing the packet header FIFO in step S104, the information generating and header FIFO control module calculates the total number of transaction packets stored in the three packet header FIFOs and compares the total number of transaction packets with the value of the output-side capacity upper limit register, and sets the disable request signal in the valid state when the total number of transaction packets is greater than or equal to the value of the output-side capacity upper limit register, so that the input port is disabled from sending a new exchange request.
Preferably, after the transaction packet header is read in step S105, if the total number of transaction packets stored in the three packet header FIFOs is lower than the value of the lower limit register of the output port capacity, the information generating and header FIFO control module clears the disable request signal, and enables the switch request of the input port.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides an output port transaction processing device and method of PCIe exchange circuit,
the system comprises a main control module, wherein the main control module is interactively connected with a limit generation and load FIFO control module, an information generation and head FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interactively connected with an analysis conversion module and two load FIFOs, the information generation and head FIFO control module is interactively connected with a load receiving and conversion module and three packet head FIFOs, the analysis conversion module is interactively connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interactively connected with an arbitration table and a loading module thereof, and the three packet head FIFOs and the two load FIFO output ends are respectively connected with a reading and transmitting module; the input end of the information generation and header FIFO control module is connected with an output end capacity upper limit register signal UprC and an output end capacity lower limit register signal lowC, and outputs a forbidden request signal, the input ends of the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal is also connected with the main control module, the input end of the port arbitration logic module is connected with a switching request signal, the output end of the port arbitration logic module is connected with a response signal, the input end of the arbitration table and the loading module is connected with a PAT loading command signal and a PAT loading value signal, the output end of the arbitration table and the loading module is connected with a PAT loading completion signal, the output end of the reading and sending module is connected with a sending interface signal, and the output end of the arbitration logic module is connected with a credit signal; the application has the following advantages: 1. the received transaction packets are classified and stored by three packet header FIFOs and two payload FIFOs, and the writing and reading control of the transaction is simple and reliable; 2. key information such as sequence number bits, header format Fmt and the like in the packet head FIFO is stored by a register, and memory banks of other bits are stored by a memory, so that the register can output the stored key information without reading while ensuring that the memory bank of the transaction has smaller area overhead in a circuit, and the lower processing logic is convenient for reading and sending scheduling of the stored transaction; 3. by generating and writing the end mark when the last data load of each transaction is written, writing the end mark when the transaction fails and throwing away redundant load data, the length error of the transaction is ensured to be processed by the output port, and the data integrity of the load FIFO is ensured; 4. through reasonable arrangement of the output port capacity upper limit register, excessive transactions cached in the output port are avoided, the problem that partial transactions of the input port sensitive to delay cannot be output through the output port in time is avoided, and the output port storage load has a dynamic adjusting function.
Drawings
FIG. 1 is a schematic block diagram of a PCIe switched circuit egress port transaction device in accordance with an embodiment of the present invention;
fig. 2 is a diagram showing the composition of a memory read request transaction packet in the nph_fifo of the present embodiment.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention provides an outbound transaction processing device of a PCIe switching circuit, as shown in figure 1, which comprises a main control module, wherein the main control module is interactively connected with a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interactively connected with an analysis conversion module and two load FIFOs, the information generation and header FIFO control module is interactively connected with a load receiving and conversion module and three packet header FIFOs, the analysis conversion module is interactively connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interactively connected with an arbitration table and a loading module thereof, and the three packet headers and the two load FIFO output ends are respectively connected with a reading and sending module;
the input end of the information generation and header FIFO control module is connected with an output end capacity upper limit register signal UprC and an output end capacity lower limit register signal lowC, and outputs a forbidden request signal, the input ends of the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal is also connected with the main control module, the input end of the port arbitration logic module is connected with a switching request signal, the output end of the port arbitration logic module is connected with a response signal, the input end of the arbitration table and the loading module is connected with a PAT loading command signal and a PAT loading value signal, the output end of the arbitration table is connected with a PAT loading completion signal, the output end of the reading and sending module is connected with a sending interface signal, and the output end of the arbitration logic module is connected with a communication amount signal.
The analysis conversion module is used for interacting with the configuration signal, the information generation and header FIFO control module, the main control module and the port arbitration logic, receiving the request data of the input port under the control of the main control module and the configuration signal, analyzing the type and the data length of the transaction packet and converting the bit width, and judging whether the cache is enough to store the request data;
the information generation and header FIFO control module is used for storing the packet header of the finished packet or the packet header of the P transaction into the corresponding header FIFO under the control of the main control module, and storing the packet header of the NP transaction and the possible data load into the NPH_FIFO; generating a sequence number and writing the sequence number and the transaction packet header into a corresponding transaction packet header FIFO; in addition, the module also generates a prohibition request signal according to the value of the capacity upper limit register of the output port, the value of the capacity lower limit register and the total number of transaction packets stored in the head FIFO;
the load receiving and converting module is used for receiving the request data from the input port and converting the bit width of the data load of the request of the completion packet or the forwarding transaction packet according to the indication of the configuration signal;
the limit generation and load FIFO control module is used for receiving the data load of the completion packet or the forwarding transaction packet output by the load receiving and converting module and caching the data load into a completion packet load FIFO or a P transaction load FIFO; generating an end tag and writing an end bit of the FIFO at the last data payload write of each transaction; when the data load analyzed by the transaction packet head is inconsistent with the load data quantity actually requested or ECRC check error occurs in the current transaction, generating a termination mark and writing the termination mark into a termination bit of the FIFO; when the data load analyzed by the transaction packet header is smaller than the load data volume actually requested, writing the transaction load FIFO according to the number of the data loads analyzed by the packet header, and throwing away redundant load data;
the arbitration table and the loading module thereof are used for maintaining a port arbitration table in the outlet port for port arbitration logic, loading the port arbitration table according to a loading command and generating a loading completion signal when the current exchange transaction is received in the last clock cycle or no transaction is received;
the port arbitration logic module is used for deciding whether the main control module is authorized to respond to the transaction exchange request of the port which is currently turned to according to the current transaction number in the output port cache and the receiving cache capacity of the current transaction after the current transaction processing is completed and giving a response to the exchange request;
the main control module is used for receiving the authorization of the port arbitration module, controlling the analysis conversion module, the information generation and header FIFO control module, the load receiving and conversion module and the limit generation and load FIFO control module to complete the respective functions;
the reading and sending module is used for reading one of the three packet header FIFOs and one possible load FIFO according to the PCIE ordering rule according to the credit input, the serial number of each packet header FIFO and other information, and sending the read transaction packet according to the interface requirement of the sending interface; specifically, when the transaction packet sequence number of a certain FIFO queue head in the three packet header FIFOs is minimum and the credit amount of the corresponding Type transaction is greater than or equal to the credit amount required by the transaction packet, reading the transaction packet (including the packet header and possible loads indicated by Fmt, type and Length in the packet header), and sending the read transaction packet according to the interface requirement of the sending interface; when the transaction packet sequence number of a certain FIFO queue head in the three packet header FIFOs is minimum but the credit amount of the corresponding type of transaction is smaller than the credit amount required by the transaction packet, selecting a transaction packet (comprising possible load) which can exceed the transaction packet and has the credit amount of the corresponding type of transaction larger than or equal to the credit amount required by the transaction packet according to the PCIE ordering rule, and sending the read transaction packet according to the interface requirement of the sending interface; because the storage bodies of the sequence number bits, the Fmt, the Type and the Length in the packet header FIFO are registers, the reading and sending module can acquire the values of the sequence number, the Fmt, the Type and the Length without reading the packet header FIFO, thereby conveniently comparing the sequence numbers of the three packet header FIFOs with the credit required by determining the transaction.
Preferably, the three packet header FIFOs include nph_fifo, ch_fifo and ph_fifo, the two payload FIFOs include cd_fifo and pd_fifo, wherein the nph_fifo has a bit width of 165 bits, the ch_fifo and ph_fifo has a bit width of 133 bits, 5 bits in each address unit of the three packet header FIFOs are sequence number bits, and the other bits store transaction packet header or ECRC; setting a bit end bit and a bit end bit for each address unit of the two load FIFOs, wherein the bit width of the load FIFOs is 66 bits in an x4 link port mode, and the bit width of the load FIFOs is 130 bits in an x8 link port mode; the sequence number bit, header format Fmt, TLP Type and Length field memory bank in the header FIFO are implemented by registers, and the memory banks of other bits are implemented by memories. Specifically, as shown in fig. 2, a memory read request transaction packet with a 64-bit memory address is formed in the nph_fifo of the present embodiment; the memory read request transaction belongs to an NP transaction, and as can be seen in fig. 2, the transaction packet occupies 128 bits, the sequence number bit occupies 5 bits, and the ECRC of the transaction packet occupies 32 bits in the NP transaction header FIFO.
Preferably, the arbitration table and the loading module thereof are used for loading the port arbitration table according to the loading command and generating a loading completion signal when the current exchange transaction receives the last clock cycle of completion or no transaction is received; the arbitration table and the output port of the loading module thereof maintain a 32-phase Port Arbitration Table (PAT) for use by port arbitration logic, and it should be noted that: when the current exchange transaction receives the last clock cycle of completion or does not receive the transaction, the port arbitration table is loaded according to the loading command and a loading completion signal is generated, specifically: when the arbitration table and the loading module receive the port arbitration table loading command: if the output port is not currently in the process of receiving the exchange transaction of a certain input port, immediately updating a port arbitration table maintained in the output port and making an indication of finishing updating; if the output port is receiving the exchange transaction of a certain input port, firstly storing the received loading command until the last clock period of the current exchange transaction to be received is about to be completed, updating the internally maintained port arbitration table and making an instruction of completing the updating; the port arbitration logic determines whether the main control module is authorized to respond to the transaction exchange request of the port which is turned to currently according to the current transaction number in the output port cache and the receiving cache capacity of the current transaction after the current transaction is finished, and gives a response to the exchange request; the port rotation rotates in the port order indicated by the port arbitration table 0 to 31 phase values of the internal 32 phase.
The invention provides an outgoing port transaction processing method of a PCIe switching circuit, which comprises the following steps:
s101, analyzing the request data of an input port by an analysis conversion module, and judging whether the cache of the corresponding type is enough to store the request data according to the transaction packet type and the data length;
s102, after the previous transaction is finished, the port arbitration logic decides whether to authorize the main control logic to respond to the current exchange request of the input port which is rotated by the internal port arbitration table according to whether the buffer memory judged by the analysis conversion module is enough to store the corresponding request data:
s103, when the receiving buffer capacity of the current transaction is insufficient to store the current transaction, not responding to the exchange request of the input port which is turned to currently, port arbitration jumps to the next phase, and processing of the next input port is started from the step S101;
s104, when the receiving buffer capacity of the current transaction can store the current transaction, responding to the exchange request of the input port which is turned to by the current transaction, writing the request data into the corresponding packet head FIFO and the load FIFO, and completing the generation and buffer writing of sequence numbers, end marks, termination bits and the like;
s105, the reading and sending module reads one of the three packet header FIFOs and one possible load FIFO according to PCIE ordering rules according to information such as the information input by the credit, the serial numbers of the packet header FIFOs and the like, and sends the read transaction packet according to the interface requirement of the sending interface.
Preferably, the step S104 includes the steps of:
a1, an analysis conversion module receives request data of an input port, and performs bit width conversion on a transaction packet head according to bit width requirements of a packet head FIFO;
a2, the information generation and header FIFO control module stores the packet header of the completion packet after the bit width conversion or the packet header of the P transaction into a corresponding transaction packet header FIFO, stores NPH_FIFO and possible data load into NPH_FIFO, generates a sequence number according to the sequence of receiving the transaction when the packet header of the transaction is stored into the corresponding transaction packet header FIFO, and writes the sequence number and the packet header of the transaction subjected to the bit width conversion into the corresponding transaction packet header FIFO;
a3, the load receiving and converting module receives the request data from the input port, and performs bit width conversion on the data load requested by the completion packet or the forwarding transaction packet according to the bit width requirement of the corresponding load FIFO according to the indication of the configuration signal;
a4, the limit generation and load FIFO control module is used for receiving the completion packet output by the load receiving and converting module or the data load of the forwarding transaction packet and caching the data load into a completion packet load FIFO or a PD_FIFO; generating an end tag and writing an end bit of the FIFO at the last data payload write of each transaction; when the data load analyzed by the transaction packet head is inconsistent with the load data quantity actually requested or ECRC check error occurs in the current transaction, generating a termination mark and writing the termination mark into a termination bit of the FIFO; when the data load analyzed by the transaction packet header is smaller than the load data volume actually requested, writing corresponding load FIFO according to the number of the data loads analyzed by the packet header, and throwing away redundant load data.
Preferably, when writing the packet header FIFO in step S104, the information generating and header FIFO control module calculates the total number of transaction packets stored in the three packet header FIFOs and compares the total number of transaction packets with the value of the output-side capacity upper limit register, and sets the disable request signal in the valid state when the total number of transaction packets is greater than or equal to the value of the output-side capacity upper limit register, so that the input port is disabled from sending a new exchange request.
Preferably, after the transaction packet header is read in step S105, if the total number of transaction packets stored in the three packet header FIFOs is lower than the value of the lower limit register of the output port capacity, the information generating and header FIFO control module clears the disable request signal, and enables the switch request of the input port.
Claims (10)
1. The port transaction processing device of the PCIe switching circuit is characterized by comprising a main control module, wherein the main control module is interactively connected with a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interactively connected with an analysis conversion module and two load FIFOs, the information generation and header FIFO control module is interactively connected with a load receiving and conversion module and three packet header FIFOs, the analysis conversion module is interactively connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interactively connected with an arbitration table and a loading module thereof, and the three packet header FIFOs and the two load FIFO output ends are respectively connected with a reading and sending module;
the input end of the information generation and header FIFO control module is connected with an output end capacity upper limit register signal UprC and an output end capacity lower limit register signal lowC, and outputs a forbidden request signal, the input ends of the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal is also connected with the main control module, the input end of the port arbitration logic module is connected with a switching request signal, the output end of the port arbitration logic module is connected with a response signal, the input end of the arbitration table and the loading module is connected with a PAT loading command signal and a PAT loading value signal, the output end of the arbitration table is connected with a PAT loading completion signal, the output end of the reading and sending module is connected with a sending interface signal, and the output end of the arbitration logic module is connected with a communication amount signal.
2. The egress port transaction device of the PCIe switch circuit of claim 1 wherein the three packet header FIFOs comprise nph_fifo, ch_fifo, and ph_fifo, and the two payload FIFOs comprise cd_fifo and pd_fifo.
3. The device of claim 2, wherein the nph_fifo has a bit width of 165 bits, the ch_fifo and ph_fifo have a bit width of 133 bits, 5 bits in each address unit of the three packet header FIFOs are sequence number bits, and the other bits store transaction packet header or ECRC.
4. The egress port transaction device of claim 2, wherein each address unit of the two payload FIFOs sets a one-bit end bit and a one-bit end bit, the payload FIFOs having a bit width of 66 bits in x4 link port mode and a bit width of 130 bits in x8 link port mode;
the sequence number bit, header format Fmt, TLP Type and Length field memory bank in the header FIFO are implemented by registers, and the memory banks of other bits are implemented by memories.
5. The device of claim 1, wherein the arbitration table and the loading module are configured to load the port arbitration table and generate the load complete signal according to a load command when the last clock cycle for which the current switch transaction was received is complete or when no transaction is received.
6. The device of claim 5, wherein the arbitration table and the output port of the load module maintain a 32-phase Port Arbitration Table (PAT) for use by port arbitration logic.
7. An egress port transaction processing method of a PCIe switching circuit, characterized by an egress port transaction processing device of a PCIe switching circuit based on any one of claims 1-6, comprising the steps of:
s101, analyzing the request data of an input port by an analysis conversion module, and judging whether the cache of the corresponding type is enough to store the request data according to the transaction packet type and the data length;
s102, after the previous transaction is finished, the port arbitration logic decides whether to authorize the main control logic to respond to the current exchange request of the input port which is rotated by the internal port arbitration table according to whether the buffer memory judged by the analysis conversion module is enough to store the corresponding request data:
s103, when the receiving buffer capacity of the current transaction is insufficient to store the current transaction, not responding to the exchange request of the input port which is turned to currently, port arbitration jumps to the next phase, and processing of the next input port is started from the step S101;
s104, when the receiving buffer capacity of the current transaction can store the current transaction, responding to the exchange request of the input port which is turned to by the current transaction, writing the request data into the corresponding packet head FIFO and the load FIFO, and completing the generation and buffer writing of sequence numbers, end marks, termination bits and the like;
s105, the reading and sending module reads one of the three packet header FIFOs and one possible load FIFO according to PCIE ordering rules according to information such as the information input by the credit, the serial numbers of the packet header FIFOs and the like, and sends the read transaction packet according to the interface requirement of the sending interface.
8. The method for processing the outgoing port transaction of the PCIe switching circuit according to claim 7, wherein the step S104 comprises the steps of:
a1, an analysis conversion module receives request data of an input port, and performs bit width conversion on a transaction packet head according to bit width requirements of a packet head FIFO;
a2, the information generation and header FIFO control module stores the packet header of the completion packet after the bit width conversion or the packet header of the P transaction into a corresponding transaction packet header FIFO, stores NPH_FIFO and possible data load into NPH_FIFO, generates a sequence number according to the sequence of receiving the transaction when the packet header of the transaction is stored into the corresponding transaction packet header FIFO, and writes the sequence number and the packet header of the transaction subjected to the bit width conversion into the corresponding transaction packet header FIFO;
a3, the load receiving and converting module receives the request data from the input port, and performs bit width conversion on the data load requested by the completion packet or the forwarding transaction packet according to the bit width requirement of the corresponding load FIFO according to the indication of the configuration signal;
a4, the limit generation and load FIFO control module receives the data load of the completion packet or the forwarding transaction packet output by the load receiving and converting module and caches the data load into a completion packet load FIFO or a PD_FIFO; generating an end tag and writing an end bit of the FIFO at the last data payload write of each transaction; when the data load analyzed by the transaction packet head is inconsistent with the load data quantity actually requested or ECRC check error occurs in the current transaction, generating a termination mark and writing the termination mark into a termination bit of the FIFO; when the data load analyzed by the transaction packet header is smaller than the load data volume actually requested, writing corresponding load FIFO according to the number of the data loads analyzed by the packet header, and throwing away redundant load data.
9. The method according to claim 7, wherein the information generating and header FIFO control module calculates the total number of transaction packets stored in the three packet header FIFOs and compares the total number with the value of the egress capacity upper limit register when the total number of transaction packets is greater than or equal to the value of the egress capacity upper limit register, sets the disable request signal in an active state, and disables the input port from transmitting a new exchange request when the packet header FIFO is written in step S104.
10. The method according to claim 7, wherein after the transaction packet header is read in step S105, if the total number of the transaction packets stored in the three packet header FIFOs is lower than the value of the egress port capacity lower limit register, the information generation and header FIFO control module clears the disable request signal to enable the switch request of the input port.
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| CN117290272A (en) * | 2023-11-23 | 2023-12-26 | 井芯微电子技术(天津)有限公司 | PCIe Switch and realization method of configuration access thereof |
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| CN117290272A (en) * | 2023-11-23 | 2023-12-26 | 井芯微电子技术(天津)有限公司 | PCIe Switch and realization method of configuration access thereof |
| CN117290272B (en) * | 2023-11-23 | 2024-02-23 | 井芯微电子技术(天津)有限公司 | PCIe Switch and realization method of configuration access thereof |
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