CN116150072A

CN116150072A - Clock signal receiving circuit, clock signal receiving device and electronic equipment

Info

Publication number: CN116150072A
Application number: CN202310417054.7A
Authority: CN
Inventors: 龙爽
Original assignee: Beijing Chaomo Technology Co ltd
Current assignee: Beijing Chaomo Technology Co ltd
Priority date: 2023-04-19
Filing date: 2023-04-19
Publication date: 2023-05-23
Anticipated expiration: 2043-04-19
Also published as: CN116150072B

Abstract

The invention provides a clock signal receiving circuit, a clock signal receiving device and electronic equipment, which are used for receiving a clock signal through a signal type judging module, judging the type of the clock signal and outputting a corresponding judging signal; the common mode potential adjustment module performs adaptive first processing on the clock signal according to the judgment signal to output an adjustment clock signal, and the clock signal amplification module performs adaptive second processing on the adjustment clock signal according to the judgment signal to output a clock amplification signal; the duty ratio judgment module extracts the duty ratio information of the clock amplified signal, compares the duty ratio information with a preset duty ratio, and outputs a duty ratio judgment signal to the common mode potential adjustment module and the clock signal amplification module so as to adjust the duty ratio of the clock signal and the clock signal, so that the finally output clock amplified signal meets the requirement of the preset signal common mode potential and the preset signal duty ratio, and the quality of signal transmission is ensured.

Description

Clock signal receiving circuit, clock signal receiving device and electronic equipment

Technical Field

The present invention relates to the field of semiconductor chips, and in particular, to a clock signal receiving circuit, a clock signal receiving device, and an electronic device.

Background

In recent years, the field of data communication by high-speed parallel communication technology, especially in the field of short-distance chip interconnection and the like, has been widely used, and parallel transmission of information does not require that the transmitted information be in a fixed format.

Short-range high-speed parallel interfaces commonly used at present, including UCie interfaces, boW interfaces, AIB interfaces and the like, are widely applied to equipment and systems needing short-range and high-speed data exchange.

The clock signal receiving end device of the existing high-speed parallel interface can only receive one clock signal. The clock signal receiving end devices are generally divided into a double-ended clock signal receiving device and a single-ended clock signal receiving device with a phase difference according to different clock signals, and are amplified and shaped by a standard logic unit (e.g., an inverter, etc.) or a double-ended amplifying unit (e.g., a current-mode logic circuit) with a phase difference. However, the common high-speed clock signal amplifier has high requirements on the common mode level of the input clock signal, and different amplifying circuits are designed according to different clock signals, for example, when amplifying a single-ended clock signal, a separate common mode level reference voltage generating circuit is required to be designed to provide a reference voltage for the single-ended clock signal.

Therefore, how to realize that the clock signal receiving end device can receive and process various clock signals, and ensure the quality of signal transmission, has become a technical problem to be solved in the industry.

Disclosure of Invention

The invention provides a clock signal receiving circuit, a clock signal receiving device and electronic equipment, which are used for solving the technical problem of how to realize that a clock signal receiving end device can receive and process various clock signals and ensure the quality of signal transmission.

According to a first aspect of the present invention, there is provided a clock signal receiving circuit comprising:

the signal type judging module is used for receiving a clock signal, judging the type of the clock signal and outputting a corresponding judging signal; wherein the types of clock signals include a single-ended clock signal and a double-ended clock signal having a phase difference; the decision signal is used for representing the type of the clock signal;

the common mode potential adjustment module is used for receiving the clock signal and the judgment signal, and performing first processing which is adaptive to the type of the clock signal on the clock signal according to the type of the clock signal represented by the judgment signal so as to output an adjustment clock signal; wherein the first process includes at least a common mode potential shift process;

The clock signal amplifying module is used for receiving the judging signal and the adjusting clock signal, carrying out second processing which is adaptive to the type of the clock signal on the adjusting clock signal according to the type of the clock signal represented by the judging signal, and outputting a clock amplifying signal; wherein the second process includes at least an amplification process;

the duty ratio judgment module is used for receiving the clock amplification signal, extracting duty ratio information of the clock amplification signal, comparing the extracted duty ratio information with a preset duty ratio, and outputting a duty ratio judgment signal to the common mode potential adjustment module and the clock signal amplification module, wherein the common mode potential adjustment module and the clock signal amplification module respectively adjust the duty ratio of the clock signal and the duty ratio of the adjustment clock signal according to the duty ratio judgment signal so that the clock amplification signal finally output by the clock signal amplification module meets the preset duty ratio requirement.

Optionally, the signal type judging module judges the type of the clock signal, specifically:

the clock signal comprises a first clock signal and a second clock signal;

The signal type judging module receives the first clock signal and the second clock signal respectively in different time windows;

if the first clock signal or the second clock signal is a direct current signal, judging that the type of the clock signal is a single-ended clock signal, and outputting a first judgment signal by the signal type judgment module; otherwise, judging the type of the clock signal to be a double-ended clock signal with a phase difference, and outputting a second judgment signal by the signal type judgment module.

Optionally, the signal type decision module includes a first signal selector, a first resistor, a first capacitor, and a comparator;

the first end and the second end of the first signal selector respectively receive the first clock signal and the second clock signal, the third end of the first signal selector is coupled to the first end of the first resistor, the second end of the first resistor is respectively coupled to the first end of the first capacitor and the first input end of the comparator, the second input end of the comparator receives a first reference voltage, and the output end of the comparator is used for outputting a corresponding judgment signal;

wherein the first resistor and the first capacitor are used for filtering.

Optionally, the common mode potential adjustment module includes two common mode potential adjustment units; each common mode potential adjusting unit comprises a pull-up resistor and a pull-down resistor which are connected in series; the output end of the common mode potential adjusting unit is connected with a node between the pull-up resistor and the pull-down resistor;

the common mode potential adjusting unit is used for receiving the first clock signal or the second clock signal, adjusting the resistance values of the pull-up resistor and the pull-down resistor according to the corresponding judgment signals, and outputting corresponding adjusting clock signals;

and adjusting the resistance values of the pull-up resistor and the pull-down resistor to translate the common mode potential of the first clock signal or the common mode potential of the second clock signal.

Optionally, the common mode potential adjustment module translates the common mode potential of the first clock signal and the common mode potential of the second clock signal to a voltage amplitude of 1/2.

Optionally, the first process further includes a termination impedance adjustment process to improve the transmission quality of the clock signal.

Optionally, the clock signal amplifying module includes two amplifying units; each amplifying unit correspondingly receives the adjusting clock signal output by the common mode potential adjusting unit.

Optionally, the second process further includes a disabling process, specifically:

if the signal type judging module outputs a first judging signal, outputting a corresponding single-ended clock amplifying signal only by the amplifying unit which correspondingly receives the single-ended clock signal;

if the signal type judging module outputs a second judging signal, the amplifying unit correspondingly receiving the first clock signal outputs a corresponding first double-end clock amplifying signal, and the amplifying unit correspondingly receiving the second clock signal outputs a corresponding second double-end clock amplifying signal; wherein the first double-ended clock amplified signal and the second double-ended clock amplified signal are combined into a double-ended clock amplified signal having a phase difference.

Optionally, the first processing and the second processing further include duty cycle adjustment, specifically:

the common mode potential adjusting module adjusts the resistance ratio of the pull-up resistor to the pull-down resistor according to the duty ratio judging signal, the duty ratio of the clock signal is adjusted for the first time, the clock signal amplifying module compensates deviation caused by a circuit according to the duty ratio judging signal, and the duty ratio of the adjusting clock signal is adjusted for the second time, so that the clock amplifying signal finally output by the clock signal amplifying module meets the preset duty ratio requirement.

Optionally, the duty cycle decision module outputs the duty cycle decision signal according to the duty cycle information of the clock amplification signal, where the duty cycle decision signal includes a first duty cycle decision signal and a second duty cycle decision signal; the method comprises the following steps:

the duty ratio judgment module outputs the first duty ratio judgment signal only when the duty ratio of the clock amplification signal is 50%; otherwise, outputting the second duty ratio judgment signal, so that the common mode potential adjustment module and the clock signal amplification module respectively adjust the duty ratio of the clock signal and the adjustment clock signal according to the second duty ratio judgment signal.

Optionally, the duty ratio decision module includes a second signal selector, a low-pass filter, an analog-to-digital converter, and a logic unit;

the first end and the second end of the second signal selector respectively receive the first clock amplified signal and the second clock amplified signal, the third end of the second signal selector is coupled to the first end of the low-pass filter, the fourth end of the second signal selector is coupled to the first end of the logic unit, the second end of the low-pass filter is coupled to the first end of the analog-to-digital converter, the second end of the analog-to-digital converter is coupled to the second end of the logic unit, and the third end of the logic unit outputs the duty ratio decision signal.

According to a second aspect of the present invention, there is provided a clock signal receiving apparatus comprising the clock signal receiving circuit provided in any one of the first aspects of the present invention.

According to a third aspect of the present invention, there is provided an electronic device comprising the clock signal receiving apparatus provided in the second aspect of the present invention.

In the clock signal receiving circuit, the clock signal receiving device and the electronic equipment provided by the invention, a clock signal is received through the signal type judging module, the type of the clock signal is judged, and a corresponding judging signal is output; the common mode potential adjustment module performs adaptive first processing on the clock signal according to the judgment signal to output an adjustment clock signal, and the clock signal amplification module performs adaptive second processing on the adjustment clock signal according to the judgment signal to output a clock amplification signal; the duty ratio judgment module extracts the duty ratio information of the clock amplified signal, compares the duty ratio information with a preset duty ratio, and outputs a duty ratio judgment signal to the common mode potential adjustment module and the clock signal amplification module so as to adjust the duty ratio of the clock signal and the clock signal, so that the finally output clock amplified signal meets the requirement of the preset signal common mode potential and the preset signal duty ratio, and the quality of signal transmission is ensured.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a schematic diagram of a clock signal receiving circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of the construction of a signal type decision module in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a common mode potential adjustment module according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a clock signal amplifying module according to an embodiment of the present invention;

fig. 5 is a schematic diagram of the construction of a duty cycle decision module according to an embodiment of the present invention;

reference numerals illustrate:

10-a signal type judging module;

a 20-common mode potential adjustment module;

30-a clock signal amplification module;

a 40-duty cycle decision module;

CLKP 1-a first clock signal;

CLKN 1-a second clock signal;

101-a first signal selector;

102-a comparator;

RFT-first resistance;

CFT-first capacitance;

vcomp-decision signals;

201-a first common mode potential adjustment unit;

202-a second common mode potential adjustment unit;

RTP 1-a first pull-up resistor;

RTN 1-a first pull-down resistor;

RTP 2-a second pull-up resistor;

RTN 2-second pull-down resistor;

KRTP 1-first pull-up decision signal;

KRTN 1-first pull-down decision signal;

KRTP 2-a second pull-up decision signal;

KRTN 2-second pull-down decision signal;

CLKP 2-a first adjusted clock signal;

CLKN 2-a second adjusted clock signal;

VDD-voltage input;

GND-ground;

301-a first amplifying unit;

302-a second amplifying unit;

CLKP 3-first clock amplifying signal;

CLKN 3-a second clock amplified signal;

KBP 1-third pull-up decision signal;

KBN 1-third pull-down decision signal;

KBP 2-fourth pull-up decision signal;

KBN 2-fourth pull-down decision signal;

401-a second signal selector;

402-a low pass filter;

403-analog-to-digital converter;

404-logic unit.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, circuit, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

In view of the fact that in the prior art, a clock signal receiving end device is difficult to receive and process various clock signals, and the quality of signal transmission is guaranteed, the invention provides a clock signal receiving circuit, which receives a clock signal through a signal type judging module, judges the type of the clock signal and outputs a corresponding judging signal; the common mode potential adjustment module performs adaptive first processing on the clock signal according to the judgment signal to output an adjustment clock signal, and the clock signal amplification module performs adaptive second processing on the adjustment clock signal according to the judgment signal to output a clock amplification signal; the duty ratio judgment module extracts the duty ratio information of the clock amplified signal, compares the duty ratio information with a preset duty ratio, and outputs a duty ratio judgment signal to the common mode potential adjustment module and the clock signal amplification module so as to adjust the duty ratio of the clock signal and the clock signal, so that the finally output clock amplified signal meets the requirement of the preset signal common mode potential and the preset signal duty ratio, and the quality of signal transmission is ensured.

Referring to fig. 1, an embodiment of the present invention provides a clock signal receiving circuit, including:

the signal type judging module 10 is used for receiving a clock signal, judging the type of the clock signal and outputting a corresponding judging signal; wherein the types of clock signals include a single-ended clock signal and a double-ended clock signal having a phase difference; the decision signal is used for representing the type of the clock signal;

the common mode potential adjustment module 20 is configured to receive the clock signal and the decision signal, and perform a first process on the clock signal according to a type of the clock signal represented by the decision signal, where the first process is adapted to the type of the clock signal, so as to output an adjusted clock signal; wherein the first process includes at least a common mode potential shift process;

the clock signal amplifying module 30 is configured to receive the decision signal and the adjustment clock signal, perform a second process on the adjustment clock signal according to the type of the clock signal represented by the decision signal, and output a clock amplified signal; wherein the second process includes at least an amplification process;

The duty ratio decision module 40 is configured to receive the clock amplification signal, extract duty ratio information of the clock amplification signal, compare the extracted duty ratio information with a preset duty ratio, and output a duty ratio decision signal to the common mode potential adjustment module 20 and the clock signal amplification module 30, where the common mode potential adjustment module 20 and the clock signal amplification module 30 respectively adjust duty ratios of the clock signal and the adjusted clock signal according to the duty ratio decision signal, so that the clock amplification signal finally output by the clock signal amplification module 30 meets a preset duty ratio requirement.

In one embodiment, the signal type determining module 10 determines the type of the clock signal, specifically:

the clock signal includes a first clock signal CLKP1 and a second clock signal CLKN1;

the signal type decision module 10 receives the first clock signal CLKP1 and the second clock signal CLKN1 at different time windows, respectively;

if the first clock signal CLKP1 or the second clock signal CLKN1 is a dc signal, determining that the type of the clock signal is a single-ended clock signal, and the signal type determining module 10 outputs a first determination signal; otherwise, the type of the clock signal is judged to be a double-ended clock signal with a phase difference, and the signal type judgment module 10 outputs a second judgment signal.

Specifically, referring to fig. 2, the signal type determining module 10 includes a first signal selector 101, a first resistor RFT, a first capacitor CFT, and a comparator 102;

the first end and the second end of the first signal selector 101 respectively receive the first clock signal CLKP1 and the second clock signal CLKN1, a third end thereof is coupled to the first end of the first resistor RFT, a second end thereof is coupled to the first end of the first capacitor CFT and the first input end of the comparator 102 respectively, and a second input end of the comparator 102 receives a first reference voltage VREF1, and an output end thereof is used for outputting a corresponding decision signal;

wherein the first resistor RFT and the first capacitor CFT are used for filtering.

In the example shown in fig. 2, since the first signal selector 101 can only accept one clock signal at the same time, the first signal selector 101 receives the first clock signal CLKP1 and the second clock signal CLKN1 respectively in different time windows, wherein the time length of the time window includes several periods of the clock signal. Since the first resistor RFT and the first capacitor CFT form a low-pass filter circuit, the first clock signal CLKP1 or the second clock signal CLKN1 is a direct current (unchanged) signal after passing through the low-pass filter circuit, and the direct current signal is a common mode level of the first clock signal CLKP1 or the second clock signal CLKN 1. The common mode level of the first clock signal CLKP1 or the second clock signal CLKN1 is fed into the first input end of the comparator 102, and the comparator 102 compares the common mode level with the first reference voltage VREF1, and the comparison result is the corresponding decision signal Vcomp.

In this case, the output terminal of the comparator 102 is used as the output terminal of the signal type decision module 10, and is configured to output a corresponding decision signal Vcomp, specifically:

if the clock signal is a single-ended clock signal, the voltage of the second end of the first resistor RFT is lower than the first reference voltage VREF1, and the output end of the comparator 102 outputs a high level;

if the clock signal is a double-ended clock signal with a phase difference, the voltage of the second end of the first resistor RFT is higher than the first reference voltage VREF1, and the output end of the comparator 102 outputs a low level.

In one embodiment, referring to fig. 3, the common mode voltage adjustment module 20 includes two common mode voltage adjustment units; each common mode potential adjusting unit comprises a pull-up resistor and a pull-down resistor which are connected in series; the output end of the common mode potential adjusting unit is connected with a node between the pull-up resistor and the pull-down resistor;

the common mode potential adjusting unit is configured to receive the first clock signal CLKP1 or the second clock signal CLKN1, adjust resistance values of the pull-up resistor and the pull-down resistor according to a corresponding decision signal Vcomp, and output a corresponding adjusting clock signal;

The resistance values of the pull-up resistor and the pull-down resistor are adjusted to shift the common mode potential of the first clock signal CLKP1 or the common mode potential of the second clock signal CLKN 1.

Meanwhile, the pull-up resistor and the pull-down resistor which are connected in series can also inhibit signal overshoot, false triggering of signal level can not be caused, and when no signal exists on the circuit, a direct current level can be provided for the circuit, so that the bus application is suitable.

In a preferred embodiment, the common mode potential adjustment module 20 translates the common mode potential of the first clock signal CLKP1 and the common mode potential of the second clock signal CLKN1 to a 1/2 voltage amplitude.

In a specific embodiment, referring to fig. 3, the two common mode potential adjusting units are a first common mode potential adjusting unit 201 and a second common mode potential adjusting unit 202, and the common mode potential adjusting module 20 will be further described by taking the first common mode potential adjusting unit 201 as an example:

the first common-mode voltage adjusting unit 201 includes a first pull-up resistor RTP1 and a first pull-down resistor RTN1;

the first end of the first pull-up resistor RTP1 is coupled to the voltage input end VDD, and the second end of the first pull-up resistor RTP1 is coupled to the first end of the first pull-down resistor RTN1;

In an example, the node between the first pull-up resistor RTP1 and the first pull-down resistor RTN1 receives the first clock signal CLKP1, and the common mode potential of the first clock signal CLKP1 translates to a preset signal common mode potential after being regulated by the first pull-up resistor RTP1 and the first pull-down resistor RTN 1.

The pull-up resistor and the pull-down resistor form a termination resistor, and reflection is absorbed by the pull-up resistor and the pull-down resistor, so that signal transmission effect is improved, and in a preferred embodiment, the first process further includes a termination impedance adjustment process to improve transmission quality of the clock signal. Specifically, when the resistance values of the pull-up resistor and the pull-down resistor satisfy the following relationship with the characteristic impedance of the transmission line, the impedance of the circuit can be regarded as being matched:

wherein, R1 is the resistance of the pull-up resistor in the common mode potential adjusting unit, R2 is the resistance of the pull-down resistor in the common mode potential adjusting unit, zo is the equivalent resistance of the characteristic impedance of the corresponding transmission line.

The clock signal amplifying module 30 performs a second process of adapting the adjusted clock signal shifted to a preset signal common mode potential, where the adjusted clock signal includes a first adjusted clock signal CLKP2 and a second adjusted clock signal CLKN2;

In one embodiment, referring to fig. 4, the clock signal amplifying module 30 includes two amplifying units; each amplifying unit correspondingly receives the adjusting clock signal output by the common mode potential adjusting unit, wherein the two amplifying units form an inverting amplifier in order to reduce the influence caused by standing waves and improve the anti-interference capability in the signal propagation process.

In the example shown in fig. 4, the clock signal amplifying module 30 includes a first amplifying unit 301 and a second amplifying unit 302.

In one example, the first amplifying unit 301 corresponds to a first adjustment clock signal CLKP2 output by a common mode voltage adjusting unit, and the second amplifying unit 302 corresponds to a second adjustment clock signal CLKN2 output by another common mode voltage adjusting unit.

In this case, the first amplifying unit 301 will be further described by taking the amplifying unit as an example:

in an embodiment, referring to fig. 4, the first amplifying unit 301 includes a first adjustable resistor RP1, a second adjustable resistor RN1, a first feedback resistor RFB1, a first transmission gate TG1, a second transmission gate TG2, a first CMOS amplifying tube M1, a second CMOS amplifying tube M2, a third CMOS amplifying tube M3, and a fourth CMOS amplifying tube M4; wherein the first CMOS amplifying transistor M1 and the third CMOS amplifying transistor M3 are PMOS transistors, and the second CMOS amplifying transistor M2 and the fourth CMOS amplifying transistor M4 are NMOS transistors;

The input ends of the first transmission gate TG1 and the second transmission gate TG2 respectively receive the first adjustment clock signal CLKP2, the output end of the second transmission gate TG2 is coupled to the first end of the second adjustment resistor, the positive control end and the negative control end of the first transmission gate TG1 respectively receive the first positive signal TGP1 and the first inversion signal TGN1, and the positive control end and the negative control end of the second transmission gate TG2 respectively receive the second positive signal TGP2 and the second inversion signal TGN2;

the first end of the first adjustable resistor RP1 is coupled to the voltage input end VDD, the second end thereof is respectively coupled to the output end of the first transmission gate TG1, the source of the first CMOS amplifier M1 and the source of the third CMOS amplifier M3, the gate of the first CMOS amplifier M1 is coupled to the first end of the first feedback resistor RFB1, the first end of the first feedback resistor RFB1 is further coupled to the gate of the second CMOS amplifier M2, the drain of the second CMOS amplifier M2 is coupled to the drain of the first CMOS amplifier M1, the source of the second CMOS amplifier M2 is coupled to the first end of the second adjustable resistor RN1, and the second end of the second adjustable resistor RN1 is grounded;

The gate of the third CMOS amplifier M3 and the gate of the fourth CMOS amplifier M4 respectively receive a fixed level bias signal Vb, the drain of the third CMOS amplifier M3 is coupled to the drain of the fourth CMOS amplifier M4, the source of the fourth CMOS amplifier M4 is coupled to the first end of the second adjustable resistor RN1, and the second end of the first feedback resistor RFB1 is sequentially coupled to a node between the drain of the second CMOS amplifier M2 and the drain of the first CMOS amplifier M1, and a node between the drain of the third CMOS amplifier M3 and the drain of the fourth CMOS amplifier M4;

the node between the drain of the third CMOS amplifier M3 and the drain of the fourth CMOS amplifier M4 is configured to output a first clock amplified signal CLKN3, where the first clock amplified signal CLKN3 and the first adjustment clock signal CLKP2 are opposite signals;

the first positive phase signal TGP1 and the first inversion signal TGN1 are opposite signals, and are used for controlling signal transmission of the first transmission gate TG1, and the second positive phase signal TGP2 and the second inversion signal TGN2 are opposite signals, and are used for controlling signal transmission of the second transmission gate TG 2; the inverted signal is understood to mean that the phase difference between the two signals is 180 °, and when one of the signals is at a high level, the other signal is at a low level.

The working principle of the amplifying unit is specifically described as follows:

in the first amplifying unit 301, the first transmission gate TG1 and the second transmission gate TG2 are responsible for transmitting the first adjustment clock signal CLKP2 to the source of the first CMOS amplifying transistor M1, the source of the second CMOS amplifying transistor M2, the source of the third CMOS amplifying transistor M3 and the source of the fourth CMOS amplifying transistor M4 for amplifying; the third CMOS amplifying tube M3 and the fourth CMOS amplifying tube M4 form a source amplifier, and the first CMOS amplifying tube M1, the second CMOS amplifying tube M2 and the first feedback resistor RFB1 form a feedback unit;

further, the first feedback resistor RFB1 may react the output variation of the first clock amplification signal CLKN3 to the drain and gate potentials of the first CMOS amplification tube M1 and the drain and gate potentials of the second CMOS amplification tube M2, so that the variation of the first clock amplification signal CLKN3 is faster, for example, at the moment when the first clock amplification signal CLKN3 becomes high, the drain and gate voltages of the first CMOS amplification tube M1 become high, and the current flowing through the first CMOS amplification tube M1 becomes rapidly small; meanwhile, the drain voltage of the third CMOS amplifying tube M3 becomes high, the gate voltage of the third CMOS amplifying tube M3 is unchanged, and the current flowing through the third CMOS amplifying tube M3 becomes large; on this basis, if the third CMOS amplifier M3 has a large tube size, the current increased by the third CMOS amplifier M3 is larger than the current decreased by the first CMOS amplifier M1, the charging current to the node between the drain of the third CMOS amplifier M3 and the drain of the fourth CMOS amplifier M4 is larger, and the level of the output first clock amplified signal CLKN3 is accelerated.

Similarly, referring to fig. 4, the second amplifying unit 302 includes a third adjustable resistor RP2, a fourth adjustable resistor RN2, a second feedback resistor RFB2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth CMOS amplifying tube M5, a sixth CMOS amplifying tube M6, a seventh CMOS amplifying tube M7, and an eighth CMOS amplifying tube M8; wherein the fifth CMOS amplifying transistor and the seventh CMOS amplifying transistor M7 are PMOS transistors, and the sixth CMOS amplifying transistor M6 and the eighth CMOS amplifying transistor M8 are NMOS transistors; since the circuit connection relationship between the first amplifying unit 301 and the second amplifying unit 302 is the same, the connection relationship between the devices in the second amplifying unit 302 is not repeated in the present invention.

In a preferred embodiment, referring to fig. 4, the positive control terminal and the negative control terminal of the third transmission gate TG3 respectively receive the first positive phase signal TGP1 and the first inverse signal TGN1, and the positive control terminal and the negative control terminal of the fourth transmission gate TG4 respectively receive the second positive phase signal TGP2 and the second inverse signal TGN2; the first transmission gate TG1 and the third transmission gate TG3 are simultaneously turned on, the second transmission gate TG2 and the fourth transmission gate TG4 are simultaneously turned off, or the second transmission gate TG2 and the fourth transmission gate TG4 are simultaneously turned on, and the first transmission gate TG1 and the third transmission gate TG3 are simultaneously turned off.

In order to facilitate the subsequent circuit processing of different clock signals, in a preferred embodiment, the second processing further comprises disabling processing, in particular:

if the signal type decision module 10 outputs a first decision signal, only outputting a corresponding single-ended clock amplified signal by the amplifying unit corresponding to the single-ended clock signal;

if the signal type decision module 10 outputs a second decision signal, the amplifying unit correspondingly receiving the first clock signal CLKP1 outputs a corresponding first double-ended clock amplified signal, and the amplifying unit correspondingly receiving the second clock signal CLKN1 outputs a corresponding second double-ended clock amplified signal; wherein the first double-ended clock amplified signal and the second double-ended clock amplified signal are combined into a double-ended clock amplified signal having a phase difference.

In a specific example, referring to fig. 4, if the second amplifying unit 302 receives the dc signal, the resistance value of the third adjustable resistor RP2 is controlled to be the maximum, so that the second amplifying unit 302 stops outputting the corresponding clock amplifying signal.

However, shifting the common mode potential of the first clock signal CLKP1 or the common mode potential of the second clock signal CLKN1 affects the operating state of the clock signal amplified signal, thereby affecting the duty cycle of the clock signal amplified signal output clock. In order to make the finally output clock amplified signal meet both the requirement of the preset signal common mode potential and the requirement of the preset signal duty ratio, in one embodiment, the first processing and the second processing further include duty ratio adjustment, specifically:

The common mode potential adjusting module 20 adjusts the resistance ratio of the pull-up resistor to the pull-down resistor according to the duty ratio decision signal, and adjusts the duty ratio of the clock signal for the first time, the clock signal amplifying module 30 compensates the deviation caused by the circuit according to the duty ratio decision signal, and adjusts the duty ratio of the adjusted clock signal for the second time, so that the clock amplifying signal finally output by the clock signal amplifying module 30 meets the preset duty ratio requirement.

On the basis, in one embodiment, the duty cycle decision module 40 outputs the duty cycle decision signal according to the duty cycle information of the clock amplification signal, where the duty cycle decision signal includes a first duty cycle decision signal and a second duty cycle decision signal; the method comprises the following steps:

the duty cycle decision module 40 outputs the first duty cycle decision signal only when the clock amplified signal duty cycle is 50%; otherwise, the second duty ratio decision signal is output, so that the common mode potential adjusting module 20 and the clock signal amplifying module 30 respectively adjust the duty ratios of the clock signal and the adjusted clock signal according to the second duty ratio decision signal.

In an example, referring to fig. 5, the duty ratio decision module 40 includes a second signal selector 401, a low-pass filter 402, an analog-to-digital converter 403, and a logic unit 404;

the first end and the second end of the second signal selector 401 respectively receive the first clock amplified signal CLKN3 and the second clock amplified signal CLKP3, the third end of the second signal selector 401 is coupled to the first end of the low-pass filter 402, the fourth end thereof is coupled to the first end of the logic unit 404, the second end of the low-pass filter 402 is coupled to the first end of the analog-to-digital converter 403, the second end of the analog-to-digital converter 403 is coupled to the second end of the logic unit 404, and the third end of the logic unit 404 outputs the duty ratio decision signal.

In the example shown in fig. 5, the second signal selector 401 may accept only one clock signal at a time, the first clock amplified signal CLKN3 and the second clock amplified signal CLKP3 are input to the second signal selector 401 in the form of double-ended signals having a phase difference, and the second signal selector 401 receives the first clock amplified signal CLKN3 of several cycles or the second clock amplified signal CLKP3 of several cycles for a period of time, wherein the first clock amplified signal CLKN3 and the second clock amplified signal CLKP3 may be combined into the double-ended clock amplified signal or the single-ended clock amplified signal having a phase difference.

In this case, the second signal selector 401 inputs the first clock amplified signal CLKN3 and the second clock amplified signal CLKP3 into the low-pass filter 402 to filter out noise, and the first clock amplified signal CLKN3 and the second clock amplified signal CLKP3 at this time correspond to a direct current signal that includes the duty ratio information of the first clock amplified signal CLKN3 or the duty ratio information of the second clock amplified signal CLKP3, and the analog-to-digital converter 403 converts the duty ratio information of the first clock amplified signal CLKN3 or the duty ratio information of the second clock amplified signal CLKP3 into digital information and sends the digital information to the logic unit 404 for processing. The logic unit 404 outputs a corresponding duty cycle decision signal according to the duty cycle information.

The control of the circuits shown in fig. 3 and 4 will now be further described with the duty cycle decision module 40:

in an example, referring to fig. 3, the duty ratio decision signal output by the logic unit 404 includes a first pull-up decision signal KRTP1, a first pull-down decision signal KRTP1, a second pull-up decision signal KRTP2, and a second pull-down decision signal KRTN2, so as to control the common mode potential adjustment module 20 shown in fig. 3, and respectively adjust the resistance ratio of the first pull-up resistor RTP1 to the first pull-down resistor RTN1 and the resistance ratio of the second pull-up resistor RTP2 to the second pull-down resistor RTN 2. In an ideal state, at this time, the duty ratio of the adjusted clock signal should meet a preset duty ratio requirement.

However, in an actual circuit, in the process of amplifying the first adjustment clock signal CLKP2 and the second adjustment clock signal CLKN2 by the clock signal amplifying module 30, a duty cycle deviation is generated, and in a preferred embodiment, please refer to fig. 4, the logic unit 404 further outputs a third pull-up decision signal KRP1, a third pull-down decision signal KRN1, a fourth pull-up decision signal KRP2, and a fourth pull-down decision signal KRN2, which are used for controlling the resistance ratio of the first adjustable resistor RP1 to the second adjustable resistor RN1 and the resistance ratio of the third adjustable resistor RP2 to the fourth adjustable resistor RN2, so as to compensate the deviation caused by the circuit in the clock signal amplifying module 30, thereby performing the second adjustment on the duty cycle of the adjustment clock signal.

Specifically, in one adjustment mode, when power is turned on, the resistance value of the first pull-up resistor RTP1 and the resistance value of the first pull-down resistor RTN1 may be the same, and then whether to adjust the duty ratio of the clock signal and the adjustment clock signal is determined according to the duty ratio decision signal output by the duty ratio decision module 40;

only when the duty ratio of the first clock amplification signal CLKN3 or the duty ratio of the second clock amplification signal CLKP3 is 50%, the logic unit 404 outputs a first duty ratio decision signal to the common mode potential adjustment module 20 and the clock signal amplification module 30, and stops adjusting the resistance value of the internal resistor of each module, otherwise, the logic unit 404 outputs a second duty ratio decision signal to the common mode potential adjustment module 20 and the clock signal amplification module 30, so that the common mode potential adjustment module 20 and the clock signal amplification module 30 respectively adjust the duty ratio of the clock signal and the duty ratio of the adjusted clock signal according to the second duty ratio decision signal, thereby ensuring that the clock amplification signal finally output by the clock signal amplification module 30 meets the preset duty ratio requirement.

In addition, the embodiment of the invention also provides a clock signal receiving device which comprises the clock signal receiving circuit. By way of example, the clock signal receiving apparatus may be used for high-speed parallel interfaces including uci interfaces, boW interfaces, AIB interfaces, and the like.

In addition, the embodiment of the invention also provides electronic equipment which comprises the clock signal receiving device. By way of example, the device may be a DDR interface, an HBM interface, etc., and may be used in other devices and systems that require high speed data exchange.

In summary, in the clock signal receiving circuit, the clock signal receiving device and the electronic device provided by the invention, a clock signal is received through the signal type judging module, the type of the clock signal is judged, and a corresponding judging signal is output; the common mode potential adjustment module performs adaptive first processing on the clock signal according to the judgment signal to output an adjustment clock signal, and the clock signal amplification module performs adaptive second processing on the adjustment clock signal according to the judgment signal to output a clock amplification signal; the duty ratio judgment module extracts the duty ratio information of the clock amplified signal, compares the duty ratio information with a preset duty ratio, and outputs a duty ratio judgment signal to the common mode potential adjustment module and the clock signal amplification module so as to adjust the duty ratio of the clock signal and the clock signal, so that the finally output clock amplified signal meets the requirement of the preset signal common mode potential and the preset signal duty ratio, and the quality of signal transmission is ensured.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A clock signal receiving circuit, comprising:

2. The clock signal receiving circuit according to claim 1, wherein the signal type determining module determines the type of the clock signal, specifically:

The clock signal comprises a first clock signal and a second clock signal;

3. The clock signal receiving circuit of claim 2, wherein the signal type decision module comprises a first signal selector, a first resistor, a first capacitor, and a comparator;

Wherein the first resistor and the first capacitor are used for filtering.

4. The clock signal receiving circuit according to claim 2, wherein the common mode potential adjustment module includes two common mode potential adjustment units; each common mode potential adjusting unit comprises a pull-up resistor and a pull-down resistor which are connected in series; the output end of the common mode potential adjusting unit is connected with a node between the pull-up resistor and the pull-down resistor;

5. The clock signal receiving circuit of claim 4, wherein the common mode potential adjustment module translates the common mode potential of the first clock signal and the common mode potential of the second clock signal to a 1/2 voltage magnitude.

6. The clock signal receiving circuit of claim 4, wherein the first process further comprises a termination impedance adjustment process to improve the transmission quality of the clock signal.

7. The clock signal receiving circuit of claim 4, wherein the clock signal amplifying module comprises two amplifying units; each amplifying unit correspondingly receives the adjusting clock signal output by the common mode potential adjusting unit.

8. The clock signal receiving circuit of claim 7, wherein the second process further comprises a disabling process, in particular:

9. The clock signal receiving circuit according to any one of claims 4 to 8, wherein the first and second processing further comprises duty cycle adjustment, in particular:

10. The clock signal receiving circuit of claim 9, wherein the duty cycle decision module outputs the duty cycle decision signal according to duty cycle information of the clock amplified signal, the duty cycle decision signal comprising a first duty cycle decision signal and a second duty cycle decision signal; the method comprises the following steps:

11. The clock signal receiving circuit of claim 10, wherein the duty cycle decision module comprises a second signal selector, a low pass filter, an analog to digital converter, and a logic unit;

12. A clock signal receiving apparatus comprising a clock signal receiving circuit as claimed in any one of claims 1 to 11.

13. An electronic device comprising the clock signal receiving apparatus of claim 12.