CN116150069A - Data processing method, device, equipment and storage medium - Google Patents

Data processing method, device, equipment and storage medium Download PDF

Info

Publication number
CN116150069A
CN116150069A CN202310175423.6A CN202310175423A CN116150069A CN 116150069 A CN116150069 A CN 116150069A CN 202310175423 A CN202310175423 A CN 202310175423A CN 116150069 A CN116150069 A CN 116150069A
Authority
CN
China
Prior art keywords
circuit
branch
universal serial
serial bus
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310175423.6A
Other languages
Chinese (zh)
Inventor
何彩婷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Fibocom Wireless Software Inc
Original Assignee
Xian Fibocom Wireless Software Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Fibocom Wireless Software Inc filed Critical Xian Fibocom Wireless Software Inc
Priority to CN202310175423.6A priority Critical patent/CN116150069A/en
Publication of CN116150069A publication Critical patent/CN116150069A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application discloses a data processing method, a device, equipment and a storage medium, wherein the method comprises the following steps: acquiring a switch connection position of a variable switch in a target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series; if the switch connection position indicates that the variable switch is connected to the first branch, starting the first universal serial bus circuit to perform data transmission; if the switch connection position indicates that the variable switch is connected to the second branch, based on the connection instruction, a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit is started to transmit data. By adopting the embodiment of the application, the universality of the circuit and the flexibility of circuit switching can be improved, and the testing efficiency is improved.

Description

Data processing method, device, equipment and storage medium
Technical Field
The present disclosure relates to the field of artificial intelligence technologies, and in particular, to a data processing method, apparatus, device, and storage medium.
Background
Currently, with the popularization of internet technology, electronic devices need to transmit data through different types of circuits, but the wiring accessories needed by the different types of circuits for data transmission are different, and the interfaces and the data lines used by the different types of circuits are inconsistent, so that the different circuits are independent from each other, and separate communication circuits need to be deployed for the different types of circuits. When the electronic equipment is communicated, a required communication circuit is required to be deployed, and the electronic equipment is connected to the communication circuit, so that the circuit required to be maintained is complex, occupies a large space and is not maintained, and the circuit is required to be deployed every time, so that the data transmission efficiency is low. And when using different circuits, need to carry out the access to the electronic equipment based on the demand and connect out, lead to the circuit to use comparatively loaded down with trivial details, circuit availability factor is low.
Disclosure of Invention
The embodiment of the application provides a data processing method, a device, equipment and a storage medium, which can improve the universality of a circuit and the flexibility of circuit switching and improve the testing efficiency.
An aspect of an embodiment of the present application provides a data processing method, which is characterized in that the method includes:
Acquiring a switch connection position of a variable switch in a target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series;
if the switch connection position indicates that the variable switch is connected to the first branch, starting the first universal serial bus circuit to perform data transmission;
if the switch connection position indicates that the variable switch is connected to the second branch, based on the connection instruction, a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit is started to transmit data.
An aspect of an embodiment of the present application provides a data processing system, including:
the system comprises a variable switch, a target circuit and upper computer equipment; the target circuit comprises a first branch and a second branch, and the first branch is connected with the second branch in parallel; the first branch comprises a first universal serial bus circuit, the second branch comprises a second universal serial bus circuit and an asynchronous receiving and transmitting transmission circuit, and the second universal serial bus circuit is connected with the asynchronous receiving and transmitting transmission circuit in series;
The variable switch is used for starting the first universal serial bus circuit to transmit data when being connected to the first branch circuit;
the variable switch is also used for starting a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting transmission circuit to transmit data based on a connection instruction when the variable switch is connected to the second branch circuit;
the upper computer equipment is connected to the target circuit through the circuit interface and used for generating a connection instruction.
An aspect of an embodiment of the present application provides a data processing apparatus, including:
the position acquisition module is used for acquiring the switch connection position of the variable switch in the target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series;
the first data transmission module is used for starting the first universal serial bus circuit to perform data transmission if the switch connection position indicates that the variable switch is connected to the first branch circuit;
and the second data transmission module is used for starting a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit based on the connection instruction to perform data transmission if the connection position of the switch indicates that the variable switch is connected to the second branch circuit.
Wherein the second data transmission module comprises:
the instruction acquisition unit is used for acquiring a connection instruction if the switch connection position indicates that the variable switch is connected to the second branch circuit;
the first data transmission unit is used for determining a second universal serial bus circuit in the second branch circuit as a communication circuit if the connection instruction is a first connection instruction, starting the communication circuit and carrying out data transmission;
and the second data transmission unit is used for determining the asynchronous receiving and transmitting transmission circuit in the second branch circuit as a connected circuit if the connection instruction is the second connection instruction, starting the connected circuit and carrying out data transmission.
Wherein, the data processing device still includes:
the connection module is used for connecting the equipment to be tested with the upper computer equipment through the target circuit; the upper computer equipment is connected to the target circuit through a circuit interface;
and the test module is used for running a test script based on the target circuit and automatically testing the equipment to be tested and the upper computer equipment.
Wherein, the data processing device still includes:
the updating module is used for switching the communication circuit in the second branch circuit based on the updated connection instruction if the updating of the connection instruction is detected; the updated communication circuit refers to an updated connection instruction, and the updated connection instruction is indicated in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit;
And the third data transmission module is used for starting the updated connected circuit to perform data transmission.
Wherein, the data processing device still includes:
the first result acquisition module is used for acquiring a first test result generated when the first universal serial bus circuit is started to transmit data of the equipment to be tested;
the second result acquisition module is used for acquiring a second test result generated when the second universal serial bus circuit is started to transmit data based on the connection instruction;
and the result integration module is used for integrating the first test result and the second test result to determine a target test result of the equipment to be tested.
Wherein, the data processing device still includes:
the parameter acquisition module is used for acquiring the test configuration parameters associated with the equipment to be tested and transmitting the test configuration parameters to the upper computer equipment; the test configuration parameters are used for indicating the circuit types associated with the equipment to be tested;
and the instruction transmission module is used for generating a connection instruction based on the test configuration parameters in the upper computer equipment and transmitting the connection instruction to the target circuit through the circuit interface.
An aspect of an embodiment of the present application provides a data processing apparatus, including:
The system comprises a constitution module, a control module and a control module, wherein the constitution module is used for expressing that the system comprises a variable switch, a target circuit and upper computer equipment; the target circuit comprises a first branch and a second branch, and the first branch is connected with the second branch in parallel; the first branch comprises a first universal serial bus circuit, the second branch comprises a second universal serial bus circuit and an asynchronous receiving and transmitting transmission circuit, and the second universal serial bus circuit is connected with the asynchronous receiving and transmitting transmission circuit in series;
the switch module is used for expressing the variable switch and is used for starting the first universal serial bus circuit to transmit data when being connected to the first branch circuit;
the switch module is also used for expressing the variable switch and starting a communication circuit in the second universal serial bus circuit and the asynchronous transceiving transmission circuit to transmit data based on a connection instruction when the switch module is connected to the second branch circuit;
the upper computer module is used for expressing upper computer equipment, is connected to the target circuit through the circuit interface and is used for generating a connection instruction.
In one aspect, the present application provides a computer device comprising: a processor, a memory, a network interface;
the processor is connected to the memory and the network interface, where the network interface is used to provide a data communication function, the memory is used to store a computer program, and the processor is used to call the computer program to make the computer device execute the method in the embodiment of the present application.
In one aspect, embodiments of the present application provide a computer readable storage medium having a computer program stored therein, the computer program being adapted to be loaded by a processor and to perform a method according to embodiments of the present application.
In one aspect, embodiments of the present application provide a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium; the processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the methods in the embodiments of the present application.
In the embodiment of the application, the computer device may obtain the switch connection position of the variable switch in the target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series; if the switch connection position indicates that the variable switch is connected to the first branch, starting the first universal serial bus circuit to perform data transmission; if the switch connection position indicates that the variable switch is connected to the second branch, based on the connection instruction, a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit is started to transmit data. According to the embodiment of the application, the first branch circuit and the second branch circuit are connected in parallel, so that different types of circuits at a hardware level are fused. Further, by connecting the second universal serial bus circuit in series with the asynchronous transceiving transmission circuit, the second universal serial bus circuit and the asynchronous transceiving transmission circuit can be selected, and further, the data transmission using different circuits can be controlled. The second universal serial bus circuit and the asynchronous receiving and transmitting circuit are connected in series to one circuit, so that the universality of the circuit and the flexibility of circuit switching can be improved, the time for circuit switching is saved, the flow of circuit switching is greatly reduced, and the testing efficiency is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a system architecture according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another system architecture provided in an embodiment of the present application;
FIG. 3 is a schematic flow chart of a data processing method according to an embodiment of the present application;
FIG. 4 is a schematic flow chart of one possible connection instruction detection provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a circuit switching system according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a system architecture according to an embodiment of the present application. As shown in fig. 1, the method of the embodiment of the present application is illustrated as being performed by a computer device, which may include a target circuit. Optionally, the computer device may include a target circuit, and may further include a circuit control module. The circuit control module is used for controlling circuit selection in the target circuit. For ease of understanding, the system of the embodiments of the present application may include a host device Z11, a target circuit Z12, a variable switch, and a device under test. In the case of using the system, the upper computer device Z11 can perform data transmission with a device to be tested (such as an integrated chip, an integrated module, or an integrated device). Specifically, the upper computer device Z11 may be further connected to the target circuit Z12 by connecting to a circuit interface in the target circuit Z12, and may be connected to a device to be tested by the target circuit Z12. Specifically, the target circuit Z12 may include a circuit interface, a first branch Z13, and a second branch Z14. The variable switch can be connected with the first branch or the second branch according to the requirement of a user. The circuit interface may refer to an interface for accessing other devices to the target circuit. In particular, the circuit interface may be used to manage the data type of the transport protocol defined at the software level. Further, the first branch and the second branch in the target circuit may be in an alternative relationship, and the variable switch may be used to switch between the first branch and the second branch.
Referring to fig. 2, fig. 2 is a schematic diagram of another system architecture according to an embodiment of the present application. As shown in fig. 2, the method according to the embodiment of the present application is illustrated by a computer device, and the system may include a host device Z21 and a target circuit Z22. The target circuit Z22 includes a first branch Z23 and a second branch Z24.
Alternatively, the device to be tested may be the same device as the host computer device, as shown in fig. 2, or may be a different device, as shown in fig. 1. The target circuit in fig. 1 and fig. 2 only shows some of the electrical devices referred to in the application, and in actual circuit components, the target circuit may further include other electrical devices, such as electrical wires, a power source, and electrical resistors, to achieve communication between the target circuits, which are not described herein.
Further, referring to fig. 3, fig. 3 is a flow chart of a data processing method according to an embodiment of the present application. As shown in fig. 3, the method may be performed by a computer device, and the data processing method may include at least the following steps S101 to S103:
step S101, obtaining a switch connection position of a variable switch in a target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting circuit in series.
Specifically, the computer device may obtain a current usage state of the variable switch, where the current usage state is determined according to whether the variable switch is connected in the target circuit, and the usage state may include a closed state and an open state. Specifically, when the current use state of the variable switch is the closed state, it means that the variable switch is connected in the target circuit, that is, the current in the target circuit flows through the variable switch; accordingly, when the current use state of the variable switch is the off state, it means that the variable switch is not connected in the target circuit, that is, the current of the target circuit does not flow through the variable switch. Further, the closed state may include a first open state and a second open state. If the current use state of the variable switch is a first opening and closing state, the connection position of the switch of the variable switch is a first branch; correspondingly, if the current use state of the variable switch is the second open-close state, the switch connection position of the variable switch is indicated to be the second branch. Specifically, the first open-close state of the variable switch may be when the dual switch is turned on to the circuit below (i.e., the first branch) as shown in fig. 1. The variable switch refers to a switch capable of changing the direction of a circuit through physical structure change. In particular, in one particular embodiment, the variable switch may comprise a dual switch. Wherein, the double switch refers to a switch which can directly select two circuits.
If the switch connection position of the variable switch is the first branch, the computer device selects the first branch to perform data transmission, that is, uses the first universal serial bus circuit to perform data transmission. The first universal serial bus circuit is a circuit for data transmission using a universal serial bus (Universal Serial Bus, USB). Specifically, the universal serial bus refers to an external bus standard for standardizing the connection and communication between a computer device and an external device. In other words, a universal serial bus may be understood as an interface technology applied in the field of computer devices. Specifically, the USB uses four-wire cables, two of which are serial channels for transmitting data, and the other two of which provide power for the device under test, and for any peripherals that have been successfully connected and mutually identified, the data will be transmitted at the highest rate that both devices can support. Wherein, USB will be automatically switched from high speed to low speed dynamically and match and lock at proper rate in compatible transmission mode according to peripheral conditions. Specifically, the USB adopts a cascade star topology, which consists of three basic parts: a Host (Host), a Hub (Hub) and a functional device to which the USB is connected. In an embodiment of the present application, the functional device may include a device under test.
Further, the main controller included in the USB is responsible for the transmission of data streams between the host in the topology and the functional devices to which the USB is connected. Wherein these transmitted data streams may be continuous bit streams. Each of the function devices provides one or more circuit interfaces that can communicate with the client program, each circuit interface being composed of at least one pipe that can independently transfer data between the host computer device and the function device to which the USB is connected, respectively. Among other possible USB circuit interface structures, the USB circuit interface may include a transmit signal line (TX signal line), a receive signal line (RX signal line), and other signal lines (e.g., ground line).
USB supports four basic data transfer modes: control transmission, isochronous transmission, interrupt transmission and data block transmission. The specific data transmission modes are as follows:
(1) control transmission: the data transmission mode may be used to transmit information such as control information, status information, configuration information, etc. between the host of the USB and the functional device of the USB, and in short, the data transmission mode may be understood as a control channel established between the host of the USB and the functional device of the USB.
(2) Isochronous (or synchronous) transmissions: the data transmission mode can be used for periodic data transmission processing, and particularly, the data transmission mode can be used for data transmission with unchanged data transmission rate when the transmission time delay between a host of the USB and functional equipment of the USB is larger than the specified time delay and the transmission bandwidth is smaller than the specified bandwidth. The specified time delay and the specified bandwidth can be the conventional time delay and the conventional bandwidth of the data transmission industry. For example, the data transfer mode may be used for data transfer between a telephone integration system (CTI) of a computer and a host of a USB, or the data transfer mode may be used for data transfer between an audio system of a computer and a host of a USB.
(3) Interrupt transmission: in particular, the data transmission mode can be used for data transmission between input devices such as a game pad, a computer mouse, a computer keyboard and the like and a host of the USB. When data transmission is carried out between input equipment such as a game handle, a computer mouse, a computer keyboard and the like and a host computer of the USB, the data magnitude of the data transmission is small, the data transmission process is not periodic, and the response time of the data transmission is sensitive.
(4) Data block (Bulk) transmission: the data transmission mode can be used for functional equipment connected with USB (universal serial bus) such as printers, scanners, digital cameras and the like, the data magnitude of data transmission between the functional equipment connected with the USB and a host computer of the USB is large, and the USB can perform the data transmission under the condition of meeting the bandwidth.
Correspondingly, if the switch connection position of the variable switch is the second branch, the computer device selects the second branch to perform data transmission, that is, uses a circuit of the second universal serial bus circuit in series with the asynchronous receiving and transmitting circuit to perform data transmission. Specifically, the second universal serial bus circuit is a circuit for data transmission using a universal serial bus. The asynchronous transmitting/receiving circuit is a circuit for transmitting data using a universal asynchronous receiver/transmitter (Universal Asynchronous Receive Transmitter, UART). The UART may be used for processing serial/parallel conversion between the data bus and the serial port, and if the computer device using the UART for data transmission and the device to be tested adopt the same frame format and baud rate, the data transmission process may be completed through the transmission signal line and the reception signal line.
In general, a computer device may be switchable between a first branch and a second branch in a target circuit by a variable switch.
Alternatively, the computer device may obtain a device connection type of the device under test, where the device connection type is used to indicate a circuit test requirement for the device under test. If the circuit test requirement of the equipment to be tested is the universal serial bus circuit test requirement, determining that the equipment connection type is a universal connection type; if the circuit test requirement of the equipment to be tested is a mixed circuit test requirement, determining that the equipment connection type is a mixed connection type, wherein the mixed connection type is used for indicating that the equipment to be tested needs to perform data transmission through a universal serial bus circuit and also needs to perform data transmission through an asynchronous receiving and transmitting circuit; if the circuit test requirement of the device to be tested is an asynchronous circuit test requirement, determining that the device connection type is an asynchronous connection type. Further, if the device connection type is a general connection type, controlling the variable switch to be randomly connected to the first switch node or the second switch node; if the device connection type is a hybrid connection type or an asynchronous connection type, the variable switch is controlled to be connected to the second switch node first. Wherein the first switching node refers to a connection point between the first branch and the variable switch, such as the first switching node Z15 shown in fig. 1, and the second switching node refers to a connection point between the second branch and the variable switch, such as the second switching node Z16 shown in fig. 1. Further, a switch connection position of the variable switch may be obtained, when the variable switch is connected to the first switch node, the switch connection position indicates that the variable switch is connected to the first branch, and step S102 is performed; when the variable switch is connected to the second switch node, the switch connection position indicates that the variable switch is connected to the second branch, and step S103 is performed. Optionally, when a circuit control module exists in the target circuit, the circuit control module may control the variable switch to be connected to the first switch node or the second switch node, where the circuit control module may be an entity electrical device for controlling a communication mode of the target circuit, or may be a circuit control program integrated in the target circuit.
Step S102, if the switch connection position indicates that the variable switch is connected to the first branch, the first USB circuit is started for data transmission.
Specifically, the computer device may connect the target circuit to the first branch through the variable switch, where the first branch includes the first universal serial bus circuit, and at this time, it may be considered that if the switch connection position indicates that the variable switch is connected to the first branch, it indicates that the second branch is subjected to the disconnection process, and the first universal serial bus circuit is started, so that the current flow path in the target circuit may flow to the first universal serial bus circuit through the variable switch as shown in fig. 1, so as to implement data transmission. Optionally, because the generation of the connection instruction is not required at this time, the second branch circuit may be subjected to the disconnection process, so that the first branch circuit in the target circuit is connected, and the second branch circuit is not connected; or if the switch connection position indicates that the variable switch is connected to the first branch, controlling the first universal serial bus circuit to be communicated and controlling the first auxiliary circuit to be short-circuited so that the upper computer equipment can still be connected into the target circuit for data transmission, wherein the first auxiliary circuit is a circuit which is relatively far away from the variable switch in the second branch, such as the second universal serial bus circuit shown in fig. 1, or after the second universal serial bus circuit shown in fig. 1 is exchanged with the asynchronous transceiving transmission circuit, the first auxiliary circuit is an asynchronous transceiving transmission circuit, so that the upper computer equipment can be connected into the target circuit through the first auxiliary circuit; or if the switch connection position indicates that the variable switch is connected to the first branch, the first universal serial bus circuit is controlled to be communicated, and data transmission and the like are performed through the first universal serial bus circuit and the second universal serial bus circuit. The first universal serial bus circuit and the second universal serial bus circuit are circuits using universal serial buses, so that when the variable switch is connected to the first branch, the variable switch passes through the first universal serial bus and then passes through the second universal serial bus, and no additional influence is caused on the effect of the format circuit of data transmission.
Alternatively, the computer device may perform a control operation by a software program such that, when the current flow path reaches the second universal serial bus circuit after passing through the first universal serial bus circuit, the current flows in the second universal serial bus circuit by way of a short circuit, that is, the current does not flow through an electrical element such as a resistor of the second universal serial bus.
Step S103, if the switch connection position indicates that the variable switch is connected to the second branch, the communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit is started to transmit data based on the connection instruction.
Specifically, if the switch connection position indicates that the variable switch is connected to the second branch, a connection instruction is obtained. If the connection instruction is the first connection instruction, determining the second universal serial bus circuit in the second branch circuit as a connection circuit, starting the connection circuit to perform data transmission, for example, short-circuit processing can be performed on the asynchronous transceiving transmission circuit in the second branch circuit, so that when current passes through the second branch circuit, the current does not flow through the asynchronous transceiving transmission circuit, and data transmission based on the second universal serial bus circuit in the second branch circuit is realized; correspondingly, if the connection instruction is the second connection instruction, the asynchronous receiving and transmitting transmission circuit in the second branch is determined as a connected circuit, and the connected circuit is started to perform data transmission, for example, the second universal serial bus circuit in the second branch can be subjected to short circuit processing based on the first connection instruction, so that when current passes through the second branch, the current does not flow through the second universal serial bus circuit, and data transmission based on the asynchronous receiving and transmitting transmission circuit in the second branch is realized.
Further, the computer device may connect the device to be tested with the host device through the target circuit. Specifically, the upper computer device is connected to the target circuit through the circuit interface. Further, running a test script based on the target circuit, and automatically testing the equipment to be tested and the upper computer equipment to obtain a test result aiming at the equipment to be tested. The upper computer device may refer to a device that directly issues a control command (such as a connection command). In short, the data transmission between the upper computer device and the device to be tested can be realized through the target circuit.
Specifically, the computer device may control the communication circuit in the second branch through the connection instruction. The connection instruction may include a first connection instruction and a second connection instruction. The first connection instruction may refer to an instruction for performing data transmission by using the second universal serial bus circuit in the second branch. The corresponding second connection instruction may refer to an instruction for data transmission using an asynchronous transceiving transmission circuit in the second leg. That is, the computer device may use the second universal serial bus circuit in the second branch to perform data transmission through the first connection instruction, and correspondingly, the computer device may use the asynchronous transceiving transmission circuit in the second branch to perform data transmission through the second connection instruction. For example, in a particular embodiment, the connection instruction may be an AT (Attention) instruction. Specifically, the AT command is a command applied to connection and communication between the terminal device and the computer device. The AT command may include at=1 and at=0. Specifically, at=1 may represent that the computer device uses the second universal serial bus circuit in the second branch for data transmission, and at=0 may represent that the computer device uses the asynchronous transceiving transmission circuit in the second branch for data transmission.
In addition, if the computer equipment detects the update of the connection instruction, the communication circuit in the second branch circuit is switched based on the updated connection instruction; the updated communication circuit refers to an updated connection instruction, and the updated connection instruction is indicated in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit; and starting the updated communication circuit to transmit data. Further, for example, in a specific embodiment, when the connection command is changed from at=0 to at=1, the computer device switches from a state of using the asynchronous transceiving transmission circuit in the second branch to a state of using the second universal serial bus circuit in the second branch for data transmission.
Further, referring to fig. 4, fig. 4 is a schematic flow chart of one possible connection instruction detection according to an embodiment of the present application. As shown in fig. 4, after the detection of the connection instruction starts, the computer device may detect a switch position of the variable switch, and if the switch position is connected to the first branch, the first universal serial circuit is started to perform data transmission; correspondingly, if the switch position is connected with the second branch, the type of the connection instruction is detected. Specifically, the type of the connection instruction may include a first connection instruction and a second connection instruction. If the connection instruction is a first connection instruction (for example, at=1), the second universal serial circuit is started; if the connection command is a second connection command (e.g., at=0), the asynchronous transfer circuit is started. Further, the computer device may detect the update operation for the connection instruction, and the detailed description of detecting the update for the connection instruction is referred to above, which is not described herein.
Further, the computer device may obtain a first test result generated when the first usb circuit is started to perform data transmission. Correspondingly, the computer equipment can acquire a second test result generated when the computer equipment starts the second universal serial bus circuit to transmit data based on the connection instruction. Furthermore, the computer device can integrate the first test result and the second test result to determine the target test result of the device to be tested. The computer device may compare the first test result with the second test result, determine test result difference information and test result commonality information between the first test result and the second test result, and adjust the first test result or the second test result based on the test result difference information and the test result commonality information to obtain a general test result of the device to be tested, where the general test result is used to represent a device performance of the device to be tested when the device to be tested performs data transmission through the general serial bus, and the device performance is an object to be tested by the pointer, that is, a test object for the test script, for example, an operation speed (that is, an object to be tested is an operation speed) of the device to be tested in the process, and the device performance refers to the operation speed of the device to be tested.
Further, test configuration parameters associated with the equipment to be tested are obtained, and the test configuration parameters are sent to the upper computer equipment; the test configuration parameters are used for indicating the circuit types associated with the equipment to be tested; in the host computer device, a connection instruction is generated based on the test configuration parameters, and the connection instruction is transmitted to the target circuit through the circuit interface. Optionally, when acquiring the test configuration parameter, the specified parameter input by the user may be directly acquired, or the device connection type may be acquired, and the device connection type is determined as the test configuration parameter; and feeding the test configuration parameters back to the upper computer equipment, and generating a connection instruction by the upper computer equipment through the test configuration parameters.
Optionally, if the device connection type is a hybrid connection type, the test configuration parameter may be fed back to the host device, and the host device generates the first target connection instruction at random through the test configuration parameter, where the first target connection instruction is any one of the first connection instruction and the second connection instruction, and performs acquisition processing based on the first target connection instruction, and acquires a test result for the device to be tested. Further, when a third test result for the device to be tested, which is acquired based on the first target connection instruction, is acquired, the first target connection instruction is switched to a second target connection instruction, wherein the second target connection instruction refers to a connection instruction except the first target connection instruction, among the first connection instruction and the second connection instruction, and acquisition processing is performed based on the second target connection instruction, so that a fourth test result for the device to be tested is acquired. Meanwhile, the computer device may compare the third test result with the fourth test result, determine an influence of the circuit type on the device under test, and determine performance parameters of a test object for the device under test, where the test object refers to an object for which the test script is aimed in the device under test, and includes, but is not limited to, an operation speed, a data transmission rate, and data processing accuracy.
It should be appreciated that embodiments of the present application provide a data processing system that includes a variable switch, a target circuit, and a host device. The target circuit comprises a first branch and a second branch, and the first branch is connected with the second branch in parallel. Specifically, the first branch circuit comprises a first universal serial bus circuit, the second branch circuit comprises a second universal serial bus circuit and an asynchronous receiving and transmitting transmission circuit, and the second universal serial bus circuit is connected with the asynchronous receiving and transmitting transmission circuit in series. The variable switch is used for starting the first universal serial bus circuit to transmit data when being connected to the first branch circuit. In addition, the variable switch is further used for starting a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit to transmit data based on the connection instruction when the variable switch is connected to the second branch circuit. The upper computer equipment is connected to the target circuit through the circuit interface and used for generating a connection instruction.
According to the embodiment of the application, the first branch circuit and the second branch circuit are connected in parallel, so that different types of circuits at a hardware level are fused. Further, by connecting the second universal serial bus circuit in series with the asynchronous transceiving transmission circuit, the second universal serial bus circuit and the asynchronous transceiving transmission circuit can be selected, and further, the data transmission using different circuits can be controlled. The second universal serial bus circuit and the asynchronous receiving and transmitting transmission circuit are connected in series to one circuit, and the switching of the second universal serial bus circuit and the asynchronous receiving and transmitting transmission circuit is controlled through a connection instruction, so that the universality of the circuit and the flexibility of circuit switching can be improved, the time of circuit switching is saved, the flow of circuit switching is greatly reduced, and the testing efficiency is further improved.
Further, referring to fig. 5, fig. 5 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application. The data processing means may be a computer program (comprising program code) running in a computer device, for example the data processing means is an application software; the device can be used for executing corresponding steps in the method provided by the embodiment of the application. As shown in fig. 5, the data processing apparatus 1 may include: a position acquisition module 11, a first data transmission module 12 and a second data transmission module 13.
A position acquisition module 11 for acquiring a switch connection position of a variable switch in a target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series;
a first data transmission module 12, configured to start the first usb circuit for data transmission if the switch connection position indicates that the variable switch is connected to the first branch;
and the second data transmission module 13 is configured to, if the switch connection position indicates that the variable switch is connected to the second branch, start the connection circuit of the second universal serial bus circuit and the asynchronous transceiving transmission circuit based on the connection instruction, and perform data transmission.
The specific functional implementation manners of the position obtaining module 11, the first data transmission module 12, and the second data transmission module 13 may be referred to step S101-step S103 in the corresponding embodiment of fig. 3, which are not described herein.
Referring again to fig. 5, the second data transmission module 13 includes:
an instruction obtaining unit 131, configured to obtain a connection instruction if the switch connection position indicates that the variable switch is connected to the second branch;
the first data transmission unit 132 is configured to determine the second universal serial bus circuit in the second branch circuit as a connection circuit if the connection instruction is the first connection instruction, and start the connection circuit to perform data transmission;
and the second data transmission unit 133 is configured to determine the asynchronous receiving and transmitting circuit in the second branch circuit as a connected circuit if the connection instruction is the second connection instruction, and start the connected circuit to perform data transmission.
The specific functional implementation manner of the instruction obtaining unit 131, the first data transmitting unit 132, and the second data transmitting unit 133 may refer to step S103 in the corresponding embodiment of fig. 3, and will not be described herein.
Referring again to fig. 5, the data processing apparatus 1 further includes:
The connection module 14 is used for connecting the device to be tested with the upper computer device through the target circuit; the upper computer equipment is connected to the target circuit through a circuit interface;
and the test module 15 is used for running a test script based on the target circuit and automatically testing the equipment to be tested and the upper computer equipment.
The specific functional implementation manner of the connection module 14 and the test module 15 may refer to step S101 in the corresponding embodiment of fig. 3, which is not described herein.
Referring again to fig. 5, the data processing apparatus 1 further includes:
an updating module 16, configured to switch the connection circuit in the second branch based on the updated connection instruction if the update for the connection instruction is detected; the updated communication circuit refers to an updated connection instruction, and the updated connection instruction is indicated in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit;
and the third data transmission module 17 is used for starting the updated connected circuit to perform data transmission.
The specific functional implementation manner of the updating module 16 and the third data transmission module 17 may refer to step S101 in the corresponding embodiment of fig. 3, and will not be described herein.
Referring again to fig. 5, the data processing apparatus 1 further includes:
a first result obtaining module 18, configured to obtain a first test result generated when the first usb circuit is started to perform data transmission, for the device to be tested;
a second result obtaining module 19, configured to obtain a second test result generated when the device to be tested starts the second universal serial bus circuit to perform data transmission based on the connection instruction;
the result integrating module 20 is configured to integrate the first test result and the second test result to determine a target test result of the device under test.
The specific functional implementation manner of the first result obtaining module 18, the second result obtaining module 19, and the result integrating module 20 may refer to step S101 in the corresponding embodiment of fig. 3, and will not be described herein.
Referring again to fig. 5, the data processing apparatus 1 further includes:
the parameter obtaining module 21 is configured to obtain a test configuration parameter associated with the device to be tested, and send the test configuration parameter to the host computer device; the test configuration parameters are used for indicating the circuit types associated with the equipment to be tested;
the instruction transmission module 22 is configured to generate a connection instruction in the host device based on the test configuration parameter, and transmit the connection instruction to the target circuit through the circuit interface.
The specific functional implementation manner of the parameter obtaining module 21 and the instruction transmitting module 22 may refer to step S101 in the corresponding embodiment of fig. 3, and will not be described herein.
Further, referring to fig. 6, fig. 6 is a schematic structural diagram of a circuit switching system according to an embodiment of the present application. The circuit switching system 3 can be used for performing circuit switching between a first branch 32 including a first universal serial bus circuit 321 and a second branch 33 including a second universal serial bus circuit 332 and an asynchronous transceiving transmission circuit 331, and comprises a variable switch 31, a target circuit and a host device.
The target circuit comprises a first branch circuit 32 and a second branch circuit 33, wherein the first branch circuit 32 is connected with the second branch circuit 33 in parallel; the first branch 32 includes a first universal serial bus circuit 321, the second branch 33 includes a second universal serial bus circuit 332 and an asynchronous transceiving transmission circuit 331, and the second universal serial bus circuit 332 is connected in series with the asynchronous transceiving transmission circuit 331;
specifically, the variable switch 31 is configured to activate the first usb circuit 321 when connected to the first branch 32, so as to perform data transmission; the variable switch 31 is further configured to, when connected to the second branch 33, activate, based on the connection instruction, a communication circuit of the second universal serial bus circuit 332 and the asynchronous transceiving transmission circuit 331 for data transmission;
The upper computer equipment is connected to the target circuit through the circuit interface and used for generating a connection instruction.
Further, referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present application. As shown in fig. 7, the computer device 1000 may include: at least one processor 1001, such as a CPU, at least one network interface 1004, a user interface 1003, a memory 1005, at least one communication bus 1002. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display (Display), a Keyboard (Keyboard), and the network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others. The memory 1005 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 1005 may also optionally be at least one storage device located remotely from the aforementioned processor 1001. As shown in fig. 7, the memory 1005, which is one type of computer storage medium, may include an operating system, a network communication module, a user interface module, and a device control application.
In the computer device 1000 shown in FIG. 7, the network interface 1004 may provide network communication functions; while user interface 1003 is primarily used as an interface for providing input to a user; and the processor 1001 may be used to invoke a device control application stored in the memory 1005 to implement:
creating a game pair comprising intelligent virtual characters, the intelligent virtual characters using virtual shooting equipment in the game pair; when a game shooting request aiming at the intelligent virtual character is acquired, and the current game state of the intelligent virtual character is detected to be in accordance with game shooting conditions according to the game shooting request, acquiring shooting stable operation parameters, and controlling the intelligent virtual character to operate virtual shooting equipment to execute shooting actions according to the shooting stable operation parameters; counting shooting evaluation data generated based on shooting actions, and adjusting shooting stable operation parameters through the shooting evaluation data to obtain target shooting stable operation parameters; the target firing stabilization operating parameter is used to provide a stable firing state for the virtual firing equipment during the firing performance test.
It should be understood that the computer device 1000 described in the embodiments of the present application may perform the description of the data processing method in the embodiments corresponding to fig. 2, 3 and 4, the description of the data processing apparatus 1 in the embodiment corresponding to fig. 5, and the description of the circuit switching system 3 in the embodiment corresponding to fig. 6, which are not repeated herein. In addition, the description of the beneficial effects of the same method is omitted.
The embodiment of the present application further provides a computer readable storage medium, where the computer readable storage medium stores a computer program, where the computer program includes program instructions, and when executed by a processor, implement the data processing method provided by each step in fig. 2, fig. 3, and fig. 4, and specifically refer to the implementation manner provided by each step in fig. 2, fig. 3, and fig. 4, which is not repeated herein. In addition, the description of the beneficial effects of the same method is omitted.
The computer readable storage medium may be the data processing apparatus provided in any one of the foregoing embodiments or an internal storage unit of the computer device, for example, a hard disk or a memory of the computer device. The computer readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card (flash card) or the like, which are provided on the computer device. Further, the computer-readable storage medium may also include both internal storage units and external storage devices of the computer device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.
Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device can execute the description of the data processing method in the embodiments corresponding to fig. 2, 3 and 4, which are not described herein. In addition, the description of the beneficial effects of the same method is omitted.
The term "comprising" and any variations thereof in the description of the embodiments of the present application and in the claims and drawings is intended to cover a non-exclusive inclusion. For example, a process, method, apparatus, article, or device that comprises a list of steps or elements is not limited to the list of steps or modules but may, in the alternative, include other steps or modules not listed or inherent to such process, method, apparatus, article, or device.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The methods and related devices provided in the embodiments of the present application are described with reference to the method flowcharts and/or structure diagrams provided in the embodiments of the present application, and each flowchart and/or block of the method flowcharts and/or structure diagrams may be implemented by computer program instructions, and combinations of flowcharts and/or blocks in the flowchart and/or block diagrams. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or structural diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or structures.
The foregoing disclosure is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the claims herein, as the equivalent of the claims herein shall be construed to fall within the scope of the claims herein.

Claims (10)

1. A method of data processing, comprising:
acquiring a switch connection position of a variable switch in a target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series;
if the switch connection position indicates that the variable switch is connected to the first branch, starting the first universal serial bus circuit to perform data transmission;
and if the switch connection position indicates that the variable switch is connected to the second branch circuit, starting a communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit based on a connection instruction to perform data transmission.
2. The method of claim 1, wherein if the switch connection position indicates that the variable switch is connected to the second branch, starting the second universal serial bus circuit to communicate with the communication circuit in the asynchronous transceiving circuit based on a connection instruction, comprising:
If the switch connection position indicates that the variable switch is connected to the second branch, a connection instruction is acquired;
if the connection instruction is a first connection instruction, determining a second universal serial bus circuit in the second branch circuit as a communication circuit, starting the communication circuit, and carrying out data transmission;
and if the connection instruction is a second connection instruction, determining an asynchronous receiving and transmitting transmission circuit in the second branch circuit as a communication circuit, starting the communication circuit, and carrying out data transmission.
3. The method as recited in claim 1, further comprising:
connecting the equipment to be tested with the upper computer equipment through the target circuit; the upper computer equipment is connected to the target circuit through a circuit interface;
and running a test script based on the target circuit, and automatically testing the equipment to be tested and the upper computer equipment.
4. The method as recited in claim 1, further comprising:
if the update of the connection instruction is detected, switching the communication circuit in the second branch circuit based on the updated connection instruction; the updated communication circuit refers to the updated connection instruction, and the circuit is indicated in the second universal serial bus circuit and the asynchronous receiving and transmitting transmission circuit;
And starting the updated communication circuit to transmit data.
5. The method of claim 1, wherein the method further comprises:
acquiring a first test result generated when the first universal serial bus circuit is started to transmit data of the equipment to be tested;
acquiring a second test result generated when the device to be tested starts the second universal serial bus circuit to transmit data based on a connection instruction;
and integrating the first test result and the second test result to determine a target test result of the device to be tested.
6. A method as claimed in claim 3, wherein the method further comprises:
acquiring test configuration parameters associated with the equipment to be tested, and sending the test configuration parameters to the upper computer equipment; the test configuration parameters are used for indicating the circuit type associated with the equipment to be tested;
and generating the connection instruction based on the test configuration parameters in the upper computer equipment, and transmitting the connection instruction to the target circuit through the circuit interface.
7. A data processing system, wherein the system comprises a variable switch, a target circuit and an upper computer device; the target circuit comprises a first branch and a second branch, and the first branch is connected with the second branch in parallel; the first branch comprises a first universal serial bus circuit, the second branch comprises a second universal serial bus circuit and an asynchronous receiving and transmitting transmission circuit, and the second universal serial bus circuit is connected with the asynchronous receiving and transmitting transmission circuit in series;
The variable switch is used for starting the first universal serial bus circuit to transmit data when being connected to the first branch circuit;
the variable switch is further configured to, when connected to the second branch, start a communication circuit in the second universal serial bus circuit and the asynchronous transceiving transmission circuit based on a connection instruction, and perform data transmission;
the upper computer equipment is connected to the target circuit through a circuit interface and is used for generating a connection instruction.
8. A data processing apparatus, comprising:
the position acquisition module is used for acquiring the switch connection position of the variable switch in the target circuit; the target circuit comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the second branch circuit in parallel, and the first branch circuit comprises a first universal serial bus circuit; the second branch is formed by connecting a second universal serial bus circuit with an asynchronous receiving and transmitting transmission circuit in series;
the first data transmission module is used for starting the first universal serial bus circuit to perform data transmission if the switch connection position indicates that the variable switch is connected to the first branch circuit;
and the second data transmission module is used for starting the communication circuit in the second universal serial bus circuit and the asynchronous receiving and transmitting circuit to perform data transmission based on a connection instruction if the switch connection position indicates that the variable switch is connected to the second branch circuit.
9. A computer device, comprising: a processor, a memory, and a network interface;
the processor is connected to a memory, a network interface for providing data communication functions, the memory for storing a computer program, the processor for invoking the computer program to cause the computer device to perform the method of any of claims 1-7.
10. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, which computer program is adapted to be loaded and executed by a processor to cause a computer device with a processor to perform the method of any of claims 1-7.
CN202310175423.6A 2023-02-27 2023-02-27 Data processing method, device, equipment and storage medium Pending CN116150069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310175423.6A CN116150069A (en) 2023-02-27 2023-02-27 Data processing method, device, equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310175423.6A CN116150069A (en) 2023-02-27 2023-02-27 Data processing method, device, equipment and storage medium

Publications (1)

Publication Number Publication Date
CN116150069A true CN116150069A (en) 2023-05-23

Family

ID=86356156

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310175423.6A Pending CN116150069A (en) 2023-02-27 2023-02-27 Data processing method, device, equipment and storage medium

Country Status (1)

Country Link
CN (1) CN116150069A (en)

Similar Documents

Publication Publication Date Title
CN108270883B (en) Can automatic dispensing device address code method, breaker and storage medium
CN105282583B (en) A kind of remote controler intelligent Matching system and implementation method
CN102932695A (en) Remote control method, intelligent terminal and intelligent remote control system
CN215897719U (en) SIM card switching device and electronic equipment
EP3477997B1 (en) Method for controlling data transmission, device, and storage medium
KR101588993B1 (en) Protocol translating adapter
CN109362121A (en) Sharing method, device, storage medium and the terminal of WLAN
CN106416196B (en) Mobile terminal, power adapter and upgrading method thereof
CN112491102B (en) Single-wire communication method and related product
CN112269086A (en) Charging cable identification method and device, charging cable and readable storage medium
JP4393014B2 (en) Transmission apparatus and transmission method
KR20210017030A (en) Electronic device for reducing power consumption and operating method thereof
CN104242998A (en) Method and system for fast sharing various types of information through magnetic sensor
US20230378767A1 (en) Charging control method and apparatus, electronic device, and charger
CN106407018B (en) Method and device for synchronizing personalized data and mobile terminal
US10356828B2 (en) Method for controlling a wireless access device using channel avoidance between processors of the wireless access device
CN116150069A (en) Data processing method, device, equipment and storage medium
CN106488537B (en) Sending method, device and mobile terminal
CN108377515A (en) Wireless network transmissions method of rate control, device, terminal device and storage medium
US20170201111A1 (en) Method for Outputting Charging Current and Power Amplifier
CN108366396A (en) Wireless network transmissions method of rate control, device, terminal device and storage medium
US11330651B2 (en) Electronic device using bluetooth communication and operating method thereof
JPH09331370A (en) Data communication equipment
CN108701104A (en) Data transmission system, projecting apparatus and data transmission method
CN112702083B (en) Electronic device and communication method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination